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Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
#
# README
#
BSP NAME: gen5200
BOARD: various boards based on MPC5200 Controller:
MicroSys PM520 with Carrier board CR825
BUS: N/A
CPU FAMILY: ppc
CPU: PowerPC MPC5200
COPROCESSORS: Hardware FPU
MODE: 32 bit mode, I and D cache enabled
DEBUG MONITOR: None
PERIPHERALS
===========
TIMERS: GPT
SERIAL PORTS: 3 PSCs
2 CAN IFs
1 I2C IF
REAL-TIME CLOCK: PCF8563
DMA: for Ethernet and CompactFlash
VIDEO: none
SCSI: none
IDE: 1 CompactFlash Slot supported
NETWORKING: 1 FEC Fast Ethernet
DRIVER INFORMATION
==================
CLOCK DRIVER: using one GPT
IOSUPP DRIVER: none
SHMSUPP: none
TIMER DRIVER: Timebase register (lower 32 bits only)
STDIO
=====
PORT: PSC1
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
On-chip resources:
PSC1 /dev/console /dev/tty00
PSC2 /dev/tty01
PSC3 /dev/tty02
Board description
-----------------
Clock rate: external clock: 33MHz
Bus width: 32 bit Flash, 32 bit SDRAM
FLASH: 8MByte
RAM: 64MByte SDRAM
Debugging/ Code loading:
------------------------
Tested using the Lauterbach TRACE32 ICD debugger.