mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-03 06:07:21 +08:00
Kinsey Moore
8a2c3af9cf
This fixes some issues in the Xilinx support code that are critical to support the Cortex-R5F cores present in my Xilinx SoCs. The imported Cortex-R5 xil_cache.c matches the existing information in bsps/shared/xil/VERSION.
3 lines
82 B
C
3 lines
82 B
C
/* Minimal stub file for Xilinx driver compatibility. */
|
|
#define xdbg_printf(...)
|