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https://gitlab.rtems.org/rtems/rtos/rtems.git
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Sebastian Huber
bc7e6ae550
Make the GIC interrupt controller support a subgroup of the generic interrupt controller support.
89 lines
2.6 KiB
C
89 lines
2.6 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup DevIRQGIC
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*
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* @brief This header file provides interfaces of the ARM Generic Interrupt
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* Controller (GIC) support specific to the AArch64 architecture.
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*/
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/*
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* Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
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* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
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#define _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H
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#include <rtems/score/cpu.h>
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#include <rtems/score/cpu_irq.h>
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#include <bsp/irq-generic.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @addtogroup DevIRQGIC
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*
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* @{
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*/
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static inline uint32_t arm_interrupt_enable_interrupts(void)
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{
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uint32_t status = _CPU_ISR_Get_level();
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/* Enable interrupts for nesting */
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_CPU_ISR_Set_level(0);
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return status;
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}
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static inline void arm_interrupt_restore_interrupts(uint32_t status)
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{
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/* Restore interrupts to previous level */
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_CPU_ISR_Set_level(status);
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}
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static inline void arm_interrupt_facility_set_exception_handler(void)
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{
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AArch64_set_exception_handler(
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AARCH64_EXCEPTION_SPx_IRQ,
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_AArch64_Exception_interrupt_no_nest
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);
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AArch64_set_exception_handler(
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AARCH64_EXCEPTION_SP0_IRQ,
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_AArch64_Exception_interrupt_nest
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);
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}
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTEMS_DEV_IRQ_ARM_GIC_AARCH64_H */
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