Matteo Concas 8820b8e63f grlib/b1553rt: Fix bit shift direction ...

The RT_TSW_OK field is set to 1 if there was no error. The Message Error
(ME) field indicates an error and must be set to 0 if there was no error
so the result of tsw&RT_TSW_OK must be negated. It is then left-shifted
to the Messsage Error (ME) bit field of the message information word.

Fix issue CID 1399772

2024-10-29 13:25:14 +00:00

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acpi

ACPICA: Add file for chosen ACPICA license

2024-08-06 21:28:15 +00:00

cache

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dev

bsps: Remove imported Xilinx headers

2024-10-28 19:23:49 +00:00

freebsd

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grlib

grlib/b1553rt: Fix bit shift direction

2024-10-29 13:25:14 +00:00

irq

dev/irq: Add BSP_IRQ_HAVE_GET_SET_AFFINITY

2024-10-02 05:24:30 +02:00

ofw

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shmdr

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start

bsps: Assembly implementation for PSCI bsp_reset()

2024-10-11 01:27:48 +02:00

doxygen.h

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rtems-version.c

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