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8e6ded473c
This is an update of many lingering embedded brains GmbH licenses from the RTEMS License to the 2-BSD license where possible depending on the joint copyrights. Updates #3053.
92 lines
3.0 KiB
C
92 lines
3.0 KiB
C
/**
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* @file
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*
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* @ingroup csb337_interrupt
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*
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* @brief Interrupt Support.
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*/
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/*
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* Copyright (C) 2010 embedded brains GmbH & Co. KG
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* Copyright (C) 2004 by Jay Monkman <jtm@lopingdog.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __IRQ_H__
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#define __IRQ_H__
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#ifndef __asm__
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#include <rtems.h>
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#include <rtems/irq.h>
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#include <rtems/irq-extension.h>
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#endif /* __asm__ */
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/**
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* @defgroup csb337_interrupt Interrrupt Support
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*
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* @ingroup RTEMSBSPsARMCSB337
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*
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* @brief Interrupt Support.
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*/
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/* possible interrupt sources on the AT91RM9200 */
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#define AT91RM9200_INT_FIQ 0
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#define AT91RM9200_INT_SYSIRQ 1
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#define AT91RM9200_INT_PIOA 2
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#define AT91RM9200_INT_PIOB 3
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#define AT91RM9200_INT_PIOC 4
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#define AT91RM9200_INT_PIOD 5
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#define AT91RM9200_INT_US0 6
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#define AT91RM9200_INT_US1 7
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#define AT91RM9200_INT_US2 8
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#define AT91RM9200_INT_US3 9
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#define AT91RM9200_INT_MCI 10
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#define AT91RM9200_INT_UDP 11
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#define AT91RM9200_INT_TWI 12
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#define AT91RM9200_INT_SPI 13
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#define AT91RM9200_INT_SSC0 14
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#define AT91RM9200_INT_SSC1 15
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#define AT91RM9200_INT_SSC2 16
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#define AT91RM9200_INT_TC0 17
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#define AT91RM9200_INT_TC1 18
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#define AT91RM9200_INT_TC2 19
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#define AT91RM9200_INT_TC3 20
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#define AT91RM9200_INT_TC4 21
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#define AT91RM9200_INT_TC5 22
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#define AT91RM9200_INT_UHP 23
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#define AT91RM9200_INT_EMAC 24
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#define AT91RM9200_INT_IRQ0 25
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#define AT91RM9200_INT_IRQ1 26
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#define AT91RM9200_INT_IRQ2 27
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#define AT91RM9200_INT_IRQ3 28
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#define AT91RM9200_INT_IRQ4 28
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#define AT91RM9200_INT_IRQ5 30
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#define AT91RM9200_INT_IRQ6 31
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#define AT91RM9200_MAX_INT 32
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#define BSP_INTERRUPT_VECTOR_COUNT AT91RM9200_MAX_INT
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#endif /* __IRQ_H__ */
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