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8a2c3af9cf
This fixes some issues in the Xilinx support code that are critical to support the Cortex-R5F cores present in my Xilinx SoCs. The imported Cortex-R5 xil_cache.c matches the existing information in bsps/shared/xil/VERSION.
3 lines
82 B
C
3 lines
82 B
C
/* Minimal stub file for Xilinx driver compatibility. */
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#define xdbg_printf(...)
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