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mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2026-10-06 10:59:48 +08:00
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rtems/spec/build/bsps/riscv
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Gedare Bloom f29da813de riscv: set defaults for RISCV_MMU_VIRTUAL_ADDRESS_BITS
Use 32 for rv32 ABI and otherwise use 39 bit virtual addresses.

Fixes #5630
2026-08-14 12:21:38 -06:00
..
esp32
riscv: Add basic ESP32-C3 BSP
2026-04-07 14:52:50 -05:00
griscv
…
niosv
spec/riscv: Allow BSS to be specified independent of DATA
2026-04-07 14:52:50 -05:00
noel
bsps/noel: Fix build
2026-06-23 14:28:46 +02:00
riscv
riscv: set defaults for RISCV_MMU_VIRTUAL_ADDRESS_BITS
2026-08-14 12:21:38 -06:00
grp.yml
riscv/riscv: refactor FDT helper functions
2026-03-18 12:44:46 -06:00
linkcmds.yml
spec/riscv: Allow BSS to be specified independent of DATA
2026-04-07 14:52:50 -05:00
linkcmdsbase.yml
spec/riscv: Allow BSS to be specified independent of DATA
2026-04-07 14:52:50 -05:00
objsbi.yml
riscv/sbi: Correct path
2026-03-20 10:31:46 +01:00
optbspstartcopysections.yml
riscv: Add optional section copy callback
2026-04-07 14:52:50 -05:00
optespressifdirectboot.yml
riscv: Add support for Espressif Direct Boot
2026-04-07 14:52:50 -05:00
optextirqmax.yml
…
optrambegin.yml
…
optramsize.yml
…
optriscvmmuvirtualaddressbits.yml
riscv: set defaults for RISCV_MMU_VIRTUAL_ADDRESS_BITS
2026-08-14 12:21:38 -06:00
start.yml
…
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