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b714e4a809f1c0e9169575cdf9ac5af8b73d6803
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8 Commits

Author SHA1 Message Date
Amar Takhar
b714e4a809 ascii: Remove non-ASCII characters 
We will soon be enforcing ASCII-only characters for source.
 2025-05-22 19:35:12 +00:00
Sebastian Huber
c4c3e68790 bsps/arm: Use fatal error for data cache disable 
On the Cortex-A cores, at least the L1 data cache is required to provide
support for atomic operations.

Close #5050.
 2024-06-25 03:58:34 +00:00
Sebastian Huber
3a281aca37 bsps/arm: Fix L2C-310 instruction enabled/disable 
Set/clear SCTLR[I] on all online processors.  Do not enable/disable the
L2C-310 cache in the instruction cache enable/disable since it is a
unified cache.
 2024-06-25 03:58:34 +00:00
Sebastian Huber
ef9b49dc24 bsps/arm: Fix Doxygen group placement 2024-06-25 03:58:34 +00:00
Sebastian Huber
f69326d0c2 bsps: Improve Doxygen file comments 2023-05-26 06:56:11 +02:00
Sebastian Huber
828276b081 bsps: Adjust shared Doxygen groups 
Update #3706.
 2019-03-08 07:42:54 +01:00
Sebastian Huber
ba856559a4 ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS 
Remove this superfluous define.

Update #3667.
 2018-12-21 10:32:25 +01:00
Sebastian Huber
4cf93658ef bsps: Rework cache manager implementation 
The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file.  Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

* bsps/shared/cache

* bsps/@RTEMS_CPU@/shared/cache

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.
 2018-01-31 12:49:09 +01:00