tm02 and tm03 were modified to be reused for multiple configurations
of RTEMS Classic API Semaphores. This added tm31-36. The messages for
tm02 and tm03 were modified to indicate the semaphore attributes.
tm31 - tm36 were added. This resulted in the following cases:
tm02 - rtems_semaphore_obtain: Counting/FIFO not available caller blocks
tm03 - rtems_semaphore_release: Counting/FIFO task readied preempts caller
tm31 - rtems_semaphore_obtain: Counting/priority not available caller blocks
tm32 - rtems_semaphore_release: Counting/priority task readied preempts caller
tm33 - rtems_semaphore_obtain: Binary/FIFO not available caller blocks
tm34 - rtems_semaphore_release: Binary/FIFO task readied preempts caller
tm35 - rtems_semaphore_obtain: Binary/priority not available caller blocks
tm36 - rtems_semaphore_release: Binary/priority task readied preempts caller
The current implementation of task migration in RTEMS has some
implications with respect to the interrupt latency. It is crucial to
preserve the system invariant that a task can execute on at most one
processor in the system at a time. This is accomplished with a boolean
indicator in the task context. The processor architecture specific
low-level task context switch code will mark that a task context is no
longer executing and waits that the heir context stopped execution
before it restores the heir context and resumes execution of the heir
task. So there is one point in time in which a processor is without a
task. This is essential to avoid cyclic dependencies in case multiple
tasks migrate at once. Otherwise some supervising entity is necessary to
prevent life-locks. Such a global supervisor would lead to scalability
problems so this approach is not used. Currently the thread dispatch is
performed with interrupts disabled. So in case the heir task is
currently executing on another processor then this prolongs the time of
disabled interrupts since one processor has to wait for another
processor to make progress.
It is difficult to avoid this issue with the interrupt latency since
interrupts normally store the context of the interrupted task on its
stack. In case a task is marked as not executing we must not use its
task stack to store such an interrupt context. We cannot use the heir
stack before it stopped execution on another processor. So if we enable
interrupts during this transition we have to provide an alternative task
independent stack for this time frame. This issue needs further
investigation.
Provide a file per BSP to list tests that do not build for a BSP. This change
removes the BSP_SMALL_MEMORY hack from the code. That hack was a
mistake.
Provide configuration files for each BSP with tests that cannot build.
Do not allocate the scheduler control structures from the workspace.
This is a preparation step for configuration of clustered/partitioned
schedulers on SMP.
Rename rtems_smp_get_processor_count() in rtems_get_processor_count().
Make rtems_get_processor_count() a function in uni-processor
configurations to enable ABI compatibility with SMP configurations.
Delete global variables _Priority_Major_bit_map and _Priority_Bit_map.
This makes it possible to use multiple priority scheduler instances for
example with clustered/partitioned scheduling on SMP.
Add a local context structure to the SMP lock API for acquire and
release pairs. This context can be used to store the ISR level and
profiling information. It may be later used to enable more
sophisticated lock algorithms, e.g. MCS locks.
There is only one lock that cannot be used with a local context. This
is the per-CPU lock since here we would have to transfer the local
context through a context switch which is very complicated.
Add and use _ISR_Disable_without_giant() and
_ISR_Enable_without_giant() if RTEMS_SMP is defined.
On single processor systems the ISR disable/enable was the big hammer
which ensured system-wide mutual exclusion. On SMP configurations this
no longer works since other processors do not care about disabled
interrupts on this processor and continue to execute freely.
On SMP in addition to ISR disable/enable an SMP lock must be used.
Currently we have only the Giant lock so we can check easily that ISR
disable/enable is used only in the right context.
Use a per-CPU thread dispatch disable level. So instead of one global
thread dispatch disable level we have now one instance per processor.
This is a major performance improvement for SMP. On non-SMP
configurations this may simplifiy the interrupt entry/exit code.
The giant lock is still present, but it is now decoupled from the thread
dispatching in _Thread_Dispatch(), _Thread_Handler(),
_Thread_Restart_self() and the interrupt entry/exit. Access to the
giant lock is now available via _Giant_Acquire() and _Giant_Release().
The giant lock is still implicitly acquired via
_Thread_Dispatch_decrement_disable_level().
The giant lock is only acquired for high-level operations in interrupt
handlers (e.g. release of a semaphore, sending of an event).
As a side-effect this change fixes the lost thread dispatch necessary
indication bug in _Thread_Dispatch().
A per-CPU thread dispatch disable level greatly simplifies the SMP
support for the interrupt entry/exit code since no spin locks have to be
acquired in this area. It is only necessary to get the current
processor index and use this to calculate the address of the own per-CPU
control. This reduces the interrupt latency considerably.
All elements for the interrupt entry/exit code are now part of the
Per_CPU_Control structure: thread dispatch disable level, ISR nest level
and thread dispatch necessary. Nothing else is required (except CPU
port specific stuff like on SPARC).
This commit deletes all RTEMS ChangeLog files. These files have been abandoned
since converting to git version control. The historical data may be recovered
by checking out any commit before this one. Most of the contents of these
ChangeLog files can also be found in the git log.
Two external ChangeLog files, ChangeLog.slac and ChangeLog.zlib, remain.
Script does what is expected and tries to do it as
smartly as possible.
+ remove occurrences of two blank comment lines
next to each other after Id string line removed.
+ remove entire comment blocks which only exited to
contain CVS Ids
+ If the processing left a blank line at the top of
a file, it was removed.
Sebastian Huber
Joel Sherrill
Chris Johns
bjorn larsson
Cynthia Rempel
Daniel Ramirez
Gedare Bloom
Ralf Corsépius