From eb8a39e11587c46a5b2e1a6d7f01c3e110d2d279 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 28 Aug 2024 04:19:39 +0200 Subject: [PATCH] arm: Simplify default exception handling Writes to the execution state bits of the CPSR through MRS instructions are ignored. --- cpukit/score/cpu/arm/armv4-exception-default.S | 1 - 1 file changed, 1 deletion(-) diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S index c2de20dc5a..a8a774889c 100644 --- a/cpukit/score/cpu/arm/armv4-exception-default.S +++ b/cpukit/score/cpu/arm/armv4-exception-default.S @@ -103,7 +103,6 @@ save_more_context: mrs r3, spsr mrs r7, cpsr orr r5, r5, r3 - bic r5, #ARM_PSR_T msr cpsr, r5 mov r0, sp mov r1, lr