diff --git a/bsps/arm/altera-cyclone-v/start/bspsmp.c b/bsps/arm/altera-cyclone-v/start/bspsmp.c
index a6a322308d..290cf651a4 100644
--- a/bsps/arm/altera-cyclone-v/start/bspsmp.c
+++ b/bsps/arm/altera-cyclone-v/start/bspsmp.c
@@ -31,9 +31,10 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <rtems/score/smpimpl.h>
+#include <rtems/score/cpu.h>
 
 #include <bsp/start.h>
+#include <rtems/score/assert.h>
 
 #include <bsp/socal/alt_rstmgr.h>
 #include <bsp/socal/alt_sysmgr.h>
@@ -42,27 +43,17 @@
 
 bool _CPU_SMP_Start_processor(uint32_t cpu_index)
 {
-  bool started;
+  _Assert(cpu_index == 1);
 
-  if (cpu_index == 1) {
-    alt_write_word(
-      ALT_SYSMGR_ROMCODE_ADDR + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST,
-      ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET((uint32_t) _start)
-    );
+  alt_write_word(
+    ALT_SYSMGR_ROMCODE_ADDR + ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST,
+    ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET((uint32_t) _start)
+  );
 
-    alt_clrbits_word(
-      ALT_RSTMGR_MPUMODRST_ADDR,
-      ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK
-    );
+  alt_clrbits_word(
+    ALT_RSTMGR_MPUMODRST_ADDR,
+    ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK
+  );
 
-    /*
-     * Wait for secondary processor to complete its basic initialization so
-     * that we can enable the unified L2 cache.
-     */
-    started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
-  } else {
-    started = false;
-  }
-
-  return started;
+  return true;
 }
diff --git a/bsps/arm/shared/start/arm-a9mpcore-smp.c b/bsps/arm/shared/start/arm-a9mpcore-smp.c
index 11c44c403c..bfd6c465be 100644
--- a/bsps/arm/shared/start/arm-a9mpcore-smp.c
+++ b/bsps/arm/shared/start/arm-a9mpcore-smp.c
@@ -60,7 +60,11 @@ void _CPU_SMP_Finalize_initialization(uint32_t cpu_count)
   _Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL);
 
 #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
-  /* Enable unified L2 cache */
+  /*
+   * When all secondary processors are ready to start multitasking, enable the
+   * unified L2 cache.
+   */
+  _SMP_Wait_for_ready_to_start_multitasking();
   rtems_cache_enable_data();
 #endif
 }
diff --git a/bsps/arm/xilinx-zynq/start/bspsmp.c b/bsps/arm/xilinx-zynq/start/bspsmp.c
index 294acb0083..e287e60160 100644
--- a/bsps/arm/xilinx-zynq/start/bspsmp.c
+++ b/bsps/arm/xilinx-zynq/start/bspsmp.c
@@ -25,28 +25,26 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <rtems/score/smpimpl.h>
+#include <rtems/score/cpu.h>
 
 #include <bsp/start.h>
+#include <rtems/score/assert.h>
 
 bool _CPU_SMP_Start_processor(uint32_t cpu_index)
 {
+  volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL;
+
+  _Assert(cpu_index == 1);
+
   /*
    * Enable the second CPU.
    */
-  if (cpu_index != 0) {
-    volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL;
-    _ARM_Data_synchronization_barrier();
-    _ARM_Instruction_synchronization_barrier();
-    *kick_address = (uint32_t) _start;
-    _ARM_Data_synchronization_barrier();
-    _ARM_Instruction_synchronization_barrier();
-    _ARM_Send_event();
-  }
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
+  *kick_address = (uint32_t) _start;
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
+  _ARM_Send_event();
 
-  /*
-   * Wait for secondary processor to complete its basic initialization so that
-   * we can enable the unified L2 cache.
-   */
-  return _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
+  return true;
 }
diff --git a/bsps/arm/xilinx-zynqmp/start/bspsmp.c b/bsps/arm/xilinx-zynqmp/start/bspsmp.c
index dce6a9b45c..e8b287ce06 100644
--- a/bsps/arm/xilinx-zynqmp/start/bspsmp.c
+++ b/bsps/arm/xilinx-zynqmp/start/bspsmp.c
@@ -30,28 +30,26 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <rtems/score/smpimpl.h>
+#include <rtems/score/cpu.h>
 
 #include <bsp/start.h>
+#include <rtems/score/assert.h>
 
 bool _CPU_SMP_Start_processor(uint32_t cpu_index)
 {
+  volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL;
+
+  _Assert(cpu_index == 1);
+
   /*
    * Enable the second CPU.
    */
-  if (cpu_index != 0) {
-    volatile uint32_t* const kick_address = (uint32_t*) 0xfffffff0UL;
-    _ARM_Data_synchronization_barrier();
-    _ARM_Instruction_synchronization_barrier();
-    *kick_address = (uint32_t) _start;
-    _ARM_Data_synchronization_barrier();
-    _ARM_Instruction_synchronization_barrier();
-    _ARM_Send_event();
-  }
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
+  *kick_address = (uint32_t) _start;
+  _ARM_Data_synchronization_barrier();
+  _ARM_Instruction_synchronization_barrier();
+  _ARM_Send_event();
 
-  /*
-   * Wait for secondary processor to complete its basic initialization so that
-   * we can enable the unified L2 cache.
-   */
-  return _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
+  return true;
 }