bsps/arm: Use fatal error for data cache disable

On the Cortex-A cores, at least the L1 data cache is required to provide
support for atomic operations.

Close #5050.

spec/build/testsuites/validation/objcachedisabledata.yml

@@ -5,7 +5,8 @@ copyrights:
 - Copyright (C) 2024 embedded brains GmbH & Co. KG
 cppflags: []
 cxxflags: []
-enabled-by: true
+enabled-by:
+  not: bsps/arm/xilinx-zynq
 includes: []
 install: []
 links: []

spec/build/testsuites/validation/objcachenodisabledata.yml

@@ -5,7 +5,7 @@ copyrights:
 - Copyright (C) 2024 embedded brains GmbH & Co. KG
 cppflags: []
 cxxflags: []
-enabled-by: false
+enabled-by: bsps/arm/xilinx-zynq
 includes: []
 install: []
 links: []