From b41f83249a5bd825d2a0b5b88a0eda700bc00a40 Mon Sep 17 00:00:00 2001 From: Shivam Deolankar Date: Tue, 21 Apr 2026 05:10:52 +0530 Subject: [PATCH] bsps/zynq-uart: fix parity configuration handling Fix parity handling in zynq_uart_set_attributes() by clearing existing parity bits before setting a new mode instead of always ORing PAR_NONE, which caused incorrect or ignored parity; also fix inverted PARODD logic and add ZYNQ_UART_MODE_PAR_MASK to manage the parity field correctly. Fixes #5554 --- bsps/include/dev/serial/zynq-uart-regs.h | 1 + bsps/shared/dev/serial/zynq-uart.c | 17 +++++++---------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/bsps/include/dev/serial/zynq-uart-regs.h b/bsps/include/dev/serial/zynq-uart-regs.h index 8de6d2ea58..946a72bc7b 100644 --- a/bsps/include/dev/serial/zynq-uart-regs.h +++ b/bsps/include/dev/serial/zynq-uart-regs.h @@ -84,6 +84,7 @@ typedef struct zynq_uart { #define ZYNQ_UART_MODE_PAR_ODD 0x01U #define ZYNQ_UART_MODE_PAR_SPACE 0x02U #define ZYNQ_UART_MODE_PAR_MARK 0x03U +#define ZYNQ_UART_MODE_PAR_MASK ZYNQ_UART_MODE_PAR(7) #define ZYNQ_UART_MODE_PAR_NONE 0x04U #define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2) #define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2) diff --git a/bsps/shared/dev/serial/zynq-uart.c b/bsps/shared/dev/serial/zynq-uart.c index ebeb8e1a52..881eca9902 100644 --- a/bsps/shared/dev/serial/zynq-uart.c +++ b/bsps/shared/dev/serial/zynq-uart.c @@ -193,16 +193,13 @@ static bool zynq_uart_set_attributes( */ mode |= ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL); - /* - * Parity - */ - mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE); - if (term->c_cflag & PARENB) { - if (!(term->c_cflag & PARODD)) { - mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD); - } else { - mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN); - } + /* Apply correct parity */ + if (!(term->c_cflag & PARENB)) { + mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE); + } else if (term->c_cflag & PARODD) { + mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_ODD); + } else { + mode |= ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_EVEN); } /*