diff --git a/bsps/m68k/include/mcf5225x/fec.h b/bsps/m68k/include/mcf5225x/fec.h deleted file mode 100644 index 8d8d6c3763..0000000000 --- a/bsps/m68k/include/mcf5225x/fec.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef FEC_H -#define FEC_H - -#include -#include -#include - -struct if_config { - u8_t flags; - u8_t hwaddr_len; - u16_t mtu; - u8_t hwaddr[NETIF_MAX_HWADDR_LEN]; - sys_thread_t net_task; - void(*phy_init)(void); - u8_t name[2]; -}; - -extern err_t mcf5225xif_init(struct netif *); -extern void handle_rx_frame(struct netif*); - -extern void smi_init(u32_t); -extern void smi_write(u8_t,u8_t,u16_t); -extern u16_t smi_read(u8_t,u8_t); - -#define MAX_FRAME_LEN 1518 -#define MTU_SIZE (MAX_FRAME_LEN-18) -#define MSCR_MII_SPEED(clk) ((clk/5000000+1)<<1) -#define PHY_ADDR 1 -#define PHY_REG_ID1 2 -#define PHY_REG_ID2 3 - -#endif /* FEC_H */ diff --git a/bsps/m68k/include/mcf5225x/mcf5225x.h b/bsps/m68k/include/mcf5225x/mcf5225x.h deleted file mode 100644 index ded447ffac..0000000000 --- a/bsps/m68k/include/mcf5225x/mcf5225x.h +++ /dev/null @@ -1,3552 +0,0 @@ -/* - * File: mcf5225x.h - * Purpose: Register and bit definitions - */ - -#ifndef __MCF5225x_H__ -#define __MCF5225x_H__ - -typedef volatile unsigned char vuint8; -typedef volatile unsigned short vuint16; -typedef volatile unsigned long vuint32; - -/********************************************************************* -* -* System Control Module (SCM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x000000])) -#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x000008])) -#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) -#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x000010])) -#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x000011])) -#define MCF_SCM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) -#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x000013])) -#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) -#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x00001C])) -#define MCF_SCM_MPR (*(vuint32*)(&__IPSBAR[0x000020])) -#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x000021])) -#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x000022])) -#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x000023])) -#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x000024])) -#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x000025])) -#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x000026])) -#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x000027])) -#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x000028])) -#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x000029])) -#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x00002A])) -#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x00002B])) -#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x00002C])) -#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x000030])) -#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x000031])) - -/* Bit definitions and macros for MCF_SCM_IPSBAR */ -#define MCF_SCM_IPSBAR_V (0x00000001) -#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000) - -/* Bit definitions and macros for MCF_SCM_RAMBAR */ -#define MCF_SCM_RAMBAR_BDE (0x00000200) -#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF_SCM_CRSR */ -#define MCF_SCM_CRSR_CWDR (0x20) -#define MCF_SCM_CRSR_EXT (0x80) - -/* Bit definitions and macros for MCF_SCM_CWCR */ -#define MCF_SCM_CWCR_CWTIC (0x01) -#define MCF_SCM_CWCR_CWTAVAL (0x02) -#define MCF_SCM_CWCR_CWTA (0x04) -#define MCF_SCM_CWCR_CWT(x) (((x)&0x07)<<3) -#define MCF_SCM_CWCR_CWRI (0x40) -#define MCF_SCM_CWCR_CWE (0x80) - -/* Bit definitions and macros for MCF_SCM_LPICR */ -#define MCF_SCM_LPICR_XIPL(x) (((x)&0x07)<<4) -#define MCF_SCM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_SCM_CWSR */ -#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_SCM_PPMRH */ -#define MCF_SCM_PPMRH_CDPORTS (0x00000001) -#define MCF_SCM_PPMRH_CDEPORT (0x00000002) -#define MCF_SCM_PPMRH_CDPIT0 (0x00000008) -#define MCF_SCM_PPMRH_CDPIT1 (0x00000010) -#define MCF_SCM_PPMRH_CDCAN (0x00000020) -#define MCF_SCM_PPMRH_CDADC (0x00000080) -#define MCF_SCM_PPMRH_CDGPT (0x00000100) -#define MCF_SCM_PPMRH_CDPWN (0x00000200) -#define MCF_SCM_PPMRH_CDFCAN (0x00000400) -#define MCF_SCM_PPMRH_CDCFM (0x00000800) - -/* Bit definitions and macros for MCF_SCM_PPMRL */ -#define MCF_SCM_PPMRL_CDG (0x00000002) -#define MCF_SCM_PPMRL_CDEIM (0x00000008) -#define MCF_SCM_PPMRL_CDDMA (0x00000010) -#define MCF_SCM_PPMRL_CDUART0 (0x00000020) -#define MCF_SCM_PPMRL_CDUART1 (0x00000040) -#define MCF_SCM_PPMRL_CDUART2 (0x00000080) -#define MCF_SCM_PPMRL_CDI2C0 (0x00000200) -#define MCF_SCM_PPMRL_CDI2C1 (0x00000800) -#define MCF_SCM_PPMRL_CDQSPI (0x00000400) -#define MCF_SCM_PPMRL_CDDTIM0 (0x00002000) -#define MCF_SCM_PPMRL_CDDTIM1 (0x00004000) -#define MCF_SCM_PPMRL_CDDTIM2 (0x00008000) -#define MCF_SCM_PPMRL_CDDTIM3 (0x00010000) -#define MCF_SCM_PPMRL_CDINTC0 (0x00020000) -#define MCF_SCM_PPMRL_CDINTC1 (0x00040000) -#define MCF_SCM_PPMRL_CDFEC (0x00200000) - -/* Bit definitions and macros for MCF_SCM_MPARK */ -#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0x0000000F)<<8) -#define MCF_SCM_MPARK_PRKLAST (0x00001000) -#define MCF_SCM_MPARK_TIMEOUT (0x00002000) -#define MCF_SCM_MPARK_FIXED (0x00004000) -#define MCF_SCM_MPARK_M0PRTY(x) (((x)&0x00000003)<<18) -#define MCF_SCM_MPARK_M2PRTY(x) (((x)&0x00000003)<<20) -#define MCF_SCM_MPARK_M3PRTY(x) (((x)&0x00000003)<<22) -#define MCF_SCM_MPARK_BCR24BIT (0x01000000) -#define MCF_SCM_MPARK_M2_P_EN (0x02000000) - -/* Bit definitions and macros for MCF_SCM_PPMRS */ -#define MCF_SCM_PPMRS_DISABLE_ALL (64) -#define MCF_SCM_PPMRS_DISABLE_CFM (43) -#define MCF_SCM_PPMRS_DISABLE_CAN (42) -#define MCF_SCM_PPMRS_DISABLE_PWM (41) -#define MCF_SCM_PPMRS_DISABLE_GPT (40) -#define MCF_SCM_PPMRS_DISABLE_ADC (39) -#define MCF_SCM_PPMRS_DISABLE_PIT1 (36) -#define MCF_SCM_PPMRS_DISABLE_PIT0 (35) -#define MCF_SCM_PPMRS_DISABLE_EPORT (33) -#define MCF_SCM_PPMRS_DISABLE_PORTS (32) -#define MCF_SCM_PPMRS_DISABLE_INTC (17) -#define MCF_SCM_PPMRS_DISABLE_DTIM3 (16) -#define MCF_SCM_PPMRS_DISABLE_DTIM2 (15) -#define MCF_SCM_PPMRS_DISABLE_DTIM1 (14) -#define MCF_SCM_PPMRS_DISABLE_DTIM0 (13) -#define MCF_SCM_PPMRS_DISABLE_QSPI (10) -#define MCF_SCM_PPMRS_DISABLE_I2C (9) -#define MCF_SCM_PPMRS_DISABLE_UART2 (7) -#define MCF_SCM_PPMRS_DISABLE_UART1 (6) -#define MCF_SCM_PPMRS_DISABLE_UART0 (5) -#define MCF_SCM_PPMRS_DISABLE_DMA (4) -#define MCF_SCM_PPMRS_SET_CDG (1) - -/* Bit definitions and macros for MCF_SCM_PPMRC */ -#define MCF_SCM_PPMRC_ENABLE_ALL (64) -#define MCF_SCM_PPMRC_ENABLE_CFM (43) -#define MCF_SCM_PPMRC_ENABLE_CAN (42) -#define MCF_SCM_PPMRC_ENABLE_PWM (41) -#define MCF_SCM_PPMRC_ENABLE_GPT (40) -#define MCF_SCM_PPMRC_ENABLE_ADC (39) -#define MCF_SCM_PPMRC_ENABLE_PIT1 (36) -#define MCF_SCM_PPMRC_ENABLE_PIT0 (35) -#define MCF_SCM_PPMRC_ENABLE_EPORT (33) -#define MCF_SCM_PPMRC_ENABLE_PORTS (32) -#define MCF_SCM_PPMRC_ENABLE_INTC (17) -#define MCF_SCM_PPMRC_ENABLE_DTIM3 (16) -#define MCF_SCM_PPMRC_ENABLE_DTIM2 (15) -#define MCF_SCM_PPMRC_ENABLE_DTIM1 (14) -#define MCF_SCM_PPMRC_ENABLE_DTIM0 (13) -#define MCF_SCM_PPMRC_ENABLE_QSPI (10) -#define MCF_SCM_PPMRC_ENABLE_I2C (9) -#define MCF_SCM_PPMRC_ENABLE_UART2 (7) -#define MCF_SCM_PPMRC_ENABLE_UART1 (6) -#define MCF_SCM_PPMRC_ENABLE_UART0 (5) -#define MCF_SCM_PPMRC_ENABLE_DMA (4) -#define MCF_SCM_PPMRC_CLEAR_CDG (1) - - -/********************************************************************* -* -* Power Management Module (PMM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PMM_PPMRH (*(vuint32*)(&__IPSBAR[0x00000C])) -#define MCF_PMM_PPMRL (*(vuint32*)(&__IPSBAR[0x000018])) -#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x000012])) -#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) - -/* Bit definitions and macros for MCF_PMM_PPMRH */ -#define MCF_PMM_PPMRH_CDPORTS (0x00000001) -#define MCF_PMM_PPMRH_CDEPORT (0x00000002) -#define MCF_PMM_PPMRH_CDPIT0 (0x00000008) -#define MCF_PMM_PPMRH_CDPIT1 (0x00000010) -#define MCF_PMM_PPMRH_CDADC (0x00000080) -#define MCF_PMM_PPMRH_CDGPT (0x00000100) -#define MCF_PMM_PPMRH_CDPWM (0x00000200) -#define MCF_PMM_PPMRH_CDFCAN (0x00000400) -#define MCF_PMM_PPMRH_CDCFM (0x00000800) - -/* Bit definitions and macros for MCF_PMM_PPMRL */ -#define MCF_PMM_PPMRL_CDG (0x00000002) -#define MCF_PMM_PPMRL_CDEIM (0x00000008) -#define MCF_PMM_PPMRL_CDDMA (0x00000010) -#define MCF_PMM_PPMRL_CDUART0 (0x00000020) -#define MCF_PMM_PPMRL_CDUART1 (0x00000040) -#define MCF_PMM_PPMRL_CDUART2 (0x00000080) -#define MCF_PMM_PPMRL_CDI2C (0x00000200) -#define MCF_PMM_PPMRL_CDQSPI (0x00000400) -#define MCF_PMM_PPMRL_CDDTIM0 (0x00002000) -#define MCF_PMM_PPMRL_CDDTIM1 (0x00004000) -#define MCF_PMM_PPMRL_CDDTIM2 (0x00008000) -#define MCF_PMM_PPMRL_CDDTIM3 (0x00010000) -#define MCF_PMM_PPMRL_CDINTC0 (0x00020000) - -/* Bit definitions and macros for MCF_PMM_LPICR */ -#define MCF_PMM_LPICR_XIPL(x) (((x)&0x07)<<4) -#define MCF_PMM_LPICR_ENBSTOP (0x80) - -/* Bit definitions and macros for MCF_PMM_LPCR */ -#define MCF_PMM_LPCR_LVDSE (0x02) -#define MCF_PMM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_PMM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_PMM_LPCR_LPMD_STOP (0xC0) -#define MCF_PMM_LPCR_LPMD_WAIT (0x80) -#define MCF_PMM_LPCR_LPMD_DOZE (0x40) -#define MCF_PMM_LPCR_LPMD_RUN (0x00) - - -/********************************************************************* -* -* DMA Controller Module (DMA) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_DMA_DMAREQC (*(vuint32*)(&__IPSBAR[0x000014])) -#define MCF_DMA_SAR0 (*(vuint32*)(&__IPSBAR[0x000100])) -#define MCF_DMA_SAR1 (*(vuint32*)(&__IPSBAR[0x000110])) -#define MCF_DMA_SAR2 (*(vuint32*)(&__IPSBAR[0x000120])) -#define MCF_DMA_SAR3 (*(vuint32*)(&__IPSBAR[0x000130])) -#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x000100+((x)*0x010)])) -#define MCF_DMA_DAR0 (*(vuint32*)(&__IPSBAR[0x000104])) -#define MCF_DMA_DAR1 (*(vuint32*)(&__IPSBAR[0x000114])) -#define MCF_DMA_DAR2 (*(vuint32*)(&__IPSBAR[0x000124])) -#define MCF_DMA_DAR3 (*(vuint32*)(&__IPSBAR[0x000134])) -#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x000104+((x)*0x010)])) -#define MCF_DMA_DSR0 (*(vuint8 *)(&__IPSBAR[0x000108])) -#define MCF_DMA_DSR1 (*(vuint8 *)(&__IPSBAR[0x000118])) -#define MCF_DMA_DSR2 (*(vuint8 *)(&__IPSBAR[0x000128])) -#define MCF_DMA_DSR3 (*(vuint8 *)(&__IPSBAR[0x000138])) -#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x000108+((x)*0x010)])) -#define MCF_DMA_BCR0 (*(vuint32*)(&__IPSBAR[0x000108])) -#define MCF_DMA_BCR1 (*(vuint32*)(&__IPSBAR[0x000118])) -#define MCF_DMA_BCR2 (*(vuint32*)(&__IPSBAR[0x000128])) -#define MCF_DMA_BCR3 (*(vuint32*)(&__IPSBAR[0x000138])) -#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x000108+((x)*0x010)])) -#define MCF_DMA_DCR0 (*(vuint32*)(&__IPSBAR[0x00010C])) -#define MCF_DMA_DCR1 (*(vuint32*)(&__IPSBAR[0x00011C])) -#define MCF_DMA_DCR2 (*(vuint32*)(&__IPSBAR[0x00012C])) -#define MCF_DMA_DCR3 (*(vuint32*)(&__IPSBAR[0x00013C])) -#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x00010C+((x)*0x010)])) - -/* Bit definitions and macros for MCF_DMA_DMAREQC */ -#define MCF_DMA_DMAREQC_DMAC0(x) (((x)&0x0000000F)<<0) -#define MCF_DMA_DMAREQC_DMAC1(x) (((x)&0x0000000F)<<4) -#define MCF_DMA_DMAREQC_DMAC2(x) (((x)&0x0000000F)<<8) -#define MCF_DMA_DMAREQC_DMAC3(x) (((x)&0x0000000F)<<12) -#define MCF_DMA_DMAREQC_DMAREQC_EXT(x) (((x)&0x0000000F)<<16) - -/* Bit definitions and macros for MCF_DMA_SAR */ -#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DMA_DAR */ -#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DMA_DSR */ -#define MCF_DMA_DSR_DONE (0x01) -#define MCF_DMA_DSR_BSY (0x02) -#define MCF_DMA_DSR_REQ (0x04) -#define MCF_DMA_DSR_BED (0x10) -#define MCF_DMA_DSR_BES (0x20) -#define MCF_DMA_DSR_CE (0x40) - -/* Bit definitions and macros for MCF_DMA_BCR */ -#define MCF_DMA_BCR_BCR(x) (((x)&0x00FFFFFF)<<0) -#define MCF_DMA_BCR_DSR(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_DMA_DCR */ -#define MCF_DMA_DCR_LCH2(x) (((x)&0x00000003)<<0) -#define MCF_DMA_DCR_LCH1(x) (((x)&0x00000003)<<2) -#define MCF_DMA_DCR_LINKCC(x) (((x)&0x00000003)<<4) -#define MCF_DMA_DCR_D_REQ (0x00000080) -#define MCF_DMA_DCR_DMOD(x) (((x)&0x0000000F)<<8) -#define MCF_DMA_DCR_SMOD(x) (((x)&0x0000000F)<<12) -#define MCF_DMA_DCR_START (0x00010000) -#define MCF_DMA_DCR_DSIZE(x) (((x)&0x00000003)<<17) -#define MCF_DMA_DCR_DINC (0x00080000) -#define MCF_DMA_DCR_SSIZE(x) (((x)&0x00000003)<<20) -#define MCF_DMA_DCR_SINC (0x00400000) -#define MCF_DMA_DCR_BWC(x) (((x)&0x00000007)<<25) -#define MCF_DMA_DCR_AA (0x10000000) -#define MCF_DMA_DCR_CS (0x20000000) -#define MCF_DMA_DCR_EEXT (0x40000000) -#define MCF_DMA_DCR_INT (0x80000000) -#define MCF_DMA_DCR_BWC_16K (0x1) -#define MCF_DMA_DCR_BWC_32K (0x2) -#define MCF_DMA_DCR_BWC_64K (0x3) -#define MCF_DMA_DCR_BWC_128K (0x4) -#define MCF_DMA_DCR_BWC_256K (0x5) -#define MCF_DMA_DCR_BWC_512K (0x6) -#define MCF_DMA_DCR_BWC_1024K (0x7) -#define MCF_DMA_DCR_DMOD_DIS (0x0) -#define MCF_DMA_DCR_DMOD_16 (0x1) -#define MCF_DMA_DCR_DMOD_32 (0x2) -#define MCF_DMA_DCR_DMOD_64 (0x3) -#define MCF_DMA_DCR_DMOD_128 (0x4) -#define MCF_DMA_DCR_DMOD_256 (0x5) -#define MCF_DMA_DCR_DMOD_512 (0x6) -#define MCF_DMA_DCR_DMOD_1K (0x7) -#define MCF_DMA_DCR_DMOD_2K (0x8) -#define MCF_DMA_DCR_DMOD_4K (0x9) -#define MCF_DMA_DCR_DMOD_8K (0xA) -#define MCF_DMA_DCR_DMOD_16K (0xB) -#define MCF_DMA_DCR_DMOD_32K (0xC) -#define MCF_DMA_DCR_DMOD_64K (0xD) -#define MCF_DMA_DCR_DMOD_128K (0xE) -#define MCF_DMA_DCR_DMOD_256K (0xF) -#define MCF_DMA_DCR_SMOD_DIS (0x0) -#define MCF_DMA_DCR_SMOD_16 (0x1) -#define MCF_DMA_DCR_SMOD_32 (0x2) -#define MCF_DMA_DCR_SMOD_64 (0x3) -#define MCF_DMA_DCR_SMOD_128 (0x4) -#define MCF_DMA_DCR_SMOD_256 (0x5) -#define MCF_DMA_DCR_SMOD_512 (0x6) -#define MCF_DMA_DCR_SMOD_1K (0x7) -#define MCF_DMA_DCR_SMOD_2K (0x8) -#define MCF_DMA_DCR_SMOD_4K (0x9) -#define MCF_DMA_DCR_SMOD_8K (0xA) -#define MCF_DMA_DCR_SMOD_16K (0xB) -#define MCF_DMA_DCR_SMOD_32K (0xC) -#define MCF_DMA_DCR_SMOD_64K (0xD) -#define MCF_DMA_DCR_SMOD_128K (0xE) -#define MCF_DMA_DCR_SMOD_256K (0xF) -#define MCF_DMA_DCR_SSIZE_LONG (0x0) -#define MCF_DMA_DCR_SSIZE_BYTE (0x1) -#define MCF_DMA_DCR_SSIZE_WORD (0x2) -#define MCF_DMA_DCR_SSIZE_LINE (0x3) -#define MCF_DMA_DCR_DSIZE_LONG (0x0) -#define MCF_DMA_DCR_DSIZE_BYTE (0x1) -#define MCF_DMA_DCR_DSIZE_WORD (0x2) -#define MCF_DMA_DCR_DSIZE_LINE (0x3) -#define MCF_DMA_DCR_LCH1_CH0 (0x0) -#define MCF_DMA_DCR_LCH1_CH1 (0x1) -#define MCF_DMA_DCR_LCH1_CH2 (0x2) -#define MCF_DMA_DCR_LCH1_CH3 (0x3) -#define MCF_DMA_DCR_LCH2_CH0 (0x0) -#define MCF_DMA_DCR_LCH2_CH1 (0x1) -#define MCF_DMA_DCR_LCH2_CH2 (0x2) -#define MCF_DMA_DCR_LCH2_CH3 (0x3) - - -/********************************************************************* -* -* Universal Asynchronous Receiver Transmitter (UART) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_UART0_UMR (*(vuint8 *)(&__IPSBAR[0x000200])) -#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x000204])) -#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x000204])) -#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x000208])) -#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x00020C])) -#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x00020C])) -#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x000210])) -#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x000210])) -#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x000214])) -#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x000214])) -#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x000218])) -#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x00021C])) -#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x000234])) -#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x000238])) -#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x00023C])) -#define MCF_UART1_UMR (*(vuint8 *)(&__IPSBAR[0x000240])) -#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x000244])) -#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x000244])) -#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x000248])) -#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x00024C])) -#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x00024C])) -#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x000250])) -#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x000250])) -#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x000254])) -#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x000254])) -#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x000258])) -#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x00025C])) -#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x000274])) -#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x000278])) -#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x00027C])) -#define MCF_UART2_UMR (*(vuint8 *)(&__IPSBAR[0x000280])) -#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x000284])) -#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x000284])) -#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x000288])) -#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x00028C])) -#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x00028C])) -#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x000290])) -#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x000290])) -#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x000294])) -#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x000294])) -#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x000298])) -#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x00029C])) -#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x0002B4])) -#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x0002B8])) -#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x0002BC])) -#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x000200+((x)*0x040)])) -#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x000204+((x)*0x040)])) -#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x000208+((x)*0x040)])) -#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x00020C+((x)*0x040)])) -#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x000210+((x)*0x040)])) -#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x000214+((x)*0x040)])) -#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x000218+((x)*0x040)])) -#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x00021C+((x)*0x040)])) -#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x000234+((x)*0x040)])) -#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x000238+((x)*0x040)])) -#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x00023C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_UART_UMR */ -#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) -#define MCF_UART_UMR_PT (0x04) -#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) -#define MCF_UART_UMR_ERR (0x20) -#define MCF_UART_UMR_RXIRQ (0x40) -#define MCF_UART_UMR_RXRTS (0x80) -#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) -#define MCF_UART_UMR_TXCTS (0x10) -#define MCF_UART_UMR_TXRTS (0x20) -#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) -#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) -#define MCF_UART_UMR_PM_MULTI_DATA (0x18) -#define MCF_UART_UMR_PM_NONE (0x10) -#define MCF_UART_UMR_PM_FORCE_HI (0x0C) -#define MCF_UART_UMR_PM_FORCE_LO (0x08) -#define MCF_UART_UMR_PM_ODD (0x04) -#define MCF_UART_UMR_PM_EVEN (0x00) -#define MCF_UART_UMR_BC_5 (0x00) -#define MCF_UART_UMR_BC_6 (0x01) -#define MCF_UART_UMR_BC_7 (0x02) -#define MCF_UART_UMR_BC_8 (0x03) -#define MCF_UART_UMR_CM_NORMAL (0x00) -#define MCF_UART_UMR_CM_ECHO (0x40) -#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) -#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) -#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) -#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) -#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) - -/* Bit definitions and macros for MCF_UART_USR */ -#define MCF_UART_USR_RXRDY (0x01) -#define MCF_UART_USR_FFULL (0x02) -#define MCF_UART_USR_TXRDY (0x04) -#define MCF_UART_USR_TXEMP (0x08) -#define MCF_UART_USR_OE (0x10) -#define MCF_UART_USR_PE (0x20) -#define MCF_UART_USR_FE (0x40) -#define MCF_UART_USR_RB (0x80) - -/* Bit definitions and macros for MCF_UART_UCSR */ -#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) -#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) -#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) -#define MCF_UART_UCSR_RCS_CTM16 (0xE0) -#define MCF_UART_UCSR_RCS_CTM (0xF0) -#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) -#define MCF_UART_UCSR_TCS_CTM16 (0x0E) -#define MCF_UART_UCSR_TCS_CTM (0x0F) - -/* Bit definitions and macros for MCF_UART_UCR */ -#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) -#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) -#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) -#define MCF_UART_UCR_NONE (0x00) -#define MCF_UART_UCR_STOP_BREAK (0x70) -#define MCF_UART_UCR_START_BREAK (0x60) -#define MCF_UART_UCR_BKCHGINT (0x50) -#define MCF_UART_UCR_RESET_ERROR (0x40) -#define MCF_UART_UCR_RESET_TX (0x30) -#define MCF_UART_UCR_RESET_RX (0x20) -#define MCF_UART_UCR_RESET_MR (0x10) -#define MCF_UART_UCR_TX_DISABLED (0x08) -#define MCF_UART_UCR_TX_ENABLED (0x04) -#define MCF_UART_UCR_RX_DISABLED (0x02) -#define MCF_UART_UCR_RX_ENABLED (0x01) - -/* Bit definitions and macros for MCF_UART_UIPCR */ -#define MCF_UART_UIPCR_CTS (0x01) -#define MCF_UART_UIPCR_COS (0x10) - -/* Bit definitions and macros for MCF_UART_UACR */ -#define MCF_UART_UACR_IEC (0x01) - -/* Bit definitions and macros for MCF_UART_UISR */ -#define MCF_UART_UISR_TXRDY (0x01) -#define MCF_UART_UISR_RXRDY_FU (0x02) -#define MCF_UART_UISR_DB (0x04) -#define MCF_UART_UISR_RXFTO (0x08) -#define MCF_UART_UISR_TXFIFO (0x10) -#define MCF_UART_UISR_RXFIFO (0x20) -#define MCF_UART_UISR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIMR */ -#define MCF_UART_UIMR_TXRDY (0x01) -#define MCF_UART_UIMR_RXRDY_FU (0x02) -#define MCF_UART_UIMR_DB (0x04) -#define MCF_UART_UIMR_COS (0x80) - -/* Bit definitions and macros for MCF_UART_UIP */ -#define MCF_UART_UIP_CTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP1 */ -#define MCF_UART_UOP1_RTS (0x01) - -/* Bit definitions and macros for MCF_UART_UOP0 */ -#define MCF_UART_UOP0_RTS (0x01) - -/********************************************************************* -* -* I2C Module (I2C) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_I2C_I2AR (*(vuint8 *)(&__IPSBAR[0x000300])) -#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x000304])) -#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x000308])) -#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x00030C])) -#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x000310])) - -/* Bit definitions and macros for MCF_I2C_I2AR */ -#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_I2C_I2FDR */ -#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) - -/* Bit definitions and macros for MCF_I2C_I2CR */ -#define MCF_I2C_I2CR_RSTA (0x04) -#define MCF_I2C_I2CR_TXAK (0x08) -#define MCF_I2C_I2CR_MTX (0x10) -#define MCF_I2C_I2CR_MSTA (0x20) -#define MCF_I2C_I2CR_IIEN (0x40) -#define MCF_I2C_I2CR_IEN (0x80) - -/* Bit definitions and macros for MCF_I2C_I2SR */ -#define MCF_I2C_I2SR_RXAK (0x01) -#define MCF_I2C_I2SR_IIF (0x02) -#define MCF_I2C_I2SR_SRW (0x04) -#define MCF_I2C_I2SR_IAL (0x10) -#define MCF_I2C_I2SR_IBB (0x20) -#define MCF_I2C_I2SR_IAAS (0x40) -#define MCF_I2C_I2SR_ICF (0x80) - -/* Bit definitions and macros for MCF_I2C_I2DR */ -#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_I2C_I2ICR */ -#define MCF_I2C_I2ICR_IE (0x01) -#define MCF_I2C_I2ICR_RE (0x02) -#define MCF_I2C_I2ICR_TE (0x04) -#define MCF_I2C_I2ICR_BNBE (0x08) - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x000340])) -#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x000344])) -#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x000348])) -#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x00034C])) -#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x000350])) -#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x000354])) - -/* Bit definitions and macros for MCF_QSPI_QMR */ -#define MCF_QSPI_QMR_BAUD(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QMR_CPHA (0x0100) -#define MCF_QSPI_QMR_CPOL (0x0200) -#define MCF_QSPI_QMR_BITS(x) (((x)&0x000F)<<10) -#define MCF_QSPI_QMR_DOHIE (0x4000) -#define MCF_QSPI_QMR_MSTR (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QDLYR */ -#define MCF_QSPI_QDLYR_DTL(x) (((x)&0x00FF)<<0) -#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF_QSPI_QDLYR_SPE (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QWR */ -#define MCF_QSPI_QWR_NEWQP(x) (((x)&0x000F)<<0) -#define MCF_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF_QSPI_QWR_CSIV (0x1000) -#define MCF_QSPI_QWR_WRTO (0x2000) -#define MCF_QSPI_QWR_WREN (0x4000) -#define MCF_QSPI_QWR_HALT (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QIR */ -#define MCF_QSPI_QIR_SPIF (0x0001) -#define MCF_QSPI_QIR_ABRT (0x0004) -#define MCF_QSPI_QIR_WCEF (0x0008) -#define MCF_QSPI_QIR_SPIFE (0x0100) -#define MCF_QSPI_QIR_ABRTE (0x0400) -#define MCF_QSPI_QIR_WCEFE (0x0800) -#define MCF_QSPI_QIR_ABRTL (0x1000) -#define MCF_QSPI_QIR_ABRTB (0x4000) -#define MCF_QSPI_QIR_WCEFB (0x8000) - -/* Bit definitions and macros for MCF_QSPI_QAR */ -#define MCF_QSPI_QAR_ADDR(x) (((x)&0x003F)<<0) - -/* Bit definitions and macros for MCF_QSPI_QDR */ -#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0) - -/********************************************************************* -* -* DMA Timers (DTIM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x000400])) -#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x000402])) -#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x000403])) -#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x000404])) -#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x000408])) -#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x00040C])) -#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x000440])) -#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x000442])) -#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x000443])) -#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x000444])) -#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x000448])) -#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x00044C])) -#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x000480])) -#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x000482])) -#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x000483])) -#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x000484])) -#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x000488])) -#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x00048C])) -#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x0004C0])) -#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x0004C2])) -#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x0004C3])) -#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x0004C4])) -#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x0004C8])) -#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x0004CC])) -#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x000400+((x)*0x040)])) -#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x000402+((x)*0x040)])) -#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x000403+((x)*0x040)])) -#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x000404+((x)*0x040)])) -#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x000408+((x)*0x040)])) -#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x00040C+((x)*0x040)])) - -/* Bit definitions and macros for MCF_DTIM_DTMR */ -#define MCF_DTIM_DTMR_RST (0x0001) -#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_DTIM_DTMR_FRR (0x0008) -#define MCF_DTIM_DTMR_ORRI (0x0010) -#define MCF_DTIM_DTMR_OM (0x0020) -#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_DTIM_DTMR_CE_ANY (0x00C0) -#define MCF_DTIM_DTMR_CE_FALL (0x0080) -#define MCF_DTIM_DTMR_CE_RISE (0x0040) -#define MCF_DTIM_DTMR_CE_NONE (0x0000) -#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) -#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) -#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) -#define MCF_DTIM_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_DTIM_DTXMR */ -#define MCF_DTIM_DTXMR_MODE16 (0x01) -#define MCF_DTIM_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_DTIM_DTER */ -#define MCF_DTIM_DTER_CAP (0x01) -#define MCF_DTIM_DTER_REF (0x02) - -/* Bit definitions and macros for MCF_DTIM_DTRR */ -#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCR */ -#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCN */ -#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* -* -* Interrupt Controller (INTC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0x000C00])) -#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0x000C04])) -#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0x000C08])) -#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0x000C0C])) -#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0x000C10])) -#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0x000C14])) -#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0x000C18])) -#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000C19])) -#define MCF_INTC0_ICR1 (*(vuint8 *)(&__IPSBAR[0x000C41])) -#define MCF_INTC0_ICR2 (*(vuint8 *)(&__IPSBAR[0x000C42])) -#define MCF_INTC0_ICR3 (*(vuint8 *)(&__IPSBAR[0x000C43])) -#define MCF_INTC0_ICR4 (*(vuint8 *)(&__IPSBAR[0x000C44])) -#define MCF_INTC0_ICR5 (*(vuint8 *)(&__IPSBAR[0x000C45])) -#define MCF_INTC0_ICR6 (*(vuint8 *)(&__IPSBAR[0x000C46])) -#define MCF_INTC0_ICR7 (*(vuint8 *)(&__IPSBAR[0x000C47])) -#define MCF_INTC0_ICR8 (*(vuint8 *)(&__IPSBAR[0x000C48])) -#define MCF_INTC0_ICR9 (*(vuint8 *)(&__IPSBAR[0x000C49])) -#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0x000C4A])) -#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0x000C4B])) -#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0x000C4C])) -#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0x000C4D])) -#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0x000C4E])) -#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0x000C4F])) -#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0x000C50])) -#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0x000C51])) -#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0x000C52])) -#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0x000C53])) -#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0x000C54])) -#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0x000C55])) -#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0x000C56])) -#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0x000C57])) -#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0x000C58])) -#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0x000C59])) -#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0x000C5A])) -#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0x000C5B])) -#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0x000C5C])) -#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0x000C5D])) -#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0x000C5E])) -#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0x000C5F])) -#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0x000C60])) -#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0x000C61])) -#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0x000C62])) -#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0x000C63])) -#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0x000C64])) -#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0x000C65])) -#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0x000C66])) -#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0x000C67])) -#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0x000C68])) -#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0x000C69])) -#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0x000C6A])) -#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0x000C6B])) -#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0x000C6C])) -#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0x000C6D])) -#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0x000C6E])) -#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0x000C6F])) -#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0x000C70])) -#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0x000C71])) -#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0x000C72])) -#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0x000C73])) -#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0x000C74])) -#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0x000C75])) -#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0x000C76])) -#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0x000C77])) -#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0x000C78])) -#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0x000C79])) -#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0x000C7A])) -#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0x000C7B])) -#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0x000C7C])) -#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0x000C7D])) -#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0x000C7E])) -#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0x000C7F])) -#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x-1)*0x001)])) -#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0x000CE0])) -#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0x000CE4])) -#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0x000CE8])) -#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0x000CEC])) -#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0x000CF0])) -#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0x000CF4])) -#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0x000CF8])) -#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0x000CFC])) -#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x-1)*0x004)])) -#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0x000D00])) -#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0x000D04])) -#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0x000D08])) -#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0x000D0C])) -#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0x000D10])) -#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0x000D14])) -#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0x000D18])) -#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0x000D19])) -#define MCF_INTC1_ICR1 (*(vuint8 *)(&__IPSBAR[0x000D41])) -#define MCF_INTC1_ICR2 (*(vuint8 *)(&__IPSBAR[0x000D42])) -#define MCF_INTC1_ICR3 (*(vuint8 *)(&__IPSBAR[0x000D43])) -#define MCF_INTC1_ICR4 (*(vuint8 *)(&__IPSBAR[0x000D44])) -#define MCF_INTC1_ICR5 (*(vuint8 *)(&__IPSBAR[0x000D45])) -#define MCF_INTC1_ICR6 (*(vuint8 *)(&__IPSBAR[0x000D46])) -#define MCF_INTC1_ICR7 (*(vuint8 *)(&__IPSBAR[0x000D47])) -#define MCF_INTC1_ICR8 (*(vuint8 *)(&__IPSBAR[0x000D48])) -#define MCF_INTC1_ICR9 (*(vuint8 *)(&__IPSBAR[0x000D49])) -#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0x000D4A])) -#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0x000D4B])) -#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0x000D4C])) -#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0x000D4D])) -#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0x000D4E])) -#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0x000D4F])) -#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0x000D50])) -#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0x000D51])) -#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0x000D52])) -#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0x000D53])) -#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0x000D54])) -#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0x000D55])) -#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0x000D56])) -#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0x000D57])) -#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0x000D58])) -#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0x000D59])) -#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0x000D5A])) -#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0x000D5B])) -#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0x000D5C])) -#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0x000D5D])) -#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0x000D5E])) -#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0x000D5F])) -#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0x000D60])) -#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0x000D61])) -#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0x000D62])) -#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0x000D63])) -#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0x000D64])) -#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0x000D65])) -#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0x000D66])) -#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0x000D67])) -#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0x000D68])) -#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0x000D69])) -#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0x000D6A])) -#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0x000D6B])) -#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0x000D6C])) -#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0x000D6D])) -#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0x000D6E])) -#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0x000D6F])) -#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0x000D70])) -#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0x000D71])) -#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0x000D72])) -#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0x000D73])) -#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0x000D74])) -#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0x000D75])) -#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0x000D76])) -#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0x000D77])) -#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0x000D78])) -#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0x000D79])) -#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0x000D7A])) -#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0x000D7B])) -#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0x000D7C])) -#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0x000D7D])) -#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0x000D7E])) -#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0x000D7F])) -#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0x000D41+((x-1)*0x001)])) -#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0x000DE0])) -#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0x000DE4])) -#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0x000DE8])) -#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0x000DEC])) -#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0x000DF0])) -#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0x000DF4])) -#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0x000DF8])) -#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0x000DFC])) -#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0x000DE4+((x-1)*0x004)])) -#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0x000C00+((x)*0x100)])) -#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0x000C04+((x)*0x100)])) -#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0x000C08+((x)*0x100)])) -#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0x000C0C+((x)*0x100)])) -#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0x000C10+((x)*0x100)])) -#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0x000C14+((x)*0x100)])) -#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0x000C18+((x)*0x100)])) -#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0x000C19+((x)*0x100)])) -#define MCF_INTC_ICR1(x) (*(vuint8 *)(&__IPSBAR[0x000C41+((x)*0x100)])) -#define MCF_INTC_ICR2(x) (*(vuint8 *)(&__IPSBAR[0x000C42+((x)*0x100)])) -#define MCF_INTC_ICR3(x) (*(vuint8 *)(&__IPSBAR[0x000C43+((x)*0x100)])) -#define MCF_INTC_ICR4(x) (*(vuint8 *)(&__IPSBAR[0x000C44+((x)*0x100)])) -#define MCF_INTC_ICR5(x) (*(vuint8 *)(&__IPSBAR[0x000C45+((x)*0x100)])) -#define MCF_INTC_ICR6(x) (*(vuint8 *)(&__IPSBAR[0x000C46+((x)*0x100)])) -#define MCF_INTC_ICR7(x) (*(vuint8 *)(&__IPSBAR[0x000C47+((x)*0x100)])) -#define MCF_INTC_ICR8(x) (*(vuint8 *)(&__IPSBAR[0x000C48+((x)*0x100)])) -#define MCF_INTC_ICR9(x) (*(vuint8 *)(&__IPSBAR[0x000C49+((x)*0x100)])) -#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0x000C4A+((x)*0x100)])) -#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0x000C4B+((x)*0x100)])) -#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0x000C4C+((x)*0x100)])) -#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0x000C4D+((x)*0x100)])) -#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0x000C4E+((x)*0x100)])) -#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0x000C4F+((x)*0x100)])) -#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0x000C50+((x)*0x100)])) -#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0x000C51+((x)*0x100)])) -#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0x000C52+((x)*0x100)])) -#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0x000C53+((x)*0x100)])) -#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0x000C54+((x)*0x100)])) -#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0x000C55+((x)*0x100)])) -#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0x000C56+((x)*0x100)])) -#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0x000C57+((x)*0x100)])) -#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0x000C58+((x)*0x100)])) -#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0x000C59+((x)*0x100)])) -#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0x000C5A+((x)*0x100)])) -#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0x000C5B+((x)*0x100)])) -#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0x000C5C+((x)*0x100)])) -#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0x000C5D+((x)*0x100)])) -#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0x000C5E+((x)*0x100)])) -#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0x000C5F+((x)*0x100)])) -#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0x000C60+((x)*0x100)])) -#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0x000C61+((x)*0x100)])) -#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0x000C62+((x)*0x100)])) -#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0x000C63+((x)*0x100)])) -#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0x000C64+((x)*0x100)])) -#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0x000C65+((x)*0x100)])) -#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0x000C66+((x)*0x100)])) -#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0x000C67+((x)*0x100)])) -#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0x000C68+((x)*0x100)])) -#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0x000C69+((x)*0x100)])) -#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0x000C6A+((x)*0x100)])) -#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0x000C6B+((x)*0x100)])) -#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0x000C6C+((x)*0x100)])) -#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0x000C6D+((x)*0x100)])) -#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0x000C6E+((x)*0x100)])) -#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0x000C6F+((x)*0x100)])) -#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0x000C70+((x)*0x100)])) -#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0x000C71+((x)*0x100)])) -#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0x000C72+((x)*0x100)])) -#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0x000C73+((x)*0x100)])) -#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0x000C74+((x)*0x100)])) -#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0x000C75+((x)*0x100)])) -#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0x000C76+((x)*0x100)])) -#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0x000C77+((x)*0x100)])) -#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0x000C78+((x)*0x100)])) -#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0x000C79+((x)*0x100)])) -#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0x000C7A+((x)*0x100)])) -#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0x000C7B+((x)*0x100)])) -#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0x000C7C+((x)*0x100)])) -#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0x000C7D+((x)*0x100)])) -#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0x000C7E+((x)*0x100)])) -#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0x000C7F+((x)*0x100)])) -#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE0+((x)*0x100)])) -#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE4+((x)*0x100)])) -#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CE8+((x)*0x100)])) -#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CEC+((x)*0x100)])) -#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF0+((x)*0x100)])) -#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF4+((x)*0x100)])) -#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CF8+((x)*0x100)])) -#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0x000CFC+((x)*0x100)])) - -/* Bit definitions and macros for MCF_INTC_IPRH */ -#define MCF_INTC_IPRH_INT32 (0x00000001) -#define MCF_INTC_IPRH_INT33 (0x00000002) -#define MCF_INTC_IPRH_INT34 (0x00000004) -#define MCF_INTC_IPRH_INT35 (0x00000008) -#define MCF_INTC_IPRH_INT36 (0x00000010) -#define MCF_INTC_IPRH_INT37 (0x00000020) -#define MCF_INTC_IPRH_INT38 (0x00000040) -#define MCF_INTC_IPRH_INT39 (0x00000080) -#define MCF_INTC_IPRH_INT40 (0x00000100) -#define MCF_INTC_IPRH_INT41 (0x00000200) -#define MCF_INTC_IPRH_INT42 (0x00000400) -#define MCF_INTC_IPRH_INT43 (0x00000800) -#define MCF_INTC_IPRH_INT44 (0x00001000) -#define MCF_INTC_IPRH_INT45 (0x00002000) -#define MCF_INTC_IPRH_INT46 (0x00004000) -#define MCF_INTC_IPRH_INT47 (0x00008000) -#define MCF_INTC_IPRH_INT48 (0x00010000) -#define MCF_INTC_IPRH_INT49 (0x00020000) -#define MCF_INTC_IPRH_INT50 (0x00040000) -#define MCF_INTC_IPRH_INT51 (0x00080000) -#define MCF_INTC_IPRH_INT52 (0x00100000) -#define MCF_INTC_IPRH_INT53 (0x00200000) -#define MCF_INTC_IPRH_INT54 (0x00400000) -#define MCF_INTC_IPRH_INT55 (0x00800000) -#define MCF_INTC_IPRH_INT56 (0x01000000) -#define MCF_INTC_IPRH_INT57 (0x02000000) -#define MCF_INTC_IPRH_INT58 (0x04000000) -#define MCF_INTC_IPRH_INT59 (0x08000000) -#define MCF_INTC_IPRH_INT60 (0x10000000) -#define MCF_INTC_IPRH_INT61 (0x20000000) -#define MCF_INTC_IPRH_INT62 (0x40000000) -#define MCF_INTC_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IPRL */ -#define MCF_INTC_IPRL_INT1 (0x00000002) -#define MCF_INTC_IPRL_INT2 (0x00000004) -#define MCF_INTC_IPRL_INT3 (0x00000008) -#define MCF_INTC_IPRL_INT4 (0x00000010) -#define MCF_INTC_IPRL_INT5 (0x00000020) -#define MCF_INTC_IPRL_INT6 (0x00000040) -#define MCF_INTC_IPRL_INT7 (0x00000080) -#define MCF_INTC_IPRL_INT8 (0x00000100) -#define MCF_INTC_IPRL_INT9 (0x00000200) -#define MCF_INTC_IPRL_INT10 (0x00000400) -#define MCF_INTC_IPRL_INT11 (0x00000800) -#define MCF_INTC_IPRL_INT12 (0x00001000) -#define MCF_INTC_IPRL_INT13 (0x00002000) -#define MCF_INTC_IPRL_INT14 (0x00004000) -#define MCF_INTC_IPRL_INT15 (0x00008000) -#define MCF_INTC_IPRL_INT16 (0x00010000) -#define MCF_INTC_IPRL_INT17 (0x00020000) -#define MCF_INTC_IPRL_INT18 (0x00040000) -#define MCF_INTC_IPRL_INT19 (0x00080000) -#define MCF_INTC_IPRL_INT20 (0x00100000) -#define MCF_INTC_IPRL_INT21 (0x00200000) -#define MCF_INTC_IPRL_INT22 (0x00400000) -#define MCF_INTC_IPRL_INT23 (0x00800000) -#define MCF_INTC_IPRL_INT24 (0x01000000) -#define MCF_INTC_IPRL_INT25 (0x02000000) -#define MCF_INTC_IPRL_INT26 (0x04000000) -#define MCF_INTC_IPRL_INT27 (0x08000000) -#define MCF_INTC_IPRL_INT28 (0x10000000) -#define MCF_INTC_IPRL_INT29 (0x20000000) -#define MCF_INTC_IPRL_INT30 (0x40000000) -#define MCF_INTC_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRH */ -#define MCF_INTC_IMRH_MASK32 (0x00000001) -#define MCF_INTC_IMRH_MASK33 (0x00000002) -#define MCF_INTC_IMRH_MASK34 (0x00000004) -#define MCF_INTC_IMRH_MASK35 (0x00000008) -#define MCF_INTC_IMRH_MASK36 (0x00000010) -#define MCF_INTC_IMRH_MASK37 (0x00000020) -#define MCF_INTC_IMRH_MASK38 (0x00000040) -#define MCF_INTC_IMRH_MASK39 (0x00000080) -#define MCF_INTC_IMRH_MASK40 (0x00000100) -#define MCF_INTC_IMRH_MASK41 (0x00000200) -#define MCF_INTC_IMRH_MASK42 (0x00000400) -#define MCF_INTC_IMRH_MASK43 (0x00000800) -#define MCF_INTC_IMRH_MASK44 (0x00001000) -#define MCF_INTC_IMRH_MASK45 (0x00002000) -#define MCF_INTC_IMRH_MASK46 (0x00004000) -#define MCF_INTC_IMRH_MASK47 (0x00008000) -#define MCF_INTC_IMRH_MASK48 (0x00010000) -#define MCF_INTC_IMRH_MASK49 (0x00020000) -#define MCF_INTC_IMRH_MASK50 (0x00040000) -#define MCF_INTC_IMRH_MASK51 (0x00080000) -#define MCF_INTC_IMRH_MASK52 (0x00100000) -#define MCF_INTC_IMRH_MASK53 (0x00200000) -#define MCF_INTC_IMRH_MASK54 (0x00400000) -#define MCF_INTC_IMRH_MASK55 (0x00800000) -#define MCF_INTC_IMRH_MASK56 (0x01000000) -#define MCF_INTC_IMRH_MASK57 (0x02000000) -#define MCF_INTC_IMRH_MASK58 (0x04000000) -#define MCF_INTC_IMRH_MASK59 (0x08000000) -#define MCF_INTC_IMRH_MASK60 (0x10000000) -#define MCF_INTC_IMRH_MASK61 (0x20000000) -#define MCF_INTC_IMRH_MASK62 (0x40000000) -#define MCF_INTC_IMRH_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRL */ -#define MCF_INTC_IMRL_MASKALL (0x00000001) -#define MCF_INTC_IMRL_MASK1 (0x00000002) -#define MCF_INTC_IMRL_MASK2 (0x00000004) -#define MCF_INTC_IMRL_MASK3 (0x00000008) -#define MCF_INTC_IMRL_MASK4 (0x00000010) -#define MCF_INTC_IMRL_MASK5 (0x00000020) -#define MCF_INTC_IMRL_MASK6 (0x00000040) -#define MCF_INTC_IMRL_MASK7 (0x00000080) -#define MCF_INTC_IMRL_MASK8 (0x00000100) -#define MCF_INTC_IMRL_MASK9 (0x00000200) -#define MCF_INTC_IMRL_MASK10 (0x00000400) -#define MCF_INTC_IMRL_MASK11 (0x00000800) -#define MCF_INTC_IMRL_MASK12 (0x00001000) -#define MCF_INTC_IMRL_MASK13 (0x00002000) -#define MCF_INTC_IMRL_MASK14 (0x00004000) -#define MCF_INTC_IMRL_MASK15 (0x00008000) -#define MCF_INTC_IMRL_MASK16 (0x00010000) -#define MCF_INTC_IMRL_MASK17 (0x00020000) -#define MCF_INTC_IMRL_MASK18 (0x00040000) -#define MCF_INTC_IMRL_MASK19 (0x00080000) -#define MCF_INTC_IMRL_MASK20 (0x00100000) -#define MCF_INTC_IMRL_MASK21 (0x00200000) -#define MCF_INTC_IMRL_MASK22 (0x00400000) -#define MCF_INTC_IMRL_MASK23 (0x00800000) -#define MCF_INTC_IMRL_MASK24 (0x01000000) -#define MCF_INTC_IMRL_MASK25 (0x02000000) -#define MCF_INTC_IMRL_MASK26 (0x04000000) -#define MCF_INTC_IMRL_MASK27 (0x08000000) -#define MCF_INTC_IMRL_MASK28 (0x10000000) -#define MCF_INTC_IMRL_MASK29 (0x20000000) -#define MCF_INTC_IMRL_MASK30 (0x40000000) -#define MCF_INTC_IMRL_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCH */ -#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCL */ -#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) -#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) -#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) -#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) -#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) -#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) -#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IRLR */ -#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) - -/* Bit definitions and macros for MCF_INTC_IACKLPR */ -#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) -#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_INTC_ICR */ -#define MCF_INTC_ICR_IP(x) (((x)&0x07)<<0) -#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<3) - -/* Bit definitions and macros for MCF_INTC_SWIACK */ -#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_INTC_LIACK */ -#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) - -/********************************************************************* -* -* General Purpose I/O (GPIO) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008])) -#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A])) -#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B])) -#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C])) -#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E])) -#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F])) -#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010])) -#define MCF_GPIO_PORTTE (*(vuint8 *)(&__IPSBAR[0x100000])) -#define MCF_GPIO_PORTTF (*(vuint8 *)(&__IPSBAR[0x100001])) -#define MCF_GPIO_PORTTG (*(vuint8 *)(&__IPSBAR[0x100002])) -#define MCF_GPIO_PORTTH (*(vuint8 *)(&__IPSBAR[0x100003])) -#define MCF_GPIO_PORTTI (*(vuint8 *)(&__IPSBAR[0x100004])) -#define MCF_GPIO_PORTTJ (*(vuint8 *)(&__IPSBAR[0x100006])) -#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011])) -#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012])) -#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013])) -#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014])) -#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015])) -#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016])) -#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020])) -#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022])) -#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023])) -#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024])) -#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026])) -#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027])) -#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028])) -#define MCF_GPIO_DDRTE (*(vuint8 *)(&__IPSBAR[0x100018])) -#define MCF_GPIO_DDRTF (*(vuint8 *)(&__IPSBAR[0x100019])) -#define MCF_GPIO_DDRTG (*(vuint8 *)(&__IPSBAR[0x10001A])) -#define MCF_GPIO_DDRTH (*(vuint8 *)(&__IPSBAR[0x10001B])) -#define MCF_GPIO_DDRTI (*(vuint8 *)(&__IPSBAR[0x10001C])) -#define MCF_GPIO_DDRTJ (*(vuint8 *)(&__IPSBAR[0x10001E])) -#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029])) -#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A])) -#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B])) -#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C])) -#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D])) -#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E])) -#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038])) -#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A])) -#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B])) -#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C])) -#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E])) -#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F])) -#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040])) -#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041])) -#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042])) -#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043])) -#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044])) -#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045])) -#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046])) -#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050])) -#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052])) -#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053])) -#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054])) -#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056])) -#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057])) -#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058])) -#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059])) -#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A])) -#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B])) -#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C])) -#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D])) -#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E])) -#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068])) -#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A])) -#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B])) -#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C])) -#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E])) -#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F])) -#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070])) -#define MCF_GPIO_PTEPAR (*(vuint8 *)(&__IPSBAR[0x100060])) -#define MCF_GPIO_PTFPAR (*(vuint8 *)(&__IPSBAR[0x100061])) -#define MCF_GPIO_PTGPAR (*(vuint8 *)(&__IPSBAR[0x100062])) -#define MCF_GPIO_PTHPAR (*(vuint8 *)(&__IPSBAR[0x100090])) -#define MCF_GPIO_PTIPAR (*(vuint8*)(&__IPSBAR[0x100064])) -#define MCF_GPIO_PTJPAR (*(vuint8*)(&__IPSBAR[0x100066])) -#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071])) -#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072])) -#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073])) -#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074])) -#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075])) -#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076])) -#define MCF_GPIO_PWOR (*(vuint16*)(&__IPSBAR[0x100078])) -#define MCF_GPIO_PDSRH (*(vuint16*)(&__IPSBAR[0x10007A])) -#define MCF_GPIO_PDSRL (*(vuint32*)(&__IPSBAR[0x10007C])) - -/* Bit definitions and macros for MCF_GPIO_PORTNQ */ -#define MCF_GPIO_PORTNQ_PORTNQ0 (0x01) -#define MCF_GPIO_PORTNQ_PORTNQ1 (0x02) -#define MCF_GPIO_PORTNQ_PORTNQ2 (0x04) -#define MCF_GPIO_PORTNQ_PORTNQ3 (0x08) -#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10) -#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20) -#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40) -#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTAN */ -#define MCF_GPIO_PORTAN_PORTAN0 (0x01) -#define MCF_GPIO_PORTAN_PORTAN1 (0x02) -#define MCF_GPIO_PORTAN_PORTAN2 (0x04) -#define MCF_GPIO_PORTAN_PORTAN3 (0x08) -#define MCF_GPIO_PORTAN_PORTAN4 (0x10) -#define MCF_GPIO_PORTAN_PORTAN5 (0x20) -#define MCF_GPIO_PORTAN_PORTAN6 (0x40) -#define MCF_GPIO_PORTAN_PORTAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTAS */ -#define MCF_GPIO_PORTAS_PORTAS0 (0x01) -#define MCF_GPIO_PORTAS_PORTAS1 (0x02) -#define MCF_GPIO_PORTAS_PORTAS2 (0x04) -#define MCF_GPIO_PORTAS_PORTAS3 (0x08) -#define MCF_GPIO_PORTAS_PORTAS4 (0x10) -#define MCF_GPIO_PORTAS_PORTAS5 (0x20) -#define MCF_GPIO_PORTAS_PORTAS6 (0x40) -#define MCF_GPIO_PORTAS_PORTAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTQS */ -#define MCF_GPIO_PORTQS_PORTQS0 (0x01) -#define MCF_GPIO_PORTQS_PORTQS1 (0x02) -#define MCF_GPIO_PORTQS_PORTQS2 (0x04) -#define MCF_GPIO_PORTQS_PORTQS3 (0x08) -#define MCF_GPIO_PORTQS_PORTQS4 (0x10) -#define MCF_GPIO_PORTQS_PORTQS5 (0x20) -#define MCF_GPIO_PORTQS_PORTQS6 (0x40) -#define MCF_GPIO_PORTQS_PORTQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTA */ -#define MCF_GPIO_PORTTA_PORTTA0 (0x01) -#define MCF_GPIO_PORTTA_PORTTA1 (0x02) -#define MCF_GPIO_PORTTA_PORTTA2 (0x04) -#define MCF_GPIO_PORTTA_PORTTA3 (0x08) -#define MCF_GPIO_PORTTA_PORTTA4 (0x10) -#define MCF_GPIO_PORTTA_PORTTA5 (0x20) -#define MCF_GPIO_PORTTA_PORTTA6 (0x40) -#define MCF_GPIO_PORTTA_PORTTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTC */ -#define MCF_GPIO_PORTTC_PORTTC0 (0x01) -#define MCF_GPIO_PORTTC_PORTTC1 (0x02) -#define MCF_GPIO_PORTTC_PORTTC2 (0x04) -#define MCF_GPIO_PORTTC_PORTTC3 (0x08) -#define MCF_GPIO_PORTTC_PORTTC4 (0x10) -#define MCF_GPIO_PORTTC_PORTTC5 (0x20) -#define MCF_GPIO_PORTTC_PORTTC6 (0x40) -#define MCF_GPIO_PORTTC_PORTTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTD */ -#define MCF_GPIO_PORTTD_PORTTD0 (0x01) -#define MCF_GPIO_PORTTD_PORTTD1 (0x02) -#define MCF_GPIO_PORTTD_PORTTD2 (0x04) -#define MCF_GPIO_PORTTD_PORTTD3 (0x08) -#define MCF_GPIO_PORTTD_PORTTD4 (0x10) -#define MCF_GPIO_PORTTD_PORTTD5 (0x20) -#define MCF_GPIO_PORTTD_PORTTD6 (0x40) -#define MCF_GPIO_PORTTD_PORTTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTE */ -#define MCF_GPIO_PORTTE_PORTTE0 (0x01) -#define MCF_GPIO_PORTTE_PORTTE1 (0x02) -#define MCF_GPIO_PORTTE_PORTTE2 (0x04) -#define MCF_GPIO_PORTTE_PORTTE3 (0x08) -#define MCF_GPIO_PORTTE_PORTTE4 (0x10) -#define MCF_GPIO_PORTTE_PORTTE5 (0x20) -#define MCF_GPIO_PORTTE_PORTTE6 (0x40) -#define MCF_GPIO_PORTTE_PORTTE7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTF */ -#define MCF_GPIO_PORTTF_PORTTF0 (0x01) -#define MCF_GPIO_PORTTF_PORTTF1 (0x02) -#define MCF_GPIO_PORTTF_PORTTF2 (0x04) -#define MCF_GPIO_PORTTF_PORTTF3 (0x08) -#define MCF_GPIO_PORTTF_PORTTF4 (0x10) -#define MCF_GPIO_PORTTF_PORTTF5 (0x20) -#define MCF_GPIO_PORTTF_PORTTF6 (0x40) -#define MCF_GPIO_PORTTF_PORTTF7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTG */ -#define MCF_GPIO_PORTTG_PORTTG0 (0x01) -#define MCF_GPIO_PORTTG_PORTTG1 (0x02) -#define MCF_GPIO_PORTTG_PORTTG2 (0x04) -#define MCF_GPIO_PORTTG_PORTTG3 (0x08) -#define MCF_GPIO_PORTTG_PORTTG4 (0x10) -#define MCF_GPIO_PORTTG_PORTTG5 (0x20) -#define MCF_GPIO_PORTTG_PORTTG6 (0x40) -#define MCF_GPIO_PORTTG_PORTTG7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTH */ -#define MCF_GPIO_PORTTH_PORTTH0 (0x01) -#define MCF_GPIO_PORTTH_PORTTH1 (0x02) -#define MCF_GPIO_PORTTH_PORTTH2 (0x04) -#define MCF_GPIO_PORTTH_PORTTH3 (0x08) -#define MCF_GPIO_PORTTH_PORTTH4 (0x10) -#define MCF_GPIO_PORTTH_PORTTH5 (0x20) -#define MCF_GPIO_PORTTH_PORTTH6 (0x40) -#define MCF_GPIO_PORTTH_PORTTH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTTI */ -#define MCF_GPIO_PORTTI_PORTTI0 (0x01) -#define MCF_GPIO_PORTTI_PORTTI1 (0x02) -#define MCF_GPIO_PORTTI_PORTTI2 (0x04) -#define MCF_GPIO_PORTTI_PORTTI3 (0x08) -#define MCF_GPIO_PORTTI_PORTTI4 (0x10) -#define MCF_GPIO_PORTTI_PORTTI5 (0x20) -#define MCF_GPIO_PORTTI_PORTTI6 (0x40) -#define MCF_GPIO_PORTTI_PORTTI7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUA */ -#define MCF_GPIO_PORTUA_PORTUA0 (0x01) -#define MCF_GPIO_PORTUA_PORTUA1 (0x02) -#define MCF_GPIO_PORTUA_PORTUA2 (0x04) -#define MCF_GPIO_PORTUA_PORTUA3 (0x08) -#define MCF_GPIO_PORTUA_PORTUA4 (0x10) -#define MCF_GPIO_PORTUA_PORTUA5 (0x20) -#define MCF_GPIO_PORTUA_PORTUA6 (0x40) -#define MCF_GPIO_PORTUA_PORTUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUB */ -#define MCF_GPIO_PORTUB_PORTUB0 (0x01) -#define MCF_GPIO_PORTUB_PORTUB1 (0x02) -#define MCF_GPIO_PORTUB_PORTUB2 (0x04) -#define MCF_GPIO_PORTUB_PORTUB3 (0x08) -#define MCF_GPIO_PORTUB_PORTUB4 (0x10) -#define MCF_GPIO_PORTUB_PORTUB5 (0x20) -#define MCF_GPIO_PORTUB_PORTUB6 (0x40) -#define MCF_GPIO_PORTUB_PORTUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTUC */ -#define MCF_GPIO_PORTUC_PORTUC0 (0x01) -#define MCF_GPIO_PORTUC_PORTUC1 (0x02) -#define MCF_GPIO_PORTUC_PORTUC2 (0x04) -#define MCF_GPIO_PORTUC_PORTUC3 (0x08) -#define MCF_GPIO_PORTUC_PORTUC4 (0x10) -#define MCF_GPIO_PORTUC_PORTUC5 (0x20) -#define MCF_GPIO_PORTUC_PORTUC6 (0x40) -#define MCF_GPIO_PORTUC_PORTUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTDD */ -#define MCF_GPIO_PORTDD_PORTDD0 (0x01) -#define MCF_GPIO_PORTDD_PORTDD1 (0x02) -#define MCF_GPIO_PORTDD_PORTDD2 (0x04) -#define MCF_GPIO_PORTDD_PORTDD3 (0x08) -#define MCF_GPIO_PORTDD_PORTDD4 (0x10) -#define MCF_GPIO_PORTDD_PORTDD5 (0x20) -#define MCF_GPIO_PORTDD_PORTDD6 (0x40) -#define MCF_GPIO_PORTDD_PORTDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTLD */ -#define MCF_GPIO_PORTLD_PORTLD0 (0x01) -#define MCF_GPIO_PORTLD_PORTLD1 (0x02) -#define MCF_GPIO_PORTLD_PORTLD2 (0x04) -#define MCF_GPIO_PORTLD_PORTLD3 (0x08) -#define MCF_GPIO_PORTLD_PORTLD4 (0x10) -#define MCF_GPIO_PORTLD_PORTLD5 (0x20) -#define MCF_GPIO_PORTLD_PORTLD6 (0x40) -#define MCF_GPIO_PORTLD_PORTLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PORTGP */ -#define MCF_GPIO_PORTGP_PORTGP0 (0x01) -#define MCF_GPIO_PORTGP_PORTGP1 (0x02) -#define MCF_GPIO_PORTGP_PORTGP2 (0x04) -#define MCF_GPIO_PORTGP_PORTGP3 (0x08) -#define MCF_GPIO_PORTGP_PORTGP4 (0x10) -#define MCF_GPIO_PORTGP_PORTGP5 (0x20) -#define MCF_GPIO_PORTGP_PORTGP6 (0x40) -#define MCF_GPIO_PORTGP_PORTGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRNQ */ -#define MCF_GPIO_DDRNQ_DDRNQ0 (0x01) -#define MCF_GPIO_DDRNQ_DDRNQ1 (0x02) -#define MCF_GPIO_DDRNQ_DDRNQ2 (0x04) -#define MCF_GPIO_DDRNQ_DDRNQ3 (0x08) -#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10) -#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20) -#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40) -#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRAN */ -#define MCF_GPIO_DDRAN_DDRAN0 (0x01) -#define MCF_GPIO_DDRAN_DDRAN1 (0x02) -#define MCF_GPIO_DDRAN_DDRAN2 (0x04) -#define MCF_GPIO_DDRAN_DDRAN3 (0x08) -#define MCF_GPIO_DDRAN_DDRAN4 (0x10) -#define MCF_GPIO_DDRAN_DDRAN5 (0x20) -#define MCF_GPIO_DDRAN_DDRAN6 (0x40) -#define MCF_GPIO_DDRAN_DDRAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRAS */ -#define MCF_GPIO_DDRAS_DDRAS0 (0x01) -#define MCF_GPIO_DDRAS_DDRAS1 (0x02) -#define MCF_GPIO_DDRAS_DDRAS2 (0x04) -#define MCF_GPIO_DDRAS_DDRAS3 (0x08) -#define MCF_GPIO_DDRAS_DDRAS4 (0x10) -#define MCF_GPIO_DDRAS_DDRAS5 (0x20) -#define MCF_GPIO_DDRAS_DDRAS6 (0x40) -#define MCF_GPIO_DDRAS_DDRAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRQS */ -#define MCF_GPIO_DDRQS_DDRQS0 (0x01) -#define MCF_GPIO_DDRQS_DDRQS1 (0x02) -#define MCF_GPIO_DDRQS_DDRQS2 (0x04) -#define MCF_GPIO_DDRQS_DDRQS3 (0x08) -#define MCF_GPIO_DDRQS_DDRQS4 (0x10) -#define MCF_GPIO_DDRQS_DDRQS5 (0x20) -#define MCF_GPIO_DDRQS_DDRQS6 (0x40) -#define MCF_GPIO_DDRQS_DDRQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTA */ -#define MCF_GPIO_DDRTA_DDRTA0 (0x01) -#define MCF_GPIO_DDRTA_DDRTA1 (0x02) -#define MCF_GPIO_DDRTA_DDRTA2 (0x04) -#define MCF_GPIO_DDRTA_DDRTA3 (0x08) -#define MCF_GPIO_DDRTA_DDRTA4 (0x10) -#define MCF_GPIO_DDRTA_DDRTA5 (0x20) -#define MCF_GPIO_DDRTA_DDRTA6 (0x40) -#define MCF_GPIO_DDRTA_DDRTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTC */ -#define MCF_GPIO_DDRTC_DDRTC0 (0x01) -#define MCF_GPIO_DDRTC_DDRTC1 (0x02) -#define MCF_GPIO_DDRTC_DDRTC2 (0x04) -#define MCF_GPIO_DDRTC_DDRTC3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_DDRTD */ -#define MCF_GPIO_DDRTD_DDRTD0 (0x01) -#define MCF_GPIO_DDRTD_DDRTD1 (0x02) -#define MCF_GPIO_DDRTD_DDRTD2 (0x04) -#define MCF_GPIO_DDRTD_DDRTD3 (0x08) -#define MCF_GPIO_DDRTD_DDRTD4 (0x10) -#define MCF_GPIO_DDRTD_DDRTD5 (0x20) -#define MCF_GPIO_DDRTD_DDRTD6 (0x40) -#define MCF_GPIO_DDRTD_DDRTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTE */ -#define MCF_GPIO_DDRTE_DDRTE0 (0x01) -#define MCF_GPIO_DDRTE_DDRTE1 (0x02) -#define MCF_GPIO_DDRTE_DDRTE2 (0x04) -#define MCF_GPIO_DDRTE_DDRTE3 (0x08) -#define MCF_GPIO_DDRTE_DDRTE4 (0x10) -#define MCF_GPIO_DDRTE_DDRTE5 (0x20) -#define MCF_GPIO_DDRTE_DDRTE6 (0x40) -#define MCF_GPIO_DDRTE_DDRTE7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTF */ -#define MCF_GPIO_DDRTF_DDRTF0 (0x01) -#define MCF_GPIO_DDRTF_DDRTF1 (0x02) -#define MCF_GPIO_DDRTF_DDRTF2 (0x04) -#define MCF_GPIO_DDRTF_DDRTF3 (0x08) -#define MCF_GPIO_DDRTF_DDRTF4 (0x10) -#define MCF_GPIO_DDRTF_DDRTF5 (0x20) -#define MCF_GPIO_DDRTF_DDRTF6 (0x40) -#define MCF_GPIO_DDRTF_DDRTF7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTG */ -#define MCF_GPIO_DDRTG_DDRTG0 (0x01) -#define MCF_GPIO_DDRTG_DDRTG1 (0x02) -#define MCF_GPIO_DDRTG_DDRTG2 (0x04) -#define MCF_GPIO_DDRTG_DDRTG3 (0x08) -#define MCF_GPIO_DDRTG_DDRTG4 (0x10) -#define MCF_GPIO_DDRTG_DDRTG5 (0x20) -#define MCF_GPIO_DDRTG_DDRTG6 (0x40) -#define MCF_GPIO_DDRTG_DDRTG7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTH */ -#define MCF_GPIO_DDRTH_DDRTH0 (0x01) -#define MCF_GPIO_DDRTH_DDRTH1 (0x02) -#define MCF_GPIO_DDRTH_DDRTH2 (0x04) -#define MCF_GPIO_DDRTH_DDRTH3 (0x08) -#define MCF_GPIO_DDRTH_DDRTH4 (0x10) -#define MCF_GPIO_DDRTH_DDRTH5 (0x20) -#define MCF_GPIO_DDRTH_DDRTH6 (0x40) -#define MCF_GPIO_DDRTH_DDRTH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRTI */ -#define MCF_GPIO_DDRTI_DDRTI0 (0x01) -#define MCF_GPIO_DDRTI_DDRTI1 (0x02) -#define MCF_GPIO_DDRTI_DDRTI2 (0x04) -#define MCF_GPIO_DDRTI_DDRTI3 (0x08) -#define MCF_GPIO_DDRTI_DDRTI4 (0x10) -#define MCF_GPIO_DDRTI_DDRTI5 (0x20) -#define MCF_GPIO_DDRTI_DDRTI6 (0x40) -#define MCF_GPIO_DDRTI_DDRTI7 (0x80) - -/* Bit definiTJons and macros for MCF_GPIO_DDRTJ */ -#define MCF_GPIO_DDRTJ_DDRTJ0 (0x01) -#define MCF_GPIO_DDRTJ_DDRTJ1 (0x02) -#define MCF_GPIO_DDRTJ_DDRTJ2 (0x04) -#define MCF_GPIO_DDRTJ_DDRTJ3 (0x08) -#define MCF_GPIO_DDRTJ_DDRTJ4 (0x10) -#define MCF_GPIO_DDRTJ_DDRTJ5 (0x20) -#define MCF_GPIO_DDRTJ_DDRTJ6 (0x40) -#define MCF_GPIO_DDRTJ_DDRTJ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUA */ -#define MCF_GPIO_DDRUA_DDRUA0 (0x01) -#define MCF_GPIO_DDRUA_DDRUA1 (0x02) -#define MCF_GPIO_DDRUA_DDRUA2 (0x04) -#define MCF_GPIO_DDRUA_DDRUA3 (0x08) -#define MCF_GPIO_DDRUA_DDRUA4 (0x10) -#define MCF_GPIO_DDRUA_DDRUA5 (0x20) -#define MCF_GPIO_DDRUA_DDRUA6 (0x40) -#define MCF_GPIO_DDRUA_DDRUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUB */ -#define MCF_GPIO_DDRUB_DDRUB0 (0x01) -#define MCF_GPIO_DDRUB_DDRUB1 (0x02) -#define MCF_GPIO_DDRUB_DDRUB2 (0x04) -#define MCF_GPIO_DDRUB_DDRUB3 (0x08) -#define MCF_GPIO_DDRUB_DDRUB4 (0x10) -#define MCF_GPIO_DDRUB_DDRUB5 (0x20) -#define MCF_GPIO_DDRUB_DDRUB6 (0x40) -#define MCF_GPIO_DDRUB_DDRUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRUC */ -#define MCF_GPIO_DDRUC_DDRUC0 (0x01) -#define MCF_GPIO_DDRUC_DDRUC1 (0x02) -#define MCF_GPIO_DDRUC_DDRUC2 (0x04) -#define MCF_GPIO_DDRUC_DDRUC3 (0x08) -#define MCF_GPIO_DDRUC_DDRUC4 (0x10) -#define MCF_GPIO_DDRUC_DDRUC5 (0x20) -#define MCF_GPIO_DDRUC_DDRUC6 (0x40) -#define MCF_GPIO_DDRUC_DDRUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRDD */ -#define MCF_GPIO_DDRDD_DDRDD0 (0x01) -#define MCF_GPIO_DDRDD_DDRDD1 (0x02) -#define MCF_GPIO_DDRDD_DDRDD2 (0x04) -#define MCF_GPIO_DDRDD_DDRDD3 (0x08) -#define MCF_GPIO_DDRDD_DDRDD4 (0x10) -#define MCF_GPIO_DDRDD_DDRDD5 (0x20) -#define MCF_GPIO_DDRDD_DDRDD6 (0x40) -#define MCF_GPIO_DDRDD_DDRDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRLD */ -#define MCF_GPIO_DDRLD_DDRLD0 (0x01) -#define MCF_GPIO_DDRLD_DDRLD1 (0x02) -#define MCF_GPIO_DDRLD_DDRLD2 (0x04) -#define MCF_GPIO_DDRLD_DDRLD3 (0x08) -#define MCF_GPIO_DDRLD_DDRLD4 (0x10) -#define MCF_GPIO_DDRLD_DDRLD5 (0x20) -#define MCF_GPIO_DDRLD_DDRLD6 (0x40) -#define MCF_GPIO_DDRLD_DDRLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_DDRGP */ -#define MCF_GPIO_DDRGP_DDRGP0 (0x01) -#define MCF_GPIO_DDRGP_DDRGP1 (0x02) -#define MCF_GPIO_DDRGP_DDRGP2 (0x04) -#define MCF_GPIO_DDRGP_DDRGP3 (0x08) -#define MCF_GPIO_DDRGP_DDRGP4 (0x10) -#define MCF_GPIO_DDRGP_DDRGP5 (0x20) -#define MCF_GPIO_DDRGP_DDRGP6 (0x40) -#define MCF_GPIO_DDRGP_DDRGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETNQ */ -#define MCF_GPIO_SETNQ_SETNQ0 (0x01) -#define MCF_GPIO_SETNQ_SETNQ1 (0x02) -#define MCF_GPIO_SETNQ_SETNQ2 (0x04) -#define MCF_GPIO_SETNQ_SETNQ3 (0x08) -#define MCF_GPIO_SETNQ_SETNQ4 (0x10) -#define MCF_GPIO_SETNQ_SETNQ5 (0x20) -#define MCF_GPIO_SETNQ_SETNQ6 (0x40) -#define MCF_GPIO_SETNQ_SETNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETAN */ -#define MCF_GPIO_SETAN_SETAN0 (0x01) -#define MCF_GPIO_SETAN_SETAN1 (0x02) -#define MCF_GPIO_SETAN_SETAN2 (0x04) -#define MCF_GPIO_SETAN_SETAN3 (0x08) -#define MCF_GPIO_SETAN_SETAN4 (0x10) -#define MCF_GPIO_SETAN_SETAN5 (0x20) -#define MCF_GPIO_SETAN_SETAN6 (0x40) -#define MCF_GPIO_SETAN_SETAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETAS */ -#define MCF_GPIO_SETAS_SETAS0 (0x01) -#define MCF_GPIO_SETAS_SETAS1 (0x02) -#define MCF_GPIO_SETAS_SETAS2 (0x04) -#define MCF_GPIO_SETAS_SETAS3 (0x08) -#define MCF_GPIO_SETAS_SETAS4 (0x10) -#define MCF_GPIO_SETAS_SETAS5 (0x20) -#define MCF_GPIO_SETAS_SETAS6 (0x40) -#define MCF_GPIO_SETAS_SETAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETQS */ -#define MCF_GPIO_SETQS_SETQS0 (0x01) -#define MCF_GPIO_SETQS_SETQS1 (0x02) -#define MCF_GPIO_SETQS_SETQS2 (0x04) -#define MCF_GPIO_SETQS_SETQS3 (0x08) -#define MCF_GPIO_SETQS_SETQS4 (0x10) -#define MCF_GPIO_SETQS_SETQS5 (0x20) -#define MCF_GPIO_SETQS_SETQS6 (0x40) -#define MCF_GPIO_SETQS_SETQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTA */ -#define MCF_GPIO_SETTA_SETTA0 (0x01) -#define MCF_GPIO_SETTA_SETTA1 (0x02) -#define MCF_GPIO_SETTA_SETTA2 (0x04) -#define MCF_GPIO_SETTA_SETTA3 (0x08) -#define MCF_GPIO_SETTA_SETTA4 (0x10) -#define MCF_GPIO_SETTA_SETTA5 (0x20) -#define MCF_GPIO_SETTA_SETTA6 (0x40) -#define MCF_GPIO_SETTA_SETTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTC */ -#define MCF_GPIO_SETTC_SETTC0 (0x01) -#define MCF_GPIO_SETTC_SETTC1 (0x02) -#define MCF_GPIO_SETTC_SETTC2 (0x04) -#define MCF_GPIO_SETTC_SETTC3 (0x08) -#define MCF_GPIO_SETTC_SETTC4 (0x10) -#define MCF_GPIO_SETTC_SETTC5 (0x20) -#define MCF_GPIO_SETTC_SETTC6 (0x40) -#define MCF_GPIO_SETTC_SETTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETTD */ -#define MCF_GPIO_SETTD_SETTD0 (0x01) -#define MCF_GPIO_SETTD_SETTD1 (0x02) -#define MCF_GPIO_SETTD_SETTD2 (0x04) -#define MCF_GPIO_SETTD_SETTD3 (0x08) -#define MCF_GPIO_SETTD_SETTD4 (0x10) -#define MCF_GPIO_SETTD_SETTD5 (0x20) -#define MCF_GPIO_SETTD_SETTD6 (0x40) -#define MCF_GPIO_SETTD_SETTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUA */ -#define MCF_GPIO_SETUA_SETUA0 (0x01) -#define MCF_GPIO_SETUA_SETUA1 (0x02) -#define MCF_GPIO_SETUA_SETUA2 (0x04) -#define MCF_GPIO_SETUA_SETUA3 (0x08) -#define MCF_GPIO_SETUA_SETUA4 (0x10) -#define MCF_GPIO_SETUA_SETUA5 (0x20) -#define MCF_GPIO_SETUA_SETUA6 (0x40) -#define MCF_GPIO_SETUA_SETUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUB */ -#define MCF_GPIO_SETUB_SETUB0 (0x01) -#define MCF_GPIO_SETUB_SETUB1 (0x02) -#define MCF_GPIO_SETUB_SETUB2 (0x04) -#define MCF_GPIO_SETUB_SETUB3 (0x08) -#define MCF_GPIO_SETUB_SETUB4 (0x10) -#define MCF_GPIO_SETUB_SETUB5 (0x20) -#define MCF_GPIO_SETUB_SETUB6 (0x40) -#define MCF_GPIO_SETUB_SETUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETUC */ -#define MCF_GPIO_SETUC_SETUC0 (0x01) -#define MCF_GPIO_SETUC_SETUC1 (0x02) -#define MCF_GPIO_SETUC_SETUC2 (0x04) -#define MCF_GPIO_SETUC_SETUC3 (0x08) -#define MCF_GPIO_SETUC_SETUC4 (0x10) -#define MCF_GPIO_SETUC_SETUC5 (0x20) -#define MCF_GPIO_SETUC_SETUC6 (0x40) -#define MCF_GPIO_SETUC_SETUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETDD */ -#define MCF_GPIO_SETDD_SETDD0 (0x01) -#define MCF_GPIO_SETDD_SETDD1 (0x02) -#define MCF_GPIO_SETDD_SETDD2 (0x04) -#define MCF_GPIO_SETDD_SETDD3 (0x08) -#define MCF_GPIO_SETDD_SETDD4 (0x10) -#define MCF_GPIO_SETDD_SETDD5 (0x20) -#define MCF_GPIO_SETDD_SETDD6 (0x40) -#define MCF_GPIO_SETDD_SETDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETLD */ -#define MCF_GPIO_SETLD_SETLD0 (0x01) -#define MCF_GPIO_SETLD_SETLD1 (0x02) -#define MCF_GPIO_SETLD_SETLD2 (0x04) -#define MCF_GPIO_SETLD_SETLD3 (0x08) -#define MCF_GPIO_SETLD_SETLD4 (0x10) -#define MCF_GPIO_SETLD_SETLD5 (0x20) -#define MCF_GPIO_SETLD_SETLD6 (0x40) -#define MCF_GPIO_SETLD_SETLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_SETGP */ -#define MCF_GPIO_SETGP_SETGP0 (0x01) -#define MCF_GPIO_SETGP_SETGP1 (0x02) -#define MCF_GPIO_SETGP_SETGP2 (0x04) -#define MCF_GPIO_SETGP_SETGP3 (0x08) -#define MCF_GPIO_SETGP_SETGP4 (0x10) -#define MCF_GPIO_SETGP_SETGP5 (0x20) -#define MCF_GPIO_SETGP_SETGP6 (0x40) -#define MCF_GPIO_SETGP_SETGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRNQ */ -#define MCF_GPIO_CLRNQ_CLRNQ0 (0x01) -#define MCF_GPIO_CLRNQ_CLRNQ1 (0x02) -#define MCF_GPIO_CLRNQ_CLRNQ2 (0x04) -#define MCF_GPIO_CLRNQ_CLRNQ3 (0x08) -#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10) -#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20) -#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40) -#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRAN */ -#define MCF_GPIO_CLRAN_CLRAN0 (0x01) -#define MCF_GPIO_CLRAN_CLRAN1 (0x02) -#define MCF_GPIO_CLRAN_CLRAN2 (0x04) -#define MCF_GPIO_CLRAN_CLRAN3 (0x08) -#define MCF_GPIO_CLRAN_CLRAN4 (0x10) -#define MCF_GPIO_CLRAN_CLRAN5 (0x20) -#define MCF_GPIO_CLRAN_CLRAN6 (0x40) -#define MCF_GPIO_CLRAN_CLRAN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRAS */ -#define MCF_GPIO_CLRAS_CLRAS0 (0x01) -#define MCF_GPIO_CLRAS_CLRAS1 (0x02) -#define MCF_GPIO_CLRAS_CLRAS2 (0x04) -#define MCF_GPIO_CLRAS_CLRAS3 (0x08) -#define MCF_GPIO_CLRAS_CLRAS4 (0x10) -#define MCF_GPIO_CLRAS_CLRAS5 (0x20) -#define MCF_GPIO_CLRAS_CLRAS6 (0x40) -#define MCF_GPIO_CLRAS_CLRAS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRQS */ -#define MCF_GPIO_CLRQS_CLRQS0 (0x01) -#define MCF_GPIO_CLRQS_CLRQS1 (0x02) -#define MCF_GPIO_CLRQS_CLRQS2 (0x04) -#define MCF_GPIO_CLRQS_CLRQS3 (0x08) -#define MCF_GPIO_CLRQS_CLRQS4 (0x10) -#define MCF_GPIO_CLRQS_CLRQS5 (0x20) -#define MCF_GPIO_CLRQS_CLRQS6 (0x40) -#define MCF_GPIO_CLRQS_CLRQS7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTA */ -#define MCF_GPIO_CLRTA_CLRTA0 (0x01) -#define MCF_GPIO_CLRTA_CLRTA1 (0x02) -#define MCF_GPIO_CLRTA_CLRTA2 (0x04) -#define MCF_GPIO_CLRTA_CLRTA3 (0x08) -#define MCF_GPIO_CLRTA_CLRTA4 (0x10) -#define MCF_GPIO_CLRTA_CLRTA5 (0x20) -#define MCF_GPIO_CLRTA_CLRTA6 (0x40) -#define MCF_GPIO_CLRTA_CLRTA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTC */ -#define MCF_GPIO_CLRTC_CLRTC0 (0x01) -#define MCF_GPIO_CLRTC_CLRTC1 (0x02) -#define MCF_GPIO_CLRTC_CLRTC2 (0x04) -#define MCF_GPIO_CLRTC_CLRTC3 (0x08) -#define MCF_GPIO_CLRTC_CLRTC4 (0x10) -#define MCF_GPIO_CLRTC_CLRTC5 (0x20) -#define MCF_GPIO_CLRTC_CLRTC6 (0x40) -#define MCF_GPIO_CLRTC_CLRTC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRTD */ -#define MCF_GPIO_CLRTD_CLRTD0 (0x01) -#define MCF_GPIO_CLRTD_CLRTD1 (0x02) -#define MCF_GPIO_CLRTD_CLRTD2 (0x04) -#define MCF_GPIO_CLRTD_CLRTD3 (0x08) -#define MCF_GPIO_CLRTD_CLRTD4 (0x10) -#define MCF_GPIO_CLRTD_CLRTD5 (0x20) -#define MCF_GPIO_CLRTD_CLRTD6 (0x40) -#define MCF_GPIO_CLRTD_CLRTD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUA */ -#define MCF_GPIO_CLRUA_CLRUA0 (0x01) -#define MCF_GPIO_CLRUA_CLRUA1 (0x02) -#define MCF_GPIO_CLRUA_CLRUA2 (0x04) -#define MCF_GPIO_CLRUA_CLRUA3 (0x08) -#define MCF_GPIO_CLRUA_CLRUA4 (0x10) -#define MCF_GPIO_CLRUA_CLRUA5 (0x20) -#define MCF_GPIO_CLRUA_CLRUA6 (0x40) -#define MCF_GPIO_CLRUA_CLRUA7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUB */ -#define MCF_GPIO_CLRUB_CLRUB0 (0x01) -#define MCF_GPIO_CLRUB_CLRUB1 (0x02) -#define MCF_GPIO_CLRUB_CLRUB2 (0x04) -#define MCF_GPIO_CLRUB_CLRUB3 (0x08) -#define MCF_GPIO_CLRUB_CLRUB4 (0x10) -#define MCF_GPIO_CLRUB_CLRUB5 (0x20) -#define MCF_GPIO_CLRUB_CLRUB6 (0x40) -#define MCF_GPIO_CLRUB_CLRUB7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRUC */ -#define MCF_GPIO_CLRUC_CLRUC0 (0x01) -#define MCF_GPIO_CLRUC_CLRUC1 (0x02) -#define MCF_GPIO_CLRUC_CLRUC2 (0x04) -#define MCF_GPIO_CLRUC_CLRUC3 (0x08) -#define MCF_GPIO_CLRUC_CLRUC4 (0x10) -#define MCF_GPIO_CLRUC_CLRUC5 (0x20) -#define MCF_GPIO_CLRUC_CLRUC6 (0x40) -#define MCF_GPIO_CLRUC_CLRUC7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRDD */ -#define MCF_GPIO_CLRDD_CLRDD0 (0x01) -#define MCF_GPIO_CLRDD_CLRDD1 (0x02) -#define MCF_GPIO_CLRDD_CLRDD2 (0x04) -#define MCF_GPIO_CLRDD_CLRDD3 (0x08) -#define MCF_GPIO_CLRDD_CLRDD4 (0x10) -#define MCF_GPIO_CLRDD_CLRDD5 (0x20) -#define MCF_GPIO_CLRDD_CLRDD6 (0x40) -#define MCF_GPIO_CLRDD_CLRDD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRLD */ -#define MCF_GPIO_CLRLD_CLRLD0 (0x01) -#define MCF_GPIO_CLRLD_CLRLD1 (0x02) -#define MCF_GPIO_CLRLD_CLRLD2 (0x04) -#define MCF_GPIO_CLRLD_CLRLD3 (0x08) -#define MCF_GPIO_CLRLD_CLRLD4 (0x10) -#define MCF_GPIO_CLRLD_CLRLD5 (0x20) -#define MCF_GPIO_CLRLD_CLRLD6 (0x40) -#define MCF_GPIO_CLRLD_CLRLD7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_CLRGP */ -#define MCF_GPIO_CLRGP_CLRGP0 (0x01) -#define MCF_GPIO_CLRGP_CLRGP1 (0x02) -#define MCF_GPIO_CLRGP_CLRGP2 (0x04) -#define MCF_GPIO_CLRGP_CLRGP3 (0x08) -#define MCF_GPIO_CLRGP_CLRGP4 (0x10) -#define MCF_GPIO_CLRGP_CLRGP5 (0x20) -#define MCF_GPIO_CLRGP_CLRGP6 (0x40) -#define MCF_GPIO_CLRGP_CLRGP7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTIPAR */ -#define MCF_GPIO_PTIPAR_PTIPAR0 (0x01) -#define MCF_GPIO_PTIPAR_PTIPAR1 (0x02) -#define MCF_GPIO_PTIPAR_PTIPAR2 (0x04) -#define MCF_GPIO_PTIPAR_PTIPAR3 (0x08) -#define MCF_GPIO_PTIPAR_PTIPAR4 (0x10) -#define MCF_GPIO_PTIPAR_PTIPAR5 (0x20) -#define MCF_GPIO_PTIPAR_PTIPAR6 (0x40) -#define MCF_GPIO_PTIPAR_PTIPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTJPAR */ -#define MCF_GPIO_PTJPAR_PTJPAR0 (0x01) -#define MCF_GPIO_PTJPAR_PTJPAR1 (0x02) -#define MCF_GPIO_PTJPAR_PTJPAR2 (0x04) -#define MCF_GPIO_PTJPAR_PTJPAR3 (0x08) -#define MCF_GPIO_PTJPAR_PTJPAR4 (0x10) -#define MCF_GPIO_PTJPAR_PTJPAR5 (0x20) -#define MCF_GPIO_PTJPAR_PTJPAR6 (0x40) -#define MCF_GPIO_PTJPAR_PTJPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PNQPAR */ -#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x0003)<<14) -#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0x0000) -#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x0004) -#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x0010) -#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x0040) -#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x0100) -#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x0400) -#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000) -#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000) -#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x0008) -#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0x000C) - -/* Bit definitions and macros for MCF_GPIO_PANPAR */ -#define MCF_GPIO_PANPAR_PANPAR0 (0x01) -#define MCF_GPIO_PANPAR_PANPAR1 (0x02) -#define MCF_GPIO_PANPAR_PANPAR2 (0x04) -#define MCF_GPIO_PANPAR_PANPAR3 (0x08) -#define MCF_GPIO_PANPAR_PANPAR4 (0x10) -#define MCF_GPIO_PANPAR_PANPAR5 (0x20) -#define MCF_GPIO_PANPAR_PANPAR6 (0x40) -#define MCF_GPIO_PANPAR_PANPAR7 (0x80) -#define MCF_GPIO_PANPAR_AN0_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN1_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN2_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN3_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN4_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN5_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN6_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN7_GPIO (0x00) -#define MCF_GPIO_PANPAR_AN0_AN0 (0x01) -#define MCF_GPIO_PANPAR_AN1_AN1 (0x02) -#define MCF_GPIO_PANPAR_AN2_AN2 (0x04) -#define MCF_GPIO_PANPAR_AN3_AN3 (0x08) -#define MCF_GPIO_PANPAR_AN4_AN4 (0x10) -#define MCF_GPIO_PANPAR_AN5_AN5 (0x20) -#define MCF_GPIO_PANPAR_AN6_AN6 (0x40) -#define MCF_GPIO_PANPAR_AN7_AN7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PASPAR */ -#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PASPAR_SCL_GPIO (0x00) -#define MCF_GPIO_PASPAR_SDA_GPIO (0x00) -#define MCF_GPIO_PASPAR_SYNCA_GPIO (0x00) -#define MCF_GPIO_PASPAR_SYNCB_GPIO (0x00) -#define MCF_GPIO_PASPAR_SCL_SCL (0x01) -#define MCF_GPIO_PASPAR_SDA_SDA (0x04) -#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x10) -#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x40) -#define MCF_GPIO_PASPAR_SCL_CANTX (0x02) -#define MCF_GPIO_PASPAR_SDA_CANRX (0x08) -#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x20) -#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x80) -#define MCF_GPIO_PASPAR_SCL_TXD2 (0x30) -#define MCF_GPIO_PASPAR_SDA_RXD2 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PQSPAR */ -#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PQSPAR_DOUT_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_DIN_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_SCK_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS0_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS1_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS2_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_CS3_GPIO (0x0000) -#define MCF_GPIO_PQSPAR_DOUT_DOUT (0x0001) -#define MCF_GPIO_PQSPAR_DIN_DIN (0x0004) -#define MCF_GPIO_PQSPAR_SCK_SCK (0x0010) -#define MCF_GPIO_PQSPAR_CS0_CS0 (0x0040) -#define MCF_GPIO_PQSPAR_CS1_CS1 (0x0100) -#define MCF_GPIO_PQSPAR_CS2_CS2 (0x0400) -#define MCF_GPIO_PQSPAR_CS3_CS3 (0x1000) -#define MCF_GPIO_PQSPAR_DOUT_CANTX (0x0002) -#define MCF_GPIO_PQSPAR_DIN_CANRX (0x0008) -#define MCF_GPIO_PQSPAR_SCK_SCL (0x0020) -#define MCF_GPIO_PQSPAR_CS0_SDA (0x0080) -#define MCF_GPIO_PQSPAR_CS3_SYNCA (0x2000) -#define MCF_GPIO_PQSPAR_DOUT_TXD1 (0x0003) -#define MCF_GPIO_PQSPAR_DIN_RXD1 (0x000C) -#define MCF_GPIO_PQSPAR_SCK_RTS1 (0x0030) -#define MCF_GPIO_PQSPAR_CS0_CTS1 (0x00C0) -#define MCF_GPIO_PQSPAR_CS3_SYNCB (0x3000) - -/* Bit definitions and macros for MCF_GPIO_PTAPAR */ -#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PTAPAR_ICOC0_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC1_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC2_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC3_GPIO (0x00) -#define MCF_GPIO_PTAPAR_ICOC0_ICOC0 (0x01) -#define MCF_GPIO_PTAPAR_ICOC1_ICOC1 (0x04) -#define MCF_GPIO_PTAPAR_ICOC2_ICOC2 (0x10) -#define MCF_GPIO_PTAPAR_ICOC3_ICOC3 (0x40) -#define MCF_GPIO_PTAPAR_ICOC0_PWM1 (0x02) -#define MCF_GPIO_PTAPAR_ICOC1_PWM3 (0x08) -#define MCF_GPIO_PTAPAR_ICOC2_PWM5 (0x20) -#define MCF_GPIO_PTAPAR_ICOC3_PWM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTCPAR */ -#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PTCPAR_TIN0_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN1_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN2_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN3_GPIO (0x00) -#define MCF_GPIO_PTCPAR_TIN0_TIN0 (0x01) -#define MCF_GPIO_PTCPAR_TIN1_TIN1 (0x04) -#define MCF_GPIO_PTCPAR_TIN2_TIN2 (0x10) -#define MCF_GPIO_PTCPAR_TIN3_TIN3 (0x40) -#define MCF_GPIO_PTCPAR_TIN0_TOUT0 (0x02) -#define MCF_GPIO_PTCPAR_TIN1_TOUT1 (0x08) -#define MCF_GPIO_PTCPAR_TIN2_TOUT2 (0x20) -#define MCF_GPIO_PTCPAR_TIN3_TOUT3 (0x80) -#define MCF_GPIO_PTCPAR_TIN0_PWM0 (0x03) -#define MCF_GPIO_PTCPAR_TIN1_PWM2 (0x0C) -#define MCF_GPIO_PTCPAR_TIN2_PWM4 (0x30) -#define MCF_GPIO_PTCPAR_TIN3_PWM6 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PTDPAR */ -#define MCF_GPIO_PTDPAR_PTDPAR0 (0x01) -#define MCF_GPIO_PTDPAR_PTDPAR1 (0x02) -#define MCF_GPIO_PTDPAR_PTDPAR2 (0x04) -#define MCF_GPIO_PTDPAR_PTDPAR3 (0x08) -#define MCF_GPIO_PTDPAR_PWM1_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM3_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM5_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM7_GPIO (0x00) -#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x01) -#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x02) -#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x04) -#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PTEPAR */ -#define MCF_GPIO_PTEPAR_PTEPAR0 (0x01) -#define MCF_GPIO_PTEPAR_PTEPAR1 (0x02) -#define MCF_GPIO_PTEPAR_PTEPAR2 (0x04) -#define MCF_GPIO_PTEPAR_PTEPAR3 (0x08) -#define MCF_GPIO_PTEPAR_PTEPAR4 (0x10) -#define MCF_GPIO_PTEPAR_PTEPAR5 (0x20) -#define MCF_GPIO_PTEPAR_PTEPAR6 (0x40) -#define MCF_GPIO_PTEPAR_PTEPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTFPAR */ -#define MCF_GPIO_PTFPAR_PTFPAR0 (0x01) -#define MCF_GPIO_PTFPAR_PTFPAR1 (0x02) -#define MCF_GPIO_PTFPAR_PTFPAR2 (0x04) -#define MCF_GPIO_PTFPAR_PTFPAR3 (0x08) -#define MCF_GPIO_PTFPAR_PTFPAR4 (0x10) -#define MCF_GPIO_PTFPAR_PTFPAR5 (0x20) -#define MCF_GPIO_PTFPAR_PTFPAR6 (0x40) -#define MCF_GPIO_PTFPAR_PTFPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTGPAR */ -#define MCF_GPIO_PTGPAR_PTGPAR0 (0x01) -#define MCF_GPIO_PTGPAR_PTGPAR1 (0x02) -#define MCF_GPIO_PTGPAR_PTGPAR2 (0x04) -#define MCF_GPIO_PTGPAR_PTGPAR3 (0x08) -#define MCF_GPIO_PTGPAR_PTGPAR4 (0x10) -#define MCF_GPIO_PTGPAR_PTGPAR5 (0x20) -#define MCF_GPIO_PTGPAR_PTGPAR6 (0x40) -#define MCF_GPIO_PTGPAR_PTGPAR7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PTHPAR */ -#define MCF_GPIO_PTHPAR_PTHPAR0(x) (((x)&0x0003)<<0) -#define MCF_GPIO_PTHPAR_PTHPAR1(x) (((x)&0x0003)<<2) -#define MCF_GPIO_PTHPAR_PTHPAR2(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PTHPAR_PTHPAR3(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PTHPAR_PTHPAR4(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PTHPAR_PTHPAR5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PTHPAR_PTHPAR6(x) (((x)&0x0003)<<12) - - -/* Bit definitions and macros for MCF_GPIO_PUAPAR */ -#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PUAPAR_TXD0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_RXD0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_RTS0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_CTS0_GPIO (0x00) -#define MCF_GPIO_PUAPAR_TXD0_TXD0 (0x01) -#define MCF_GPIO_PUAPAR_RXD0_RXD0 (0x04) -#define MCF_GPIO_PUAPAR_RTS0_RTS0 (0x10) -#define MCF_GPIO_PUAPAR_CTS0_CTS0 (0x40) -#define MCF_GPIO_PUAPAR_RTS0_CANTX (0x20) -#define MCF_GPIO_PUAPAR_CTS0_CANRX (0x80) - -/* Bit definitions and macros for MCF_GPIO_PUBPAR */ -#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PUBPAR_TXD1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_RXD1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_RTS1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_CTS1_GPIO (0x00) -#define MCF_GPIO_PUBPAR_TXD1_TXD1 (0x01) -#define MCF_GPIO_PUBPAR_RXD1_RXD1 (0x04) -#define MCF_GPIO_PUBPAR_RTS1_RTS1 (0x10) -#define MCF_GPIO_PUBPAR_CTS1_CTS1 (0x40) -#define MCF_GPIO_PUBPAR_RTS1_SYNCB (0x20) -#define MCF_GPIO_PUBPAR_CTS1_SYNCA (0x80) -#define MCF_GPIO_PUBPAR_RTS1_TXD2 (0x30) -#define MCF_GPIO_PUBPAR_CTS1_RXD2 (0xC0) - -/* Bit definitions and macros for MCF_GPIO_PUCPAR */ -#define MCF_GPIO_PUCPAR_PUCPAR0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PUCPAR_PUCPAR1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PUCPAR_PUCPAR2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PUCPAR_PUCPAR3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PUCPAR_TXD2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_RXD2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_RTS2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_CTS2_GPIO (0x00) -#define MCF_GPIO_PUCPAR_TXD2_TXD2 (0x01) -#define MCF_GPIO_PUCPAR_RXD2_RXD2 (0x02) -#define MCF_GPIO_PUCPAR_RTS2_RTS2 (0x04) -#define MCF_GPIO_PUCPAR_CTS2_CTS2 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDPAR */ -#define MCF_GPIO_PDDPAR_PDDPAR0 (0x01) -#define MCF_GPIO_PDDPAR_PDDPAR1 (0x02) -#define MCF_GPIO_PDDPAR_PDDPAR2 (0x04) -#define MCF_GPIO_PDDPAR_PDDPAR3 (0x08) -#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10) -#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20) -#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40) -#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80) -#define MCF_GPIO_PDDPAR_PDD0_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD1_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD2_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD3_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD4_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD5_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD6_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD7_GPIO (0x00) -#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x01) -#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x02) -#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x04) -#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x08) -#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10) -#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20) -#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40) -#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PLDPAR */ -#define MCF_GPIO_PLDPAR_PLDPAR0 (0x01) -#define MCF_GPIO_PLDPAR_PLDPAR1 (0x02) -#define MCF_GPIO_PLDPAR_PLDPAR2 (0x04) -#define MCF_GPIO_PLDPAR_PLDPAR3 (0x08) -#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10) -#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20) -#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40) -#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_LNKLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_COLLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_RXLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_TXLED_GPIO (0x00) -#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x01) -#define MCF_GPIO_PLDPAR_LNKLED_LNKLED (0x02) -#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x04) -#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x08) -#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10) -#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20) -#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40) - -/* Bit definitions and macros for MCF_GPIO_PGPPAR */ -#define MCF_GPIO_PGPPAR_PGPPAR0 (0x01) -#define MCF_GPIO_PGPPAR_PGPPAR1 (0x02) -#define MCF_GPIO_PGPPAR_PGPPAR2 (0x04) -#define MCF_GPIO_PGPPAR_PGPPAR3 (0x08) -#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10) -#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20) -#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40) -#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80) -#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0x00) -#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x01) -#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x02) -#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x04) -#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x08) -#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10) -#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x30) -#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40) -#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PWOR */ -#define MCF_GPIO_PWOR_PWOR0 (0x0001) -#define MCF_GPIO_PWOR_PWOR1 (0x0002) -#define MCF_GPIO_PWOR_PWOR2 (0x0004) -#define MCF_GPIO_PWOR_PWOR3 (0x0008) -#define MCF_GPIO_PWOR_PWOR4 (0x0010) -#define MCF_GPIO_PWOR_PWOR5 (0x0020) -#define MCF_GPIO_PWOR_PWOR6 (0x0040) -#define MCF_GPIO_PWOR_PWOR7 (0x0080) -#define MCF_GPIO_PWOR_PWOR8 (0x0100) -#define MCF_GPIO_PWOR_PWOR9 (0x0200) -#define MCF_GPIO_PWOR_PWOR10 (0x0400) -#define MCF_GPIO_PWOR_PWOR11 (0x0800) -#define MCF_GPIO_PWOR_PWOR12 (0x1000) -#define MCF_GPIO_PWOR_PWOR13 (0x2000) -#define MCF_GPIO_PWOR_PWOR14 (0x4000) -#define MCF_GPIO_PWOR_PWOR15 (0x8000) - -/* Bit definitions and macros for MCF_GPIO_PDSRH */ -#define MCF_GPIO_PDSRH_PDSR32 (0x0001) -#define MCF_GPIO_PDSRH_PDSR33 (0x0002) -#define MCF_GPIO_PDSRH_PDSR34 (0x0004) -#define MCF_GPIO_PDSRH_PDSR35 (0x0008) -#define MCF_GPIO_PDSRH_PDSR36 (0x0010) -#define MCF_GPIO_PDSRH_PDSR37 (0x0020) -#define MCF_GPIO_PDSRH_PDSR38 (0x0040) -#define MCF_GPIO_PDSRH_PDSR39 (0x0080) -#define MCF_GPIO_PDSRH_PDSR40 (0x0100) -#define MCF_GPIO_PDSRH_PDSR41 (0x0200) -#define MCF_GPIO_PDSRH_PDSR42 (0x0400) -#define MCF_GPIO_PDSRH_PDSR43 (0x0800) -#define MCF_GPIO_PDSRH_PDSR44 (0x1000) -#define MCF_GPIO_PDSRH_PDSR45 (0x2000) -#define MCF_GPIO_PDSRH_PDSR46 (0x4000) -#define MCF_GPIO_PDSRH_PDSR47 (0x8000) - -/* Bit definitions and macros for MCF_GPIO_PDSRL */ -#define MCF_GPIO_PDSRL_PDSR0 (0x00000001) -#define MCF_GPIO_PDSRL_PDSR1 (0x00000002) -#define MCF_GPIO_PDSRL_PDSR2 (0x00000004) -#define MCF_GPIO_PDSRL_PDSR3 (0x00000008) -#define MCF_GPIO_PDSRL_PDSR4 (0x00000010) -#define MCF_GPIO_PDSRL_PDSR5 (0x00000020) -#define MCF_GPIO_PDSRL_PDSR6 (0x00000040) -#define MCF_GPIO_PDSRL_PDSR7 (0x00000080) -#define MCF_GPIO_PDSRL_PDSR8 (0x00000100) -#define MCF_GPIO_PDSRL_PDSR9 (0x00000200) -#define MCF_GPIO_PDSRL_PDSR10 (0x00000400) -#define MCF_GPIO_PDSRL_PDSR11 (0x00000800) -#define MCF_GPIO_PDSRL_PDSR12 (0x00001000) -#define MCF_GPIO_PDSRL_PDSR13 (0x00002000) -#define MCF_GPIO_PDSRL_PDSR14 (0x00004000) -#define MCF_GPIO_PDSRL_PDSR15 (0x00008000) -#define MCF_GPIO_PDSRL_PDSR16 (0x00010000) -#define MCF_GPIO_PDSRL_PDSR17 (0x00020000) -#define MCF_GPIO_PDSRL_PDSR18 (0x00040000) -#define MCF_GPIO_PDSRL_PDSR19 (0x00080000) -#define MCF_GPIO_PDSRL_PDSR20 (0x00100000) -#define MCF_GPIO_PDSRL_PDSR21 (0x00200000) -#define MCF_GPIO_PDSRL_PDSR22 (0x00400000) -#define MCF_GPIO_PDSRL_PDSR23 (0x00800000) -#define MCF_GPIO_PDSRL_PDSR24 (0x01000000) -#define MCF_GPIO_PDSRL_PDSR25 (0x02000000) -#define MCF_GPIO_PDSRL_PDSR26 (0x04000000) -#define MCF_GPIO_PDSRL_PDSR27 (0x08000000) -#define MCF_GPIO_PDSRL_PDSR28 (0x10000000) -#define MCF_GPIO_PDSRL_PDSR29 (0x20000000) -#define MCF_GPIO_PDSRL_PDSR30 (0x40000000) -#define MCF_GPIO_PDSRL_PDSR31 (0x80000000) - -/********************************************************************* -* -* ColdFire Integration Module (CIM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CIM_RCR (*(vuint8 *)(&__IPSBAR[0x110000])) -#define MCF_CIM_RSR (*(vuint8 *)(&__IPSBAR[0x110001])) -#define MCF_CIM_CCR (*(vuint16*)(&__IPSBAR[0x110004])) -#define MCF_CIM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007])) -#define MCF_CIM_RCON (*(vuint16*)(&__IPSBAR[0x110008])) -#define MCF_CIM_CIR (*(vuint16*)(&__IPSBAR[0x11000A])) - -/* Bit definitions and macros for MCF_CIM_RCR */ -#define MCF_CIM_RCR_LVDE (0x01) -#define MCF_CIM_RCR_LVDRE (0x04) -#define MCF_CIM_RCR_LVDIE (0x08) -#define MCF_CIM_RCR_LVDF (0x10) -#define MCF_CIM_RCR_FRCRSTOUT (0x40) -#define MCF_CIM_RCR_SOFTRST (0x80) - -/* Bit definitions and macros for MCF_CIM_RSR */ -#define MCF_CIM_RSR_LOL (0x01) -#define MCF_CIM_RSR_LOC (0x02) -#define MCF_CIM_RSR_EXT (0x04) -#define MCF_CIM_RSR_POR (0x08) -#define MCF_CIM_RSR_WDR (0x10) -#define MCF_CIM_RSR_SOFT (0x20) -#define MCF_CIM_RSR_LVD (0x40) - -/* Bit definitions and macros for MCF_CIM_CCR */ -#define MCF_CIM_CCR_LOAD (0x8000) -#define MCF_CIM_CCR_EZPORT (0x05) -#define MCF_CIM_CCR_SCHIP (0x06) -#define MCF_CIM_CCR_MODE(x) (((x)&0x7)<<8) - -/* Bit definitions and macros for MCF_CIM_LPCR */ -#define MCF_CIM_LPCR_LVDSE (0x02) -#define MCF_CIM_LPCR_STPMD(x) (((x)&0x03)<<3) -#define MCF_CIM_LPCR_LPMD(x) (((x)&0x03)<<6) -#define MCF_CIM_LPCR_LPMD_STOP (0xC0) -#define MCF_CIM_LPCR_LPMD_WAIT (0x80) -#define MCF_CIM_LPCR_LPMD_DOZE (0x40) -#define MCF_CIM_LPCR_LPMD_RUN (0x00) - -/* Bit definitions and macros for MCF_CIM_RCON */ -#define MCF_CIM_RCON_RLOAD (0x0020) - -/********************************************************************* -* -* Clock Module (CLOCK) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000])) -#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002])) -#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007])) -#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008])) -#define MCF_CLOCK_CCLR (*(vuint8 *)(&__IPSBAR[0x120009])) -#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C])) -#define MCF_CLOCK_RTCCR (*(vuint8*)(&__IPSBAR[0x120012])) - -/* Bit definitions and macros for MCF_CLOCK_SYNCR */ -#define MCF_CLOCK_SYNCR_PLLEN (0x0001) -#define MCF_CLOCK_SYNCR_PLLMODE (0x0002) -#define MCF_CLOCK_SYNCR_CLKSRC (0x0004) -#define MCF_CLOCK_SYNCR_FWKUP (0x0020) -#define MCF_CLOCK_SYNCR_DISCLK (0x0040) -#define MCF_CLOCK_SYNCR_LOCEN (0x0080) -#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8) -#define MCF_CLOCK_SYNCR_LOCRE (0x0800) -#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12) -#define MCF_CLOCK_SYNCR_LOLRE (0x8000) - -/* Bit definitions and macros for MCF_CLOCK_SYNSR */ -#define MCF_CLOCK_SYNSR_LOCS (0x04) -#define MCF_CLOCK_SYNSR_LOCK (0x08) -#define MCF_CLOCK_SYNSR_LOCKS (0x10) -#define MCF_CLOCK_SYNSR_CRYOSC (0x20) -#define MCF_CLOCK_SYNSR_OCOSC (0x40) -#define MCF_CLOCK_SYNSR_EXTOSC (0x80) - -/* Bit definitions and macros for MCF_CLOCK_LPCR */ -#define MCF_CLOCK_LPCR_LPD(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_CLOCK_CCHR */ -#define MCF_CLOCK_CCHR_PFD(x) (((x)&0x07)<<0) - -/* Bit definitions and macros for MCF_CLOCK_CCHR */ -#define MCF_CLOCK_CCLR_PRIM_OSC (0x00) -#define MCF_CLOCK_CCLR_REL_OSC (0x01) -#define MCF_CLOCK_CCLR_SEC_OSC (0x02) -#define MCF_CLOCK_CCLR_SEC1_OSC (0x03) - -/* Bit definitions and macros for MCF_CLOCK_RTCDR */ -#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CLOCK_RTCCR */ -#define MCF_CLOCK_RTCCR_RTCSEL 0x01U -#define MCF_CLOCK_RTCCR_LPEN 0x02U -#define MCF_CLOCK_RTCCR_REFS 0x04U -#define MCF_CLOCK_RTCCR_KHZEN 0x08U -#define MCF_CLOCK_RTCCR_OSCEN 0x10U -#define MCF_CLOCK_RTCCR_EXTALEN 0x40U - -/********************************************************************* -* -* Edge Port Module (EPORT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR0 (*(vuint16*)(&__IPSBAR[0x130000])) -#define MCF_EPORT_EPDDR0 (*(vuint8 *)(&__IPSBAR[0x130002])) -#define MCF_EPORT_EPIER0 (*(vuint8 *)(&__IPSBAR[0x130003])) -#define MCF_EPORT_EPDR0 (*(vuint8 *)(&__IPSBAR[0x130004])) -#define MCF_EPORT_EPPDR0 (*(vuint8 *)(&__IPSBAR[0x130005])) -#define MCF_EPORT_EPFR0 (*(vuint8 *)(&__IPSBAR[0x130006])) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x0003)<<0) -#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_LEVEL (0) -#define MCF_EPORT_EPPAR_RISING (1) -#define MCF_EPORT_EPPAR_FALLING (2) -#define MCF_EPORT_EPPAR_BOTH (3) -#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000) -#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000) -#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000) -#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000) -#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000) -#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000) -#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA13_RISING (0x0400) -#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x0800) -#define MCF_EPORT_EPPAR_EPPA13_BOTH (0x0C00) -#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA12_RISING (0x0100) -#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x0200) -#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x0300) -#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA11_RISING (0x0040) -#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x0080) -#define MCF_EPORT_EPPAR_EPPA11_BOTH (0x00C0) -#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA10_RISING (0x0010) -#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x0020) -#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x0030) -#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA9_RISING (0x0004) -#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x0008) -#define MCF_EPORT_EPPAR_EPPA9_BOTH (0x000C) -#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA8_RISING (0x0001) -#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x0002) -#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x0003) -#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) -#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) -#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) -#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) -#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) -#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) -#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) -#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) -#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) -#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) -#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) -#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) -#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) -#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) -#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) -#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) -#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) -#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) -#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) -#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) -#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) -#define MCF_EPORT_EPDDR_EPDD8 (0x01) -#define MCF_EPORT_EPDDR_EPDD9 (0x02) -#define MCF_EPORT_EPDDR_EPDD10 (0x04) -#define MCF_EPORT_EPDDR_EPDD11 (0x08) -#define MCF_EPORT_EPDDR_EPDD12 (0x10) -#define MCF_EPORT_EPDDR_EPDD13 (0x20) -#define MCF_EPORT_EPDDR_EPDD14 (0x40) -#define MCF_EPORT_EPDDR_EPDD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) -#define MCF_EPORT_EPIER_EPIE8 (0x01) -#define MCF_EPORT_EPIER_EPIE9 (0x02) -#define MCF_EPORT_EPIER_EPIE10 (0x04) -#define MCF_EPORT_EPIER_EPIE11 (0x08) -#define MCF_EPORT_EPIER_EPIE12 (0x10) -#define MCF_EPORT_EPIER_EPIE13 (0x20) -#define MCF_EPORT_EPIER_EPIE14 (0x40) -#define MCF_EPORT_EPIER_EPIE15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) -#define MCF_EPORT_EPDR_EPD8 (0x01) -#define MCF_EPORT_EPDR_EPD9 (0x02) -#define MCF_EPORT_EPDR_EPD10 (0x04) -#define MCF_EPORT_EPDR_EPD11 (0x08) -#define MCF_EPORT_EPDR_EPD12 (0x10) -#define MCF_EPORT_EPDR_EPD13 (0x20) -#define MCF_EPORT_EPDR_EPD14 (0x40) -#define MCF_EPORT_EPDR_EPD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) -#define MCF_EPORT_EPPDR_EPPD8 (0x01) -#define MCF_EPORT_EPPDR_EPPD9 (0x02) -#define MCF_EPORT_EPPDR_EPPD10 (0x04) -#define MCF_EPORT_EPPDR_EPPD11 (0x08) -#define MCF_EPORT_EPPDR_EPPD12 (0x10) -#define MCF_EPORT_EPPDR_EPPD13 (0x20) -#define MCF_EPORT_EPPDR_EPPD14 (0x40) -#define MCF_EPORT_EPPDR_EPPD15 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) -#define MCF_EPORT_EPFR_EPF8 (0x01) -#define MCF_EPORT_EPFR_EPF9 (0x02) -#define MCF_EPORT_EPFR_EPF10 (0x04) -#define MCF_EPORT_EPFR_EPF11 (0x08) -#define MCF_EPORT_EPFR_EPF12 (0x10) -#define MCF_EPORT_EPFR_EPF13 (0x20) -#define MCF_EPORT_EPFR_EPF14 (0x40) -#define MCF_EPORT_EPFR_EPF15 (0x80) - - -/********************************************************************* -* -* Backup Watchdog Timer Module (BWT) -* -*********************************************************************/ - -#define MCF_BWT_WCR (*(vuint16*)(&__IPSBAR[0x140000])) -#define MCF_BWT_WMR (*(vuint16*)(&__IPSBAR[0x140002])) -#define MCF_BWT_WCNTR (*(vuint16*)(&__IPSBAR[0x140004])) -#define MCF_BWT_WSR (*(vuint16*)(&__IPSBAR[0x140006])) - -/* Bit definitions and macros for MCF_BWT_WCR */ -#define MCF_BWT_WCR_EN 0x01 -#define MCF_BWT_WCR_DOZE 0x04 -#define MCF_BWT_WCR_WAIT 0x08 -#define MCF_BWT_WCR_STOP 0x10 - -#define MCF_BWT_WSR_SEQ1 0x5555 -#define MCF_BWT_WSR_SEQ2 0xAAAA - -//MPR: TODO this Modules is new in mcf52258 vs. mcf52235 and some macros must be written first - -/********************************************************************* -* -* Programmable Interrupt Timer Modules (PIT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000])) -#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002])) -#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004])) -#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000])) -#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002])) -#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004])) -#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000+((x)*0x10000)])) -#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002+((x)*0x10000)])) -#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004+((x)*0x10000)])) - -/* Bit definitions and macros for MCF_PIT_PCSR */ -#define MCF_PIT_PCSR_EN (0x0001) -#define MCF_PIT_PCSR_RLD (0x0002) -#define MCF_PIT_PCSR_PIF (0x0004) -#define MCF_PIT_PCSR_PIE (0x0008) -#define MCF_PIT_PCSR_OVW (0x0010) -#define MCF_PIT_PCSR_HALTED (0x0020) -#define MCF_PIT_PCSR_DOZE (0x0040) -#define MCF_PIT_PCSR_PRE(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_PIT_PMR */ -#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_PIT_PCNTR */ -#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0) - -/********************************************************************* -* -* Analog-to-Digital Converter (ADC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000])) -#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002])) -#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004])) -#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006])) -#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008])) -#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A])) -#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C])) -#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E])) -#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010])) -#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012])) -#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014])) -#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016])) -#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018])) -#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A])) -#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C])) -#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E])) -#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020])) -#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012+((x)*0x002)])) -#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022])) -#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024])) -#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026])) -#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028])) -#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A])) -#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C])) -#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E])) -#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030])) -#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022+((x)*0x002)])) -#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032])) -#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034])) -#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036])) -#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038])) -#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A])) -#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C])) -#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E])) -#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040])) -#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032+((x)*0x002)])) -#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042])) -#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044])) -#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046])) -#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048])) -#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A])) -#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C])) -#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E])) -#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050])) -#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042+((x)*0x002)])) -#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052])) -#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054])) - -/* Bit definitions and macros for MCF_ADC_CTRL1 */ -#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x0007)<<0) -#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0x000F)<<4) -#define MCF_ADC_CTRL1_HLMTIE (0x0100) -#define MCF_ADC_CTRL1_LLMTIE (0x0200) -#define MCF_ADC_CTRL1_ZCIE (0x0400) -#define MCF_ADC_CTRL1_EOSIE0 (0x0800) -#define MCF_ADC_CTRL1_SYNC0 (0x1000) -#define MCF_ADC_CTRL1_START0 (0x2000) -#define MCF_ADC_CTRL1_STOP0 (0x4000) - -/* Bit definitions and macros for MCF_ADC_CTRL2 */ -#define MCF_ADC_CTRL2_DIV(x) (((x)&0x001F)<<0) -#define MCF_ADC_CTRL2_SIMULT (0x0020) -#define MCF_ADC_CTRL2_EOSIE1 (0x0800) -#define MCF_ADC_CTRL2_SYNC1 (0x1000) -#define MCF_ADC_CTRL2_START1 (0x2000) -#define MCF_ADC_CTRL2_STOP1 (0x4000) - -/* Bit definitions and macros for MCF_ADC_ADZCC */ -#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x0003)<<0) -#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x0003)<<2) -#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x0003)<<4) -#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x0003)<<6) -#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x0003)<<8) -#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x0003)<<10) -#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x0003)<<12) -#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_ADC_ADLST1 */ -#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x0007)<<0) -#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x0007)<<4) -#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x0007)<<8) -#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x0007)<<12) - -/* Bit definitions and macros for MCF_ADC_ADLST2 */ -#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x0007)<<0) -#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x0007)<<4) -#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x0007)<<8) -#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x0007)<<12) - -/* Bit definitions and macros for MCF_ADC_ADSDIS */ -#define MCF_ADC_ADSDIS_DS0 (0x0001) -#define MCF_ADC_ADSDIS_DS1 (0x0002) -#define MCF_ADC_ADSDIS_DS2 (0x0004) -#define MCF_ADC_ADSDIS_DS3 (0x0008) -#define MCF_ADC_ADSDIS_DS4 (0x0010) -#define MCF_ADC_ADSDIS_DS5 (0x0020) -#define MCF_ADC_ADSDIS_DS6 (0x0040) -#define MCF_ADC_ADSDIS_DS7 (0x0080) - -/* Bit definitions and macros for MCF_ADC_ADSTAT */ -#define MCF_ADC_ADSTAT_RDY0 (0x0001) -#define MCF_ADC_ADSTAT_RDY1 (0x0002) -#define MCF_ADC_ADSTAT_RDY2 (0x0004) -#define MCF_ADC_ADSTAT_RDY3 (0x0008) -#define MCF_ADC_ADSTAT_RDY4 (0x0010) -#define MCF_ADC_ADSTAT_RDY5 (0x0020) -#define MCF_ADC_ADSTAT_RDY6 (0x0040) -#define MCF_ADC_ADSTAT_RDY7 (0x0080) -#define MCF_ADC_ADSTAT_HLMT (0x0100) -#define MCF_ADC_ADSTAT_LLMTI (0x0200) -#define MCF_ADC_ADSTAT_ZCI (0x0400) -#define MCF_ADC_ADSTAT_EOSI (0x0800) -#define MCF_ADC_ADSTAT_CIP (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADLSTAT */ -#define MCF_ADC_ADLSTAT_LLS0 (0x0001) -#define MCF_ADC_ADLSTAT_LLS1 (0x0002) -#define MCF_ADC_ADLSTAT_LLS2 (0x0004) -#define MCF_ADC_ADLSTAT_LLS3 (0x0008) -#define MCF_ADC_ADLSTAT_LLS4 (0x0010) -#define MCF_ADC_ADLSTAT_LLS5 (0x0020) -#define MCF_ADC_ADLSTAT_LLS6 (0x0040) -#define MCF_ADC_ADLSTAT_LLS7 (0x0080) -#define MCF_ADC_ADLSTAT_HLS0 (0x0100) -#define MCF_ADC_ADLSTAT_HLS1 (0x0200) -#define MCF_ADC_ADLSTAT_HLS2 (0x0400) -#define MCF_ADC_ADLSTAT_HLS3 (0x0800) -#define MCF_ADC_ADLSTAT_HLS4 (0x1000) -#define MCF_ADC_ADLSTAT_HLS5 (0x2000) -#define MCF_ADC_ADLSTAT_HLS6 (0x4000) -#define MCF_ADC_ADLSTAT_HLS7 (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADZCSTAT */ -#define MCF_ADC_ADZCSTAT_ZCS0 (0x0001) -#define MCF_ADC_ADZCSTAT_ZCS1 (0x0002) -#define MCF_ADC_ADZCSTAT_ZCS2 (0x0004) -#define MCF_ADC_ADZCSTAT_ZCS3 (0x0008) -#define MCF_ADC_ADZCSTAT_ZCS4 (0x0010) -#define MCF_ADC_ADZCSTAT_ZCS5 (0x0020) -#define MCF_ADC_ADZCSTAT_ZCS6 (0x0040) -#define MCF_ADC_ADZCSTAT_ZCS7 (0x0080) - -/* Bit definitions and macros for MCF_ADC_ADRSLT */ -#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0x0FFF)<<3) -#define MCF_ADC_ADRSLT_SEXT (0x8000) - -/* Bit definitions and macros for MCF_ADC_ADLLMT */ -#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_ADHLMT */ -#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_ADOFS */ -#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0x0FFF)<<3) - -/* Bit definitions and macros for MCF_ADC_POWER */ -#define MCF_ADC_POWER_PD0 (0x0001) -#define MCF_ADC_POWER_PD1 (0x0002) -#define MCF_ADC_POWER_PD2 (0x0004) -#define MCF_ADC_POWER_APD (0x0008) -#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x003F)<<4) -#define MCF_ADC_POWER_PSTS0 (0x0400) -#define MCF_ADC_POWER_PSTS1 (0x0800) -#define MCF_ADC_POWER_PSTS2 (0x1000) -#define MCF_ADC_POWER_ASTBY (0x8000) - -/* Bit definitions and macros for MCF_ADC_CAL */ -#define MCF_ADC_CAL_CAL0 (0x0001) -#define MCF_ADC_CAL_CRS0 (0x0002) -#define MCF_ADC_CAL_CAL1 (0x0004) -#define MCF_ADC_CAL_CRS1 (0x0008) - -/********************************************************************* -* -* General Purpose Timer (GPT) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPT_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000])) -#define MCF_GPT_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001])) -#define MCF_GPT_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002])) -#define MCF_GPT_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003])) -#define MCF_GPT_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004])) -#define MCF_GPT_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006])) -#define MCF_GPT_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008])) -#define MCF_GPT_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009])) -#define MCF_GPT_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B])) -#define MCF_GPT_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C])) -#define MCF_GPT_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D])) -#define MCF_GPT_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E])) -#define MCF_GPT_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F])) -#define MCF_GPT_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010])) -#define MCF_GPT_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012])) -#define MCF_GPT_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014])) -#define MCF_GPT_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016])) -#define MCF_GPT_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010+((x)*0x002)])) -#define MCF_GPT_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018])) -#define MCF_GPT_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019])) -#define MCF_GPT_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A])) -#define MCF_GPT_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D])) -#define MCF_GPT_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E])) - -/* Bit definitions and macros for MCF_GPT_GPTIOS */ -#define MCF_GPT_GPTIOS_IOS0 (0x01) -#define MCF_GPT_GPTIOS_IOS1 (0x02) -#define MCF_GPT_GPTIOS_IOS2 (0x04) -#define MCF_GPT_GPTIOS_IOS3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTCFORC */ -#define MCF_GPT_GPTCFORC_FOC0 (0x01) -#define MCF_GPT_GPTCFORC_FOC1 (0x02) -#define MCF_GPT_GPTCFORC_FOC2 (0x04) -#define MCF_GPT_GPTCFORC_FOC3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTOC3D */ -#define MCF_GPT_GPTOC3D_OC3D0 (0x01) -#define MCF_GPT_GPTOC3D_OC3D1 (0x02) -#define MCF_GPT_GPTOC3D_OC3D2 (0x04) -#define MCF_GPT_GPTOC3D_OC3D3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTSCR1 */ -#define MCF_GPT_GPTSCR1_TFFCA (0x10) -#define MCF_GPT_GPTSCR1_GPTEN (0x80) - -/* Bit definitions and macros for MCF_GPT_GPTTOV */ -#define MCF_GPT_GPTTOV_TOV0 (0x01) -#define MCF_GPT_GPTTOV_TOV1 (0x02) -#define MCF_GPT_GPTTOV_TOV2 (0x04) -#define MCF_GPT_GPTTOV_TOV3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTCTL1 */ -#define MCF_GPT_GPTCTL1_OL0 (0x01) -#define MCF_GPT_GPTCTL1_OM0 (0x02) -#define MCF_GPT_GPTCTL1_OL1 (0x04) -#define MCF_GPT_GPTCTL1_OM1 (0x08) -#define MCF_GPT_GPTCTL1_OL2 (0x10) -#define MCF_GPT_GPTCTL1_OM2 (0x20) -#define MCF_GPT_GPTCTL1_OL3 (0x40) -#define MCF_GPT_GPTCTL1_OM3 (0x80) -#define MCF_GPT_GPTCTL1_OUTPUT3_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT3_TOGGLE ((0x40)) -#define MCF_GPT_GPTCTL1_OUTPUT3_CLEAR ((0x80)) -#define MCF_GPT_GPTCTL1_OUTPUT3_SET ((0xC0)) -#define MCF_GPT_GPTCTL1_OUTPUT2_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT2_TOGGLE ((0x10)) -#define MCF_GPT_GPTCTL1_OUTPUT2_CLEAR ((0x20)) -#define MCF_GPT_GPTCTL1_OUTPUT2_SET ((0x30)) -#define MCF_GPT_GPTCTL1_OUTPUT1_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT1_TOGGLE ((0x04)) -#define MCF_GPT_GPTCTL1_OUTPUT1_CLEAR ((0x08)) -#define MCF_GPT_GPTCTL1_OUTPUT1_SET ((0x0C)) -#define MCF_GPT_GPTCTL1_OUTPUT0_NOTHING ((0x00)) -#define MCF_GPT_GPTCTL1_OUTPUT0_TOGGLE ((0x01)) -#define MCF_GPT_GPTCTL1_OUTPUT0_CLEAR ((0x02)) -#define MCF_GPT_GPTCTL1_OUTPUT0_SET ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTCTL2 */ -#define MCF_GPT_GPTCTL2_EDG0A (0x01) -#define MCF_GPT_GPTCTL2_EDG0B (0x02) -#define MCF_GPT_GPTCTL2_EDG1A (0x04) -#define MCF_GPT_GPTCTL2_EDG1B (0x08) -#define MCF_GPT_GPTCTL2_EDG2A (0x10) -#define MCF_GPT_GPTCTL2_EDG2B (0x20) -#define MCF_GPT_GPTCTL2_EDG3A (0x40) -#define MCF_GPT_GPTCTL2_EDG3B (0x80) -#define MCF_GPT_GPTCTL2_INPUT3_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT3_RISING ((0x40)) -#define MCF_GPT_GPTCTL2_INPUT3_FALLING ((0x80)) -#define MCF_GPT_GPTCTL2_INPUT3_ANY ((0xC0)) -#define MCF_GPT_GPTCTL2_INPUT2_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT2_RISING ((0x10)) -#define MCF_GPT_GPTCTL2_INPUT2_FALLING ((0x20)) -#define MCF_GPT_GPTCTL2_INPUT2_ANY ((0x30)) -#define MCF_GPT_GPTCTL2_INPUT1_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT1_RISING ((0x04)) -#define MCF_GPT_GPTCTL2_INPUT1_FALLING ((0x08)) -#define MCF_GPT_GPTCTL2_INPUT1_ANY ((0x0C)) -#define MCF_GPT_GPTCTL2_INPUT0_DISABLED ((0x00)) -#define MCF_GPT_GPTCTL2_INPUT0_RISING ((0x01)) -#define MCF_GPT_GPTCTL2_INPUT0_FALLING ((0x02)) -#define MCF_GPT_GPTCTL2_INPUT0_ANY ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTIE */ -#define MCF_GPT_GPTIE_CI0 (0x01) -#define MCF_GPT_GPTIE_CI1 (0x02) -#define MCF_GPT_GPTIE_CI2 (0x04) -#define MCF_GPT_GPTIE_CI3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTSCR2 */ -#define MCF_GPT_GPTSCR2_PR(x) (((x)&0x07)<<0) -#define MCF_GPT_GPTSCR2_TCRE (0x08) -#define MCF_GPT_GPTSCR2_RDPT (0x10) -#define MCF_GPT_GPTSCR2_PUPT (0x20) -#define MCF_GPT_GPTSCR2_TOI (0x80) -#define MCF_GPT_GPTSCR2_PR_1 ((0x00)) -#define MCF_GPT_GPTSCR2_PR_2 ((0x01)) -#define MCF_GPT_GPTSCR2_PR_4 ((0x02)) -#define MCF_GPT_GPTSCR2_PR_8 ((0x03)) -#define MCF_GPT_GPTSCR2_PR_16 ((0x04)) -#define MCF_GPT_GPTSCR2_PR_32 ((0x05)) -#define MCF_GPT_GPTSCR2_PR_64 ((0x06)) -#define MCF_GPT_GPTSCR2_PR_128 ((0x07)) - -/* Bit definitions and macros for MCF_GPT_GPTFLG1 */ -#define MCF_GPT_GPTFLG1_CF0 (0x01) -#define MCF_GPT_GPTFLG1_CF1 (0x02) -#define MCF_GPT_GPTFLG1_CF2 (0x04) -#define MCF_GPT_GPTFLG1_CF3 (0x08) - -/* Bit definitions and macros for MCF_GPT_GPTFLG2 */ -#define MCF_GPT_GPTFLG2_CF0 (0x01) -#define MCF_GPT_GPTFLG2_CF1 (0x02) -#define MCF_GPT_GPTFLG2_CF2 (0x04) -#define MCF_GPT_GPTFLG2_CF3 (0x08) -#define MCF_GPT_GPTFLG2_TOF (0x80) - -/* Bit definitions and macros for MCF_GPT_GPTC */ -#define MCF_GPT_GPTC_CCNT(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTPACTL */ -#define MCF_GPT_GPTPACTL_PAI (0x01) -#define MCF_GPT_GPTPACTL_PAOVI (0x02) -#define MCF_GPT_GPTPACTL_CLK(x) (((x)&0x03)<<2) -#define MCF_GPT_GPTPACTL_PEDGE (0x10) -#define MCF_GPT_GPTPACTL_PAMOD (0x20) -#define MCF_GPT_GPTPACTL_PAE (0x40) -#define MCF_GPT_GPTPACTL_CLK_GPTPR ((0x00)) -#define MCF_GPT_GPTPACTL_CLK_PACLK ((0x01)) -#define MCF_GPT_GPTPACTL_CLK_PACLK_256 ((0x02)) -#define MCF_GPT_GPTPACTL_CLK_PACLK_65536 ((0x03)) - -/* Bit definitions and macros for MCF_GPT_GPTPAFLG */ -#define MCF_GPT_GPTPAFLG_PAIF (0x01) -#define MCF_GPT_GPTPAFLG_PAOVF (0x02) - -/* Bit definitions and macros for MCF_GPT_GPTPACNT */ -#define MCF_GPT_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTPORT */ -#define MCF_GPT_GPTPORT_PORTT(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_GPT_GPTDDR */ -#define MCF_GPT_GPTDDR_DDRT0 (0x01) -#define MCF_GPT_GPTDDR_DDRT1 (0x02) -#define MCF_GPT_GPTDDR_DDRT2 (0x04) -#define MCF_GPT_GPTDDR_DDRT3 (0x08) - -/********************************************************************* -* -* Pulse Width Modulation (PWM) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000])) -#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001])) -#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002])) -#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003])) -#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004])) -#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005])) -#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008])) -#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009])) -#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C])) -#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D])) -#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E])) -#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F])) -#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010])) -#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011])) -#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012])) -#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013])) -#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C+((x)*0x001)])) -#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014])) -#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015])) -#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016])) -#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017])) -#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018])) -#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019])) -#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A])) -#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B])) -#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014+((x)*0x001)])) -#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C])) -#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D])) -#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E])) -#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F])) -#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020])) -#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021])) -#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022])) -#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023])) -#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C+((x)*0x001)])) -#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024])) - -/* Bit definitions and macros for MCF_PWM_PWME */ -#define MCF_PWM_PWME_PWME0 (0x01) -#define MCF_PWM_PWME_PWME1 (0x02) -#define MCF_PWM_PWME_PWME2 (0x04) -#define MCF_PWM_PWME_PWME3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMPOL */ -#define MCF_PWM_PWMPOL_PPOL0 (0x01) -#define MCF_PWM_PWMPOL_PPOL1 (0x02) -#define MCF_PWM_PWMPOL_PPOL2 (0x04) -#define MCF_PWM_PWMPOL_PPOL3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMCLK */ -#define MCF_PWM_PWMCLK_PCLK0 (0x01) -#define MCF_PWM_PWMCLK_PCLK1 (0x02) -#define MCF_PWM_PWMCLK_PCLK2 (0x04) -#define MCF_PWM_PWMCLK_PCLK3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMPRCLK */ -#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x07)<<0) -#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x07)<<4) - -/* Bit definitions and macros for MCF_PWM_PWMCAE */ -#define MCF_PWM_PWMCAE_CAE0 (0x01) -#define MCF_PWM_PWMCAE_CAE1 (0x02) -#define MCF_PWM_PWMCAE_CAE2 (0x04) -#define MCF_PWM_PWMCAE_CAE3 (0x08) - -/* Bit definitions and macros for MCF_PWM_PWMCTL */ -#define MCF_PWM_PWMCTL_PFRZ (0x04) -#define MCF_PWM_PWMCTL_PSWAI (0x08) -#define MCF_PWM_PWMCTL_CON01 (0x10) -#define MCF_PWM_PWMCTL_CON23 (0x20) - -/* Bit definitions and macros for MCF_PWM_PWMSCLA */ -#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMSCLB */ -#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMCNT */ -#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMPER */ -#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMDTY */ -#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PWM_PWMSDN */ -#define MCF_PWM_PWMSDN_SDNEN (0x01) -#define MCF_PWM_PWMSDN_PWM7IL (0x02) -#define MCF_PWM_PWMSDN_PWM7IN (0x04) -#define MCF_PWM_PWMSDN_LVL (0x10) -#define MCF_PWM_PWMSDN_RESTART (0x20) -#define MCF_PWM_PWMSDN_IE (0x40) -#define MCF_PWM_PWMSDN_IF (0x80) - -/********************************************************************* -* -* FlexCAN Module (CAN) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_CAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000])) -#define MCF_CAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004])) -#define MCF_CAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008])) -#define MCF_CAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010])) -#define MCF_CAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014])) -#define MCF_CAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018])) -#define MCF_CAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C])) -#define MCF_CAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020])) -#define MCF_CAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028])) -#define MCF_CAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030])) - -/* Bit definitions and macros for MCF_CAN_CANMCR */ -#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) -#define MCF_CAN_CANMCR_SUPV (0x00800000) -#define MCF_CAN_CANMCR_FRZACK (0x01000000) -#define MCF_CAN_CANMCR_SOFTRST (0x02000000) -#define MCF_CAN_CANMCR_HALT (0x10000000) -#define MCF_CAN_CANMCR_FRZ (0x40000000) -#define MCF_CAN_CANMCR_MDIS (0x80000000) - -/* Bit definitions and macros for MCF_CAN_CANCTRL */ -#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) -#define MCF_CAN_CANCTRL_LOM (0x00000008) -#define MCF_CAN_CANCTRL_LBUF (0x00000010) -#define MCF_CAN_CANCTRL_TSYNC (0x00000020) -#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) -#define MCF_CAN_CANCTRL_SAMP (0x00000080) -#define MCF_CAN_CANCTRL_LPB (0x00001000) -#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) -#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) -#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) -#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) -#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) -#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) -#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_CAN_TIMER */ -#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RXGMASK */ -#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX14MASK */ -#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_RX15MASK */ -#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) - -/* Bit definitions and macros for MCF_CAN_ERRCNT */ -#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) -#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) - -/* Bit definitions and macros for MCF_CAN_ERRSTAT */ -#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) -#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) -#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) -#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) -#define MCF_CAN_ERRSTAT_TXRX (0x00000040) -#define MCF_CAN_ERRSTAT_IDLE (0x00000080) -#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) -#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) -#define MCF_CAN_ERRSTAT_STFERR (0x00000400) -#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) -#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) -#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) -#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) -#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) -#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) -#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) - -/* Bit definitions and macros for MCF_CAN_IMASK */ -#define MCF_CAN_IMASK_BUF(x) (1< -rtems_timer_create 0 -rtems_timer_delete 0 -rtems_timer_ident 0 -rtems_timer_fire_after 0 -rtems_timer_fire_when 1 -rtems_timer_reset 0 -rtems_timer_cancel 0 -rtems_semaphore_create 0 -rtems_semaphore_delete 0 -rtems_semaphore_ident 0 -rtems_semaphore_obtain 0 -rtems_semaphore_release 0 -rtems_message_queue_create 0 -rtems_message_queue_ident 0 -rtems_message_queue_delete 0 -rtems_message_queue_send 0 -rtems_message_queue_urgent 0 -rtems_message_queue_broadcast 0 -rtems_message_queue_receive 0 -rtems_message_queue_flush 0 - -rtems_event_send 0 -rtems_event_receive 0 -rtems_signal_catch 0 -rtems_signal_send 0 -rtems_partition_create 0 -rtems_partition_ident 0 -rtems_partition_delete 0 -rtems_partition_get_buffer 0 -rtems_partition_return_buffer 0 -rtems_region_create 0 -rtems_region_ident 0 -rtems_region_delete 0 -rtems_region_get_segment 0 -rtems_region_return_segment 0 -rtems_port_create 0 -rtems_port_ident 0 -rtems_port_delete 0 -rtems_port_external_to_internal 0 -rtems_port_internal_to_external 0 - -rtems_io_initialize 0 -rtems_io_open 0 -rtems_io_close 0 -rtems_io_read 0 -rtems_io_write 0 -rtems_io_control 0 -rtems_fatal_error_occurred 0 -rtems_rate_monotonic_create 0 -rtems_rate_monotonic_ident 0 -rtems_rate_monotonic_delete 0 -rtems_rate_monotonic_cancel 0 -rtems_rate_monotonic_period 0 -rtems_multiprocessing_announce 0 -*** END OF TIME OVERHEAD *** -``` diff --git a/bsps/m68k/mcf5225x/btimer/btimer.c b/bsps/m68k/mcf5225x/btimer/btimer.c deleted file mode 100644 index 9f7c24482d..0000000000 --- a/bsps/m68k/mcf5225x/btimer/btimer.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Timer Init - * - * Use the last DMA timer (DTIM3) as the diagnostic timer. - */ - -/* - * Copyright (c) 2005 Eric Norum - * - * COPYRIGHT (c) 2005-2010. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include - -void benchmark_timer_initialize(void) -{ - uint32_t preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000; - - MCF_DTIM3_DTMR = 0; - MCF_DTIM3_DTMR = MCF_DTIM_DTMR_PS(preScaleDivisor - 1) | - MCF_DTIM_DTMR_CLK_DIV1 | MCF_DTIM_DTMR_RST; -} - -/* - * Return timer value in microsecond units - */ -benchmark_timer_t benchmark_timer_read(void) -{ - return MCF_DTIM3_DTCN; -} - -void benchmark_timer_disable_subtracting_average_overhead(bool find_flag) -{ -} diff --git a/bsps/m68k/mcf5225x/clock/clock.c b/bsps/m68k/mcf5225x/clock/clock.c deleted file mode 100644 index 3cd76aa17a..0000000000 --- a/bsps/m68k/mcf5225x/clock/clock.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Use the last periodic interval timer (PIT2) as the system clock. - */ - -#include -#include -#include - -/* - * Use INTC0 base - */ -#define CLOCK_VECTOR (64+56) - -static rtems_timecounter_simple mcf5225x_tc; - -static uint32_t mcf5225x_tc_get(rtems_timecounter_simple *tc) -{ - return MCF_PIT1_PCNTR; -} - -static bool mcf5225x_tc_is_pending(rtems_timecounter_simple *tc) -{ - return (MCF_PIT1_PCSR & MCF_PIT_PCSR_PIF) != 0; -} - -static uint32_t mcf5225x_tc_get_timecount(struct timecounter *tc) -{ - return rtems_timecounter_simple_downcounter_get( - tc, - mcf5225x_tc_get, - mcf5225x_tc_is_pending - ); -} - -static void mcf5225x_tc_at_tick(rtems_timecounter_simple *tc) -{ - MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF; -} - -static void mcf5225x_tc_tick(void) -{ - rtems_timecounter_simple_downcounter_tick( - &mcf5225x_tc, - mcf5225x_tc_get, - mcf5225x_tc_at_tick - ); -} - -/* - * Attach clock interrupt handler - */ -#define Clock_driver_support_install_isr( _new ) \ - set_vector(_new, CLOCK_VECTOR, 1) - -/* - * Set up the clock hardware - * - * We need to have 1 interrupt every BSP_rtems_configuration_get_microseconds_per_tick() - */ -static void Clock_driver_support_initialize_hardware(void) -{ - int level; - uint32_t pmr; - uint32_t preScaleCode = 0; - uint32_t clk = bsp_get_CPU_clock_speed() >> 1; - uint32_t tps = 1000000 / rtems_configuration_get_microseconds_per_tick(); - - while (preScaleCode < 15) { - pmr = (clk >> preScaleCode) / tps; - if (pmr < (1 << 15)) - break; - preScaleCode++; - } - - MCF_INTC0_ICR56 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL) | - MCF_INTC_ICR_IP(PIT3_IRQ_PRIORITY); - rtems_interrupt_disable(level); - MCF_INTC0_IMRH &= ~MCF_INTC_IMRH_MASK56; - MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN; - rtems_interrupt_enable(level); - - MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | - MCF_PIT_PCSR_OVW | MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD; - MCF_PIT1_PMR = pmr; - MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | - MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_EN; - - rtems_timecounter_simple_install( - &mcf5225x_tc, - clk >> preScaleCode, - pmr, - mcf5225x_tc_get_timecount - ); -} - -#define Clock_driver_timecounter_tick(arg) mcf5225x_tc_tick() - -#include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/m68k/mcf5225x/config/mcf5225x-testsuite.tcfg b/bsps/m68k/mcf5225x/config/mcf5225x-testsuite.tcfg deleted file mode 100644 index 420ff1376c..0000000000 --- a/bsps/m68k/mcf5225x/config/mcf5225x-testsuite.tcfg +++ /dev/null @@ -1,17 +0,0 @@ -# -# mcf5225x RTEMS Test Database. -# -# Format is one line per test that is _NOT_ built. -# - -include: testdata/disable-iconv-tests.tcfg -include: testdata/disable-jffs2-tests.tcfg -include: testdata/small-memory-testsuite.tcfg - -exclude: cdtest -exclude: dl05 -exclude: fileio -exclude: flashdisk01 -exclude: fsdosfsname01 -exclude: iostream -exclude: linpack diff --git a/bsps/m68k/mcf5225x/config/mcf5225x.cfg b/bsps/m68k/mcf5225x/config/mcf5225x.cfg deleted file mode 100644 index 7d2fe0b2a5..0000000000 --- a/bsps/m68k/mcf5225x/config/mcf5225x.cfg +++ /dev/null @@ -1,29 +0,0 @@ -# -# Config file for the mcf5225x BSP -# - -RTEMS_CPU=m68k - -include $(RTEMS_ROOT)/make/custom/default.cfg - -# This is the actual bsp directory used during the build process. -RTEMS_BSP_FAMILY=mcf5225x - -# This contains the compiler options necessary to select the CPU model -# and (hopefully) optimize for it. -CPU_CFLAGS = -mcpu=52235 $(PROJECT_FLAGS) - -# optimize flag: typically -O2 -CFLAGS_OPTIMIZE_V = -O2 -fomit-frame-pointer - -# The following two lines enable compiling and linking on per element. -CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections -LDFLAGS = -Wl,--gc-sections - -# This defines the operations performed on the linked executable. -# is currently required. -define bsp-post-link - $(OBJCOPY) -O binary --strip-all \ - $(basename $@)$(EXEEXT) $(basename $@)$(DOWNEXT) - $(SIZE) $(basename $@)$(EXEEXT) -endef diff --git a/bsps/m68k/mcf5225x/console/console.c b/bsps/m68k/mcf5225x/console/console.c deleted file mode 100644 index 9e36e3945a..0000000000 --- a/bsps/m68k/mcf5225x/console/console.c +++ /dev/null @@ -1,689 +0,0 @@ -/* - * Multi UART console serial I/O. - * - * TO DO: Add DMA input/output - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define UART_INTC0_IRQ_VECTOR(x) (64+13+(x)) - -#define MCF_UART_USR_ERROR ( MCF_UART_USR_RB | \ - MCF_UART_USR_FE | \ - MCF_UART_USR_PE | \ - MCF_UART_USR_OE ) - -static ssize_t IntUartPollWrite(int minor, const char *buf, size_t len); -static ssize_t IntUartInterruptWrite(int minor, const char *buf, size_t len); - -#define MAX_UART_INFO 3 -#define RX_BUFFER_SIZE 512 - -struct IntUartInfoStruct -{ - int iomode; - volatile int uimr; - int baud; - int databits; - int parity; - int stopbits; - int hwflow; - int rx_in; - int rx_out; - char rx_buffer[RX_BUFFER_SIZE]; - void *ttyp; -}; - -struct IntUartInfoStruct IntUartInfo[MAX_UART_INFO]; - -/*************************************************************************** - Function : IntUartSet - - Description : This updates the hardware UART settings. - ***************************************************************************/ -static void -IntUartSet(int minor, int baud, int databits, int parity, int stopbits, - int hwflow) -{ - int divisor; - uint32_t clock_speed; - uint8_t umr1 = 0; - uint8_t umr2 = 0; - struct IntUartInfoStruct *info = &IntUartInfo[minor]; - rtems_interrupt_level level=UART0_IRQ_LEVEL; - - rtems_interrupt_disable(level); - - /* disable interrupts, clear RTS line, and disable the UARTS */ - MCF_UART_UIMR(minor) = 0; - MCF_UART_UOP0(minor) = 1; - MCF_UART_UCR(minor) = (MCF_UART_UCR_TX_DISABLED | MCF_UART_UCR_RX_DISABLED); - - /* save the current values */ - info->uimr = 0; - info->baud = baud; - info->databits = databits; - info->parity = parity; - info->stopbits = stopbits; - info->hwflow = hwflow; - - clock_speed = bsp_get_CPU_clock_speed(); - /* determine the baud divisor value */ - divisor = ((clock_speed) / (32 * baud)); - if (divisor < 2) - divisor = 2; - - /* check to see if doing hardware flow control */ - if (hwflow) { - /* set hardware flow options */ - umr1 |= MCF_UART_UMR_RXRTS; - umr2 |= MCF_UART_UMR_TXCTS; - } - - /* determine the new umr values */ - umr1 |= (parity | databits); - -#if 1 /* TZN: maybe needed for santec bus modul handling */ - if (minor==STATIONS_PORT) - umr2 |= (stopbits) | 0x20; /* 0x20 ... set TXRTS just4testing */ - else - umr2 |= (stopbits); -#else - umr2 |= (stopbits); -#endif - - /* reset the uart */ - MCF_UART_UCR(minor) = MCF_UART_UCR_RESET_ERROR; - MCF_UART_UCR(minor) = MCF_UART_UCR_RESET_RX; - MCF_UART_UCR(minor) = MCF_UART_UCR_RESET_TX; - - /* reset the uart mode register and update values */ - MCF_UART_UCR(minor) = MCF_UART_UCR_RESET_MR; - MCF_UART_UMR(minor) = umr1; - MCF_UART_UMR(minor) = umr2; - - /* set the baud rate values */ - MCF_UART_UCSR(minor) = - (MCF_UART_UCSR_RCS_SYS_CLK | MCF_UART_UCSR_TCS_SYS_CLK); - MCF_UART_UBG1(minor) = (divisor & 0xff00) >> 8; - MCF_UART_UBG2(minor) = (divisor & 0x00ff); - - /* enable the uart */ - MCF_UART_UCR(minor) = (MCF_UART_UCR_TX_ENABLED | MCF_UART_UCR_RX_ENABLED); - - /* check to see if interrupts need to be enabled */ - if (info->iomode != TERMIOS_POLLED) { - /* enable rx interrupts */ - info->uimr |= MCF_UART_UIMR_RXRDY_FU; - MCF_UART_UIMR(minor) = info->uimr; - } - - /* check to see if doing hardware flow control */ - if (hwflow) { - /* assert the RTS line */ - MCF_UART_UOP1(minor) = 1; - } - - if (minor==STATIONS_PORT) //maybe needed for santec handling - MCF_UART_UOP0(minor) = 1; - - rtems_interrupt_enable(level); - -} - -/*************************************************************************** - Function : IntUartSetAttributes - - Description : This provides the hardware-dependent portion of tcsetattr(). - value and sets it. At the moment this just sets the baud rate. - - Note: The highest baudrate is 115200 as this stays within - an error of +/- 5% at 25MHz processor clock - ***************************************************************************/ -static int IntUartSetAttributes(int minor, const struct termios *t) -{ - /* set default index values */ - int baud = (int) 19200; - int databits = (int) MCF_UART_UMR_BC_8; - int parity = (int) MCF_UART_UMR_PM_NONE; - int stopbits = (int) MCF_UART_UMR_SB_STOP_BITS_1; - int hwflow = (int) 0; - struct IntUartInfoStruct *info = &IntUartInfo[minor]; - - /* check to see if input is valid */ - if (t != (const struct termios *) 0) { - /* determine baud rate index */ - baud = rtems_termios_baud_to_number(t->c_ospeed); - - /* determine data bits */ - switch (t->c_cflag & CSIZE) { - case CS5: - databits = (int) MCF_UART_UMR_BC_5; - break; - case CS6: - databits = (int) MCF_UART_UMR_BC_6; - break; - case CS7: - databits = (int) MCF_UART_UMR_BC_7; - break; - case CS8: - databits = (int) MCF_UART_UMR_BC_8; - break; - } - - /* determine if parity is enabled */ - if (t->c_cflag & PARENB) { - if (t->c_cflag & PARODD) { - /* odd parity */ - parity = (int) MCF_UART_UMR_PM_ODD; - } else { - /* even parity */ - parity = (int) MCF_UART_UMR_PM_EVEN; - } - } - - /* determine stop bits */ - if (t->c_cflag & CSTOPB) { - /* two stop bits */ - stopbits = (int) MCF_UART_UMR_SB_STOP_BITS_2; - } - - /* check to see if hardware flow control */ - if (t->c_cflag & CRTSCTS) { - hwflow = 1; - } - } - - /* check to see if values have changed */ - if ((baud != info->baud) || - (databits != info->databits) || - (parity != info->parity) || - (stopbits != info->stopbits) || (hwflow != info->hwflow)) { - - /* call function to set values */ - IntUartSet(minor, baud, databits, parity, stopbits, hwflow); - } - - return (RTEMS_SUCCESSFUL); - -} - -/*************************************************************************** - Function : IntUartInterruptHandler - - Description : This is the interrupt handler for the internal uart. It - determines which channel caused the interrupt before queueing any received - chars and dequeueing chars waiting for transmission. - ***************************************************************************/ -static rtems_isr IntUartInterruptHandler(rtems_vector_number v) -{ - unsigned int chan = v - UART_INTC0_IRQ_VECTOR(0); - struct IntUartInfoStruct *info = &IntUartInfo[chan]; - - - /* check to see if received data */ - if (MCF_UART_UISR(chan) & MCF_UART_UISR_RXRDY_FU) { - -#if 0 /* TZN ... just4testing */ - if (MCF_GPIO_PORTTC&MCF_GPIO_PORTTC_PORTTC0) - MCF_GPIO_PORTTC &= ~MCF_GPIO_PORTTC_PORTTC0; - else - MCF_GPIO_PORTTC |= MCF_GPIO_PORTTC_PORTTC0; -#endif - - /* read data and put into the receive buffer */ - while (MCF_UART_USR(chan) & MCF_UART_USR_RXRDY) { - - if (MCF_UART_USR(chan) & MCF_UART_USR_ERROR) { - /* clear the error */ - MCF_UART_UCR(chan) = MCF_UART_UCR_RESET_ERROR; - } - /* put data in rx buffer and check for errors */ - info->rx_buffer[info->rx_in] = MCF_UART_URB(chan); - - /* update buffer values */ - info->rx_in++; - - if (info->rx_in >= RX_BUFFER_SIZE) { - info->rx_in = 0; - } - } - /* Make sure the port has been opened */ - if (info->ttyp) { - - /* check to see if task driven */ - if (info->iomode == TERMIOS_TASK_DRIVEN) { - /* notify rx task that rx buffer has data */ - rtems_termios_rxirq_occured(info->ttyp); - } else { - /* Push up the received data */ - rtems_termios_enqueue_raw_characters(info->ttyp, info->rx_buffer, - info->rx_in); - info->rx_in = 0; - } - } - } - - /* check to see if data needs to be transmitted */ - if ((info->uimr & MCF_UART_UIMR_TXRDY) && - (MCF_UART_UISR(chan) & MCF_UART_UISR_TXRDY)) { - - /* disable tx interrupts */ - info->uimr &= ~MCF_UART_UIMR_TXRDY; - MCF_UART_UIMR(chan) = info->uimr; - - /* tell upper level that character has been sent */ - if (info->ttyp) - rtems_termios_dequeue_characters(info->ttyp, 1); - } -} - -/*************************************************************************** - Function : IntUartInitialize - - Description : This initialises the internal uart hardware for all - internal uarts. If the internal uart is to be interrupt driven then the - interrupt vectors are hooked. - ***************************************************************************/ -static void IntUartInitialize(void) -{ - unsigned int chan; - struct IntUartInfoStruct *info; - rtems_isr_entry old_handler; - rtems_interrupt_level level=UART0_IRQ_LEVEL; - - for (chan = 0; chan < MAX_UART_INFO; chan++) { - info = &IntUartInfo[chan]; - - info->ttyp = NULL; - info->rx_in = 0; - info->rx_out = 0; - info->baud = -1; - info->databits = -1; - info->parity = -1; - info->stopbits = -1; - info->hwflow = -1; - info->iomode = TERMIOS_IRQ_DRIVEN; /*TZN, irq driven console io */ - //info->iomode = TERMIOS_POLLED; /*TZN, just4testint, use polling mode for all UARTS */ - - MCF_UART_UACR(chan) = 0; - MCF_UART_UIMR(chan) = 0; - if (info->iomode != TERMIOS_POLLED) { - rtems_interrupt_catch(IntUartInterruptHandler, - UART_INTC0_IRQ_VECTOR(chan), &old_handler); - } - - /* set uart default values */ - IntUartSetAttributes(chan, NULL); - - /* unmask interrupt */ - rtems_interrupt_disable(level); - switch (chan) { - case 0: - MCF_INTC0_ICR13 = MCF_INTC_ICR_IL(UART0_IRQ_LEVEL) | - MCF_INTC_ICR_IP(UART0_IRQ_PRIORITY); - MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK13 | MCF_INTC_IMRL_MASKALL); - break; - - case 1: - MCF_INTC0_ICR14 = MCF_INTC_ICR_IL(UART1_IRQ_LEVEL) | - MCF_INTC_ICR_IP(UART1_IRQ_PRIORITY); - MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK14 | MCF_INTC_IMRL_MASKALL); - break; - - case 2: - MCF_INTC0_ICR15 = MCF_INTC_ICR_IL(UART2_IRQ_LEVEL) | - MCF_INTC_ICR_IP(UART2_IRQ_PRIORITY); - MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK15 | MCF_INTC_IMRL_MASKALL); - break; - } - rtems_interrupt_enable(level); - - } /* of chan loop */ - -} /* IntUartInitialise */ - -/*************************************************************************** - Function : IntUartInterruptWrite - - Description : This writes a single character to the appropriate uart - channel. This is either called during an interrupt or in the user's task - to initiate a transmit sequence. Calling this routine enables Tx - interrupts. - ***************************************************************************/ -static ssize_t IntUartInterruptWrite(int minor, const char *buf, size_t len) -{ - if (len > 0) { - /* write out character */ - MCF_UART_UTB(minor) = *buf; - - /* enable tx interrupt */ - IntUartInfo[minor].uimr |= MCF_UART_UIMR_TXRDY; - MCF_UART_UIMR(minor) = IntUartInfo[minor].uimr; - } - - return (0); -} - -/*************************************************************************** - Function : IntUartInterruptOpen - - Description : This enables interrupts when the tty is opened. - ***************************************************************************/ -static int IntUartInterruptOpen(int major, int minor, void *arg) -{ - struct IntUartInfoStruct *info = &IntUartInfo[minor]; - - /* enable the uart */ - MCF_UART_UCR(minor) = (MCF_UART_UCR_TX_ENABLED | MCF_UART_UCR_RX_ENABLED); - - /* check to see if interrupts need to be enabled */ - if (info->iomode != TERMIOS_POLLED) { - /* enable rx interrupts */ - info->uimr |= MCF_UART_UIMR_RXRDY_FU; - MCF_UART_UIMR(minor) = info->uimr; - } - - /* check to see if doing hardware flow control */ - if (info->hwflow) { - /* assert the RTS line */ - MCF_UART_UOP1(minor) = 1; - } - - return (0); -} - -/*************************************************************************** - Function : IntUartInterruptClose - - Description : This disables interrupts when the tty is closed. - ***************************************************************************/ -static int IntUartInterruptClose(int major, int minor, void *arg) -{ - struct IntUartInfoStruct *info = &IntUartInfo[minor]; - - /* disable the interrupts and the uart */ - MCF_UART_UIMR(minor) = 0; - MCF_UART_UCR(minor) = (MCF_UART_UCR_TX_DISABLED | MCF_UART_UCR_RX_DISABLED); - - /* reset values */ - info->ttyp = NULL; - info->uimr = 0; - info->rx_in = 0; - info->rx_out = 0; - - return (0); -} - -/*************************************************************************** - Function : IntUartTaskRead - - Description : This reads all available characters from the internal uart - and places them into the termios buffer. The rx interrupts will be - re-enabled after all data has been read. - ***************************************************************************/ -static int IntUartTaskRead(int minor) -{ - char buffer[RX_BUFFER_SIZE]; - int count; - int rx_in; - int index = 0; - struct IntUartInfoStruct *info = &IntUartInfo[minor]; - - /* determine number of values to copy out */ - rx_in = info->rx_in; - if (info->rx_out <= rx_in) { - count = rx_in - info->rx_out; - } else { - count = (RX_BUFFER_SIZE - info->rx_out) + rx_in; - } - - /* copy data into local buffer from rx buffer */ - while ((index < count) && (index < RX_BUFFER_SIZE)) { - /* copy data byte */ - buffer[index] = info->rx_buffer[info->rx_out]; - index++; - - /* increment rx buffer values */ - info->rx_out++; - if (info->rx_out >= RX_BUFFER_SIZE) { - info->rx_out = 0; - } - } - - /* check to see if buffer is not empty */ - if (count > 0) { - /* set characters into termios buffer */ - rtems_termios_enqueue_raw_characters(info->ttyp, buffer, count); - } - - return (EOF); -} - -/*************************************************************************** - Function : IntUartPollRead - - Description : This reads a character from the internal uart. It returns - to the caller without blocking if not character is waiting. - ***************************************************************************/ -static -int IntUartPollRead(int minor) -{ - if ((MCF_UART_USR(minor) & MCF_UART_USR_RXRDY) == 0) - return (-1); - - return (MCF_UART_URB(minor)); -} - -/*************************************************************************** - Function : IntUartPollWrite - - Description : This writes out each character in the buffer to the - appropriate internal uart channel waiting till each one is sucessfully - transmitted. - ***************************************************************************/ -static ssize_t IntUartPollWrite(int minor, const char *buf, size_t len) -{ - /* loop over buffer */ - while (len--) { - /* block until we can transmit */ - while ((MCF_UART_USR(minor) & MCF_UART_USR_TXRDY) == 0) - continue; - /* transmit data byte */ - MCF_UART_UTB(minor) = *buf++; - } - return (0); -} - -/*************************************************************************** - Function : console_initialize - - Description : This initialises termios, both sets of uart hardware before - registering /dev/tty devices for each channel and the system /dev/console. - ***************************************************************************/ -rtems_device_driver console_initialize(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - rtems_status_code status; - - /* Set up TERMIOS */ - rtems_termios_initialize(); - - /* set io modes for the different channels and initialize device */ - IntUartInitialize(); - - /* Register the console port */ - status = rtems_io_register_name("/dev/console", major, CONSOLE_PORT); - if (status != RTEMS_SUCCESSFUL) { - rtems_fatal_error_occurred(status); - } - - /* Register the RS485 port to communicate with SANTEC stations */ - if ((STATIONS_PORT!=CONSOLE_PORT) && (STATIONS_PORT!=BLUETOOTH_PORT)) { - status = rtems_io_register_name("/dev/tty00", major,STATIONS_PORT); - if (status != RTEMS_SUCCESSFUL) { - rtems_fatal_error_occurred(status); - } - } - else { - status=RTEMS_TOO_MANY; - rtems_fatal_error_occurred(status); - } - - /* Register the Bluetooth port */ - if ((BLUETOOTH_PORT!=CONSOLE_PORT) && (BLUETOOTH_PORT!=STATIONS_PORT)) { - status = rtems_io_register_name("/dev/tty01", major, BLUETOOTH_PORT); - if (status != RTEMS_SUCCESSFUL) { - rtems_fatal_error_occurred(status); - } - } - else { - status=RTEMS_TOO_MANY; - rtems_fatal_error_occurred(status); - } - - return (RTEMS_SUCCESSFUL); -} - -/*************************************************************************** - Function : console_open - - Description : This actually opens the device depending on the minor - number set during initialisation. The device specific access routines are - passed to termios when the devices is opened depending on whether it is - polled or not. - ***************************************************************************/ -rtems_device_driver console_open(rtems_device_major_number major, - rtems_device_minor_number minor, void *arg) -{ - rtems_status_code status = RTEMS_INVALID_NUMBER; - rtems_libio_open_close_args_t *args = (rtems_libio_open_close_args_t *) arg; - struct IntUartInfoStruct *info; - - static const rtems_termios_callbacks IntUartPollCallbacks = { - NULL, /* firstOpen */ - NULL, /* lastClose */ - IntUartPollRead, /* pollRead */ - IntUartPollWrite, /* write */ - IntUartSetAttributes, /* setAttributes */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - TERMIOS_POLLED /* mode */ - }; - static const rtems_termios_callbacks IntUartIntrCallbacks = { - IntUartInterruptOpen, /* firstOpen */ - IntUartInterruptClose, /* lastClose */ - NULL, /* pollRead */ - IntUartInterruptWrite, /* write */ - IntUartSetAttributes, /* setAttributes */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - TERMIOS_IRQ_DRIVEN /* mode */ - }; - - static const rtems_termios_callbacks IntUartTaskCallbacks = { - IntUartInterruptOpen, /* firstOpen */ - IntUartInterruptClose, /* lastClose */ - IntUartTaskRead, /* pollRead */ - IntUartInterruptWrite, /* write */ - IntUartSetAttributes, /* setAttributes */ - NULL, /* stopRemoteTx */ - NULL, /* startRemoteTx */ - TERMIOS_TASK_DRIVEN /* mode */ - }; - - /* open the port depending on the minor device number */ - if ((minor >= 0) && (minor < MAX_UART_INFO)) { - info = &IntUartInfo[minor]; - switch (info->iomode) { - case TERMIOS_POLLED: - status = rtems_termios_open(major, minor, arg, &IntUartPollCallbacks); - break; - case TERMIOS_IRQ_DRIVEN: - status = rtems_termios_open(major, minor, arg, &IntUartIntrCallbacks); - info->ttyp = args->iop->data1; - break; - case TERMIOS_TASK_DRIVEN: - status = rtems_termios_open(major, minor, arg, &IntUartTaskCallbacks); - info->ttyp = args->iop->data1; - break; - } - } - - if (status == RTEMS_SUCCESSFUL) { - /* - * Reset the default baudrate. - */ - struct termios term; - - if (tcgetattr(STDIN_FILENO, &term) >= 0) { - term.c_cflag &= ~(CSIZE); - term.c_cflag |= CS8; - term.c_ispeed = B115200; - term.c_ospeed = B115200; - tcsetattr(STDIN_FILENO, TCSANOW, &term); - } - } - - return (status); -} - -/*************************************************************************** - Function : console_close - - Description : This closes the device via termios - ***************************************************************************/ -rtems_device_driver console_close(rtems_device_major_number major, - rtems_device_minor_number minor, void *arg) -{ - return (rtems_termios_close(arg)); -} - -/****************** -********************************************************* - Function : console_read - - Description : Read from the device via termios - ***************************************************************************/ -rtems_device_driver console_read(rtems_device_major_number major, - rtems_device_minor_number minor, void *arg) -{ - return (rtems_termios_read(arg)); -} - -/*************************************************************************** - Function : console_write - - Description : Write to the device via termios - ***************************************************************************/ -rtems_device_driver console_write(rtems_device_major_number major, - rtems_device_minor_number minor, void *arg) -{ - return (rtems_termios_write(arg)); -} - -/*************************************************************************** - Function : console_ioctl - - Description : Pass the IOCtl call to termios - ***************************************************************************/ -rtems_device_driver console_control(rtems_device_major_number major, - rtems_device_minor_number minor, - void *arg) -{ - return (rtems_termios_ioctl(arg)); -} diff --git a/bsps/m68k/mcf5225x/console/debugio.c b/bsps/m68k/mcf5225x/console/debugio.c deleted file mode 100644 index b91048a310..0000000000 --- a/bsps/m68k/mcf5225x/console/debugio.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Multi UART console serial I/O. - * - * TO DO: Add DMA input/output - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include -#include -#include -#include -#include -#include -#include - -#include - -static void _BSP_null_char(char c) -{ - rtems_interrupt_level level=UART0_IRQ_LEVEL; - - rtems_interrupt_disable(level); - while ((MCF_UART_USR(CONSOLE_PORT) & MCF_UART_USR_TXRDY) == 0) - continue; - MCF_UART_UTB(CONSOLE_PORT) = c; - while ((MCF_UART_USR(CONSOLE_PORT) & MCF_UART_USR_TXRDY) == 0) - continue; - rtems_interrupt_enable(level); -} - -BSP_output_char_function_type BSP_output_char = _BSP_null_char; -BSP_polling_getchar_function_type BSP_poll_char = NULL; diff --git a/bsps/m68k/mcf5225x/gdb-init b/bsps/m68k/mcf5225x/gdb-init deleted file mode 100644 index cb94382b4d..0000000000 --- a/bsps/m68k/mcf5225x/gdb-init +++ /dev/null @@ -1,48 +0,0 @@ -# -# Show the exception stack frame. -# -define show-exception-sframe - set $frsr = *(unsigned short *)((unsigned long)$sp + 2) - set $frpc = *(unsigned long *)((unsigned long)$sp + 4) - set $frfvo = *(unsigned short *)((unsigned long)$sp + 0) - set $frcode = $frfvo >> 12 - set $frvect = ($frfvo & 0xFFF) >> 2 - set $frstatus = ((($frfvo >> 10) & 3) << 2) | ($frfvo & 3) - printf "EXCEPTION -- SR:0x%X PC:0x%X FRAME:0x%x VECTOR:%d STATUS:%d\n", $frsr, $frpc, $frcode, $frvect, $frstatus - if $frstatus == 4 - printf " Fault Type: Error on instruction fetch" - end - if $frstatus == 8 - printf " Fault Type: Error on operand write" - end - if $frstatus == 12 - printf " Fault Type: Error on operand read" - end - if $frstatus == 9 - printf " Fault Type: Attempted write to write-protected space" - end -end - -# Add -v and -d flags for bdm info -# Add -B flags to utilize hardware breakpoints when they are availiable - -#target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0 -target remote | m68k-bdm-gdbserver pipe /dev/tblcf2 -B -#monitor set remote-debug 1 - -monitor bdm-reset - -# Set VBR to the beginning of what will be SRAM -monitor bdm-ctl-set 0x0801 0x20000000 - -# Set RAMBAR1 -monitor bdm-ctl-set 0x0C05 0x20000021 - -# Set FLASHBAR -monitor bdm-ctl-set 0x0C04 0x00000061 - -# Enable PST[3:0] signals -set *((char*) 0x40100074) = 0x0F - -# Add the load when debugging from ram which won't happen with rtems! -#load diff --git a/bsps/m68k/mcf5225x/include/bsp.h b/bsps/m68k/mcf5225x/include/bsp.h deleted file mode 100644 index 12f6fb57e8..0000000000 --- a/bsps/m68k/mcf5225x/include/bsp.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsM68kMCF5225X - * - * @brief Global BSP definitions. - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_M68K_MCF5225X_BSP_H -#define LIBBSP_M68K_MCF5225X_BSP_H - -/** - * @defgroup RTEMSBSPsM68kMCF5225X MCF5225X - * - * @ingroup RTEMSBSPsM68k - * - * @brief MCF5225X Board Support Package. - * - * @{ - */ - -#include -#include -#include -#include - -/***************************************************************************/ -/** Hardware data structure headers **/ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Declare base address of peripherals area */ -#define __IPSBAR ((vuint8 *) 0x40000000) - -/***************************************************************************/ -/** Network driver configuration **/ - -/***************************************************************************/ -/** User Definable configuration **/ - -/* define ports for console and DPU specific for BLUETOOTH and STATIONS */ -#define STATIONS_PORT 0 -#define CONSOLE_PORT 1 -#define BLUETOOTH_PORT 2 - -/* externals */ - -/* constants */ - -/* miscellaneous stuff assumed to exist */ - -/* - * Device Driver Table Entries - */ - -/* - * NOTE: Use the standard Console driver entry - */ - -/* - * NOTE: Use the standard Clock driver entry - */ - - -/* functions */ - -uint32_t bsp_get_CPU_clock_speed(void); - -rtems_isr_entry set_vector( - rtems_isr_entry handler, - rtems_vector_number vector, - int type -); - -/* - * Interrupt assignments - * Highest-priority listed first - */ - -#define PIT3_IRQ_LEVEL 4 -#define PIT3_IRQ_PRIORITY 0 - -#define UART0_IRQ_LEVEL 3 -#define UART0_IRQ_PRIORITY 7 -#define UART1_IRQ_LEVEL 3 -#define UART1_IRQ_PRIORITY 6 -#define UART2_IRQ_LEVEL 3 -#define UART2_IRQ_PRIORITY 5 - -/* - * Prototypes for BSP methods which cross file boundaries - */ -void Init5225x(void); - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/bsps/m68k/mcf5225x/include/bsp/irq.h b/bsps/m68k/mcf5225x/include/bsp/irq.h deleted file mode 100644 index 8a97d7a1b0..0000000000 --- a/bsps/m68k/mcf5225x/include/bsp/irq.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/bsps/m68k/mcf5225x/include/tm27.h b/bsps/m68k/mcf5225x/include/tm27.h deleted file mode 100644 index 93dc07878b..0000000000 --- a/bsps/m68k/mcf5225x/include/tm27.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * @file - * @ingroup m68k_mcf5225x - * @brief Implementations for interrupt mechanisms for Time Test 27 - */ - -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef _RTEMS_TMTEST27 -#error "This is an RTEMS internal file you must not include directly." -#endif - -#ifndef __tm27_h -#define __tm27_h - -/* - * Stuff for Time Test 27 - * Don't bother with hardware -- just use a software-interrupt - */ - -#define MUST_WAIT_FOR_INTERRUPT 0 - -#define TM27_USE_VECTOR_HANDLER - -#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) - -#define Cause_tm27_intr() asm volatile ("trap #3"); - -#define Clear_tm27_intr() /* empty */ - -#define Lower_tm27_intr() /* empty */ - -#endif diff --git a/bsps/m68k/mcf5225x/net/fec.c b/bsps/m68k/mcf5225x/net/fec.c deleted file mode 100644 index 903e336d21..0000000000 --- a/bsps/m68k/mcf5225x/net/fec.c +++ /dev/null @@ -1,279 +0,0 @@ -#include -#include - -#include -#include -#include - -#include -#include - -#if LWIP_NETIF_STATUS_CALLBACK -static void mcf5225xif_status(struct netif*); -#endif - - -#if LWIP_NETIF_LINK_CALLBACK -static void mcf5225xif_link(struct netif*); -#endif - -static u8_t __attribute__((aligned (16))) rx_buf[MAX_FRAME_LEN]; -static u8_t __attribute__((aligned (16))) tx_buf[MAX_FRAME_LEN]; - -struct __attribute__((aligned(16))) rx_desc { - u16_t ctl; - u16_t len; - u8_t* ptr; -} rx_bd = { MCF_FEC_RXBD_E | MCF_FEC_RXBD_W ,0,rx_buf}; - -struct tx_desc { - u16_t ctl; - u16_t len; - u8_t* buf; -} tx_bd[2] ={{MCF_FEC_TXBD_R | MCF_FEC_TXBD_L | MCF_FEC_TXBD_TC ,0,tx_buf},{MCF_FEC_TXBD_L | MCF_FEC_TXBD_TC | MCF_FEC_TXBD_W ,0,tx_buf}}; - -static rtems_id net_task_id; - -rtems_isr rx_frame_handler(rtems_vector_number vector) -{ - MCF_INTC0_IMRL |= MCF_INTC_IMRL_MASK27; /* disable FEC RX_INTF interrupt */ - MCF_FEC_EIR |= MCF_FEC_EIR_RXF; /* clear pending interrupt event */ - - rtems_event_send(net_task_id,RTEMS_EVENT_0); - - MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_MASK27; /* enable FEC RX_INTF interrupt */ -} - -void handle_rx_frame(struct netif* netif) -{ - /* Scan the Rx buffer rescriptor ring */ - if (rx_bd.ctl & (MCF_FEC_RXBD_RO1 | MCF_FEC_RXBD_E | MCF_FEC_RXBD_TR)) rx_bd.ctl = MCF_FEC_RXBD_E | MCF_FEC_RXBD_W; /* 1: receive process pending, pbuf still allocated, 2: Buffer empty, quit, 3: frame too long */ - else if (rx_bd.ctl & MCF_FEC_RXBD_L) { /* Last buffer in frame, finalize */ - if (rx_bd.ctl & (MCF_FEC_RXBD_LG | MCF_FEC_RXBD_NO | MCF_FEC_RXBD_CR | MCF_FEC_RXBD_OV)) rx_bd.ctl = MCF_FEC_RXBD_E | MCF_FEC_RXBD_W; /* Reception error */ - else { //pass_frame_to_upper_layer(&rx_bd); - register struct pbuf* lwip_buf=pbuf_alloc(PBUF_RAW,rx_bd.len,PBUF_RAM); - - if (lwip_buf) { - memcpy(lwip_buf->payload,rx_bd.ptr,lwip_buf->tot_len); - switch (htons(((struct eth_hdr *)lwip_buf->payload)->type)) { - /* IP or ARP packet? */ - case ETHTYPE_IP: - /* full packet send to tcpip_thread to process */ - /* skip Ethernet header */ - if (netif->input(lwip_buf, netif) != ERR_OK) pbuf_free(lwip_buf); - break; - case ETHTYPE_ARP: - /* pass p to ARP module */ - etharp_arp_input(netif, (struct eth_addr *)&netif->hwaddr, lwip_buf); - break; - default: - pbuf_free(lwip_buf); - break; - } - lwip_buf = NULL; - rx_bd.ctl = MCF_FEC_RXBD_E | MCF_FEC_RXBD_W; - } - } - } - MCF_FEC_RDAR=0; -} - -/** - * This function does the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - * @param netif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return ERR_OK if the packet could be sent - * an err_t value if the packet couldn't be sent - * - */ -static err_t -low_level_output(struct netif *netif, struct pbuf *p) -{ - struct pbuf *q; - u8_t *ptr; - static u8_t txbd_index; - - /* Suppress 'argument not used' warning */ - netif = netif; - - if (p->tot_len > MAX_FRAME_LEN) - /* Frame too long, drop it */ - return ERR_MEM; - - tx_bd[txbd_index].len = p->tot_len; // < 64 ? p->tot_len+(64-p->tot_len) : p->tot_len; - - /* Walk the pbuf chain, fill the Tx packet buffer */ - q = p; - ptr=tx_bd[txbd_index].buf; - while (q != NULL) { - memcpy(ptr, q->payload, q->len); - ptr += q->len; - q = q->next; - } - tx_bd[txbd_index].ctl |= MCF_FEC_TXBD_R; - - MCF_FEC_TDAR = 0; /* Start transmission */ - - while (MCF_FEC_TDAR != 0); /* wait for transmission complete */ - - MCF_FEC_EIR |= MCF_FEC_EIR_TXF | MCF_FEC_EIR_TXB; - - /* JUST debugging stuff */ - //~ unsigned int my_q_len=0; - //~ while (my_q_lenstate; - - net_task_id=if_config->net_task; - - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - #if LWIP_NETIF_STATUS_CALLBACK - netif->status_callback = mcf5225xif_status; - #endif - #if LWIP_NETIF_LINK_CALLBACK - netif->link_callback = mcf5225xif_link; - #endif - - netif->name[0]=if_config->name[0]; - netif->name[1]=if_config->name[1]; - netif->hwaddr_len = if_config->hwaddr_len; - memcpy(netif->hwaddr,if_config->hwaddr,ETHARP_HWADDR_LEN); /* set the mac address configured by the application */ - netif->mtu = if_config->mtu ; /* maximum transfer unit, configured by application */ - netif->flags = if_config->flags; /* device capabilities, configured by application */ - - - MCF_FEC_ECR |= MCF_FEC_ECR_RESET; - - while (MCF_FEC_ECR&MCF_FEC_ECR_RESET) __asm__ ("nop"); - - if (if_config->phy_init) if_config->phy_init(); /* call application specific optional extern phy initialization function */ - - MCF_FEC_EIMR = 0; - MCF_FEC_EIR= 0xFFFFFFFF; - - //~ Set MAC hardware address: - MCF_FEC_PALR = (u32_t)( (netif->hwaddr[0] << 24) - | (netif->hwaddr[1] << 16) - | (netif->hwaddr[2] << 8 ) - | (netif->hwaddr[3] << 0 ) ); - MCF_FEC_PAUR = (u32_t)( (netif->hwaddr[4] << 24) - | (netif->hwaddr[5] << 16) ); - - /* Do whatever else is needed to initialize interface. */ - MCF_FEC_OPD |= MCF_FEC_OPD_PAUSE_DUR(2); /* pause duration: send 2 pause frames */ - MCF_FEC_IAUR = 0; - MCF_FEC_IALR = 0; - MCF_FEC_GAUR = 0; - MCF_FEC_GALR = 0; - MCF_FEC_EMRBR = ((MAX_FRAME_LEN+15)&~15); //<<4; //RX_RING_SIZE*PBUF_POOL_BUFSIZE; //1536; - MCF_FEC_ERDSR = (uint32_t)&rx_bd; - MCF_FEC_ETDSR = (uint32_t)&tx_bd; - MCF_FEC_RCR = (MAX_FRAME_LEN << 16) | MCF_FEC_RCR_MII_MODE; - MCF_FEC_FRSR = 0x48<<2; /* avoid address clashing of receive and transmit data in FEC fifo */ - - MCF_FEC_TCR = MCF_FEC_TCR_FDEN | MCF_FEC_TCR_HBC; - - MCF_FEC_MIBC = MCF_FEC_MIBC_MIB_DISABLE; - /* TODO: clear MIB RAM??? */ - MCF_FEC_MIBC =~MCF_FEC_MIBC_MIB_DISABLE; /* enable MIBC */ - - MCF_FEC_EIMR = 0; - - rtems_interrupt_catch(rx_frame_handler,91,&old_isr_handler); /* register ISR for RX_INTF interrupt*/ - MCF_INTC0_ICR27=0x10; /* set interrupt level */ - MCF_FEC_EIR= 0xFFFFFFFF; /* clear all pending interrupts */ - MCF_FEC_EIMR |= MCF_FEC_EIR_RXF; /* enable RX_INTF interrupt */ - MCF_INTC0_IMRL &= ~MCF_INTC_IMRL_MASK27; /* enable FEC RX_INTF interrupt */ - - /* enable FEC */ - MCF_FEC_ECR |= MCF_FEC_ECR_ETHER_EN; - /* Start reception, if it's not started already */ - MCF_FEC_RDAR = 0; - - return ERR_OK; -} - -void smi_init(u32_t clk_speed) -{ - MCF_FEC_MSCR = MSCR_MII_SPEED(clk_speed); -} - -void smi_write(u8_t phy_addr,u8_t reg_addr,u16_t data) -{ - MCF_FEC_MMFR = MCF_FEC_MMFR_ST(0x1) | MCF_FEC_MMFR_OP_WRITE | (MCF_FEC_MMFR_PA(phy_addr)) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10 | data; - smi_init(bsp_get_CPU_clock_speed()); /* enable MII clock speed after MMFR is written */ - while ((MCF_FEC_EIR & MCF_FEC_EIR_MII) == 0) { __asm__ ("nop"); } - smi_init(0); /* MII frame sent, disable clock until next operation */ - MCF_FEC_EIR |= MCF_FEC_EIR_MII; -} - -u16_t smi_read(u8_t phy_addr,u8_t reg_addr) -{ - MCF_FEC_MMFR = MCF_FEC_MMFR_ST(0x1) | MCF_FEC_MMFR_OP_READ | (MCF_FEC_MMFR_PA(phy_addr)) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10; - smi_init(bsp_get_CPU_clock_speed()); /* enable MII clock speed after MMFR is written */ - while ((MCF_FEC_EIR & MCF_FEC_EIR_MII) == 0) { __asm__ ("nop"); } - smi_init(0); /* MII frame sent, disable clock until next operation */ - MCF_FEC_EIR |= MCF_FEC_EIR_MII; - - return MCF_FEC_MMFR&0xFFFF; -} - -#if LWIP_NETIF_STATUS_CALLBACK -static void -mcf5225xif_status(struct netif* netif) -{ - - return; -} -#endif - -#if LWIP_NETIF_LINK_CALLBACK -static void -mcf5225xif_link(struct netif* net_if) -{ - u16_t phy_status=smi_read(1,1); /* get phy status */ - - printf("received status: 0x%x\n",phy_status); - - if (!(phy_status&0x4)) - phy_status=smi_read(1,1); - - printf("received status: 0x%x\n",phy_status); - - if (phy_status&0x4) - MCF_GPIO_PORTTC |= MCF_GPIO_PORTTC_PORTTC1; - else - MCF_GPIO_PORTTC &=~MCF_GPIO_PORTTC_PORTTC1; -} -#endif diff --git a/bsps/m68k/mcf5225x/start/bspstart.c b/bsps/m68k/mcf5225x/start/bspstart.c deleted file mode 100644 index 779a7ad2a5..0000000000 --- a/bsps/m68k/mcf5225x/start/bspstart.c +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * This routine does the bulk of the system initialisation. - */ - -/* - * Author: - * David Fiddes, D.J@fiddes.surfaid.org - * http://www.calm.hw.ac.uk/davidf/coldfire/ - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -void __attribute__((weak)) bsp_start(void) -{ -} - -uint32_t __attribute__((weak)) bsp_get_CPU_clock_speed(void) -{ - #define DEF_CLOCK_SPEED 8000000.0F //8.0 MHz - #define MCF_MFD0_2_MASK 0x7000U - #define MCF_RFD0_2_MASK 0x0700U - #define MCF_MFD0_2_OFFSET 4U - - #define SPEED_BIAS ((((MCF_CLOCK_SYNCR & MCF_MFD0_2_MASK) >> 11) + MCF_MFD0_2_OFFSET) / (float)(((MCF_CLOCK_SYNCR & MCF_RFD0_2_MASK)>>7) ? : 1.0F)) - - return MCF_CLOCK_SYNCR & MCF_CLOCK_SYNCR_PLLEN ? SPEED_BIAS * DEF_CLOCK_SPEED : DEF_CLOCK_SPEED; -} diff --git a/bsps/m68k/mcf5225x/start/init5225x.c b/bsps/m68k/mcf5225x/start/init5225x.c deleted file mode 100644 index caf7db1953..0000000000 --- a/bsps/m68k/mcf5225x/start/init5225x.c +++ /dev/null @@ -1,84 +0,0 @@ -/* - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * - * This is where the real hardware setup is done. A minimal stack - * has been provided by the start.S code. No normal C or RTEMS - * functions can be called from here. - */ - -#include -#include - -extern void _wr_vbr(uint32_t); - -extern long _d0_reset,_d1_reset,_M68kSpuriousInterruptCount; - -/* - * From linkcmds - */ - -extern uint8_t _INTERRUPT_VECTOR[]; - -extern uint8_t _clear_start[]; -extern uint8_t _clear_end[]; - -extern uint8_t _data_src_start[]; -extern uint8_t _data_dest_start[]; -extern uint8_t _data_dest_end[]; - -void Init5225x(void) -{ - register uint32_t i; - register uint32_t *dp, *sp; - register uint8_t *dbp, *sbp; - - /* - * Copy the vector table to RAM - */ - - if (&_VBR != (void *)_INTERRUPT_VECTOR) { - sp = (uint32_t *) _INTERRUPT_VECTOR; - dp = (uint32_t *) &_VBR; - for (i = 0; i < 256; i++) { - *dp++ = *sp++; - } - } - - /* - * Move initialized data from ROM to RAM. - */ - if (_data_src_start != _data_dest_start) { - dbp = (uint8_t *) _data_dest_start; - sbp = (uint8_t *) _data_src_start; - i = _data_dest_end - _data_dest_start; - while (i--) - *dbp++ = *sbp++; - } - - asm __volatile__ ("move.l %%d5,%0\n\t":"=r" (_d0_reset)); - asm __volatile__ ("move.l %%d6,%0\n\t":"=r" (_d1_reset)); - - /* - * Zero uninitialized data - */ - - if (_clear_start != _clear_end) { - sbp = _clear_start; - dbp = _clear_end; - i = dbp - sbp; - while (i--) - *sbp++ = 0; - } - -//_wr_vbr((uint32_t) &_VBR); - asm volatile("move.l %0,%%d7;movec %%d7,%%vbr\n\t"::"i"(&_VBR): "cc"); - - /* - * We have to call some kind of RTEMS function here! - */ - - boot_card(0); - for (;;) ; -} diff --git a/bsps/m68k/mcf5225x/start/linkcmds b/bsps/m68k/mcf5225x/start/linkcmds deleted file mode 100644 index 3bd6a29cf0..0000000000 --- a/bsps/m68k/mcf5225x/start/linkcmds +++ /dev/null @@ -1,215 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * This file contains directives for the GNU linker which are specific - * to the Freescale ColdFire mcf52258 - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE.e - */ - -/* - * Declare some sizes. - */ -RamBase = DEFINED(RamBase) ? RamBase : 0x20000000; -RamSize = DEFINED(RamSize) ? RamSize : 64K; -RamEnd = RamBase + RamSize; -HeapSize = DEFINED(HeapSize) ? HeapSize : 0x0; -_FlashBase = DEFINED(_FlashBase) ? _FlashBase : 0x00000000; - -_VBR = 0x20000000; - -ENTRY(start) -STARTUP(start.o) - - -MEMORY -{ - sram : ORIGIN = 0x20000000, LENGTH = 64K - flash : ORIGIN = 0x00000000, LENGTH = 512K -} - -SECTIONS -{ - /* - * Text, data and bss segments - */ - .text : { - - *(.text*) - *(.ram_code) - - /* - * C++ constructors/destructors - */ - *(.gnu.linkonce.t.*) - - /* - * Initialization and finalization code. - * - * Various files can provide initialization and finalization - * functions. crtbegin.o and crtend.o are two instances. The - * body of these functions are in .init and .fini sections. We - * accumulate the bodies here, and prepend function prologues - * from crti.o and function epilogues from crtn.o. crti.o must - * be linked first; crtn.o must be linked last. Because these - * are wildcards, it doesn't matter if the user does not - * actually link against crti.o and crtn.o; the linker won't - * look for a file to match a wildcard. The wildcard also - * means that it doesn't matter which directory crti.o and - * crtn.o are in. - */ - PROVIDE (_init = .); - *crti.o(.init) - *(.init) - *crtn.o(.init) - PROVIDE (_fini = .); - *crti.o(.fini) - *(.fini) - *crtn.o(.fini) - - /* - * Special FreeBSD sysctl sections. - */ - . = ALIGN (16); - __start_set_sysctl_set = .; - *(set_sysctl_*); - __stop_set_sysctl_set = ABSOLUTE(.); - *(set_domain_*); - *(set_pseudo_*); - - /* - * C++ constructors/destructors - * - * gcc uses crtbegin.o to find the start of the constructors - * and destructors so we make sure it is first. Because this - * is a wildcard, it doesn't matter if the user does not - * actually link against crtbegin.o; the linker won't look for - * a file to match a wildcard. The wildcard also means that - * it doesn't matter which directory crtbegin.o is in. The - * constructor and destructor list are terminated in - * crtend.o. The same comments apply to it. - */ - . = ALIGN (16); - *crtbegin.o(.ctors) - *(.ctors) - *crtend.o(.ctors) - *crtbegin.o(.dtors) - *(.dtors) - *crtend.o(.dtors) - - /* - * Exception frame info - */ - . = ALIGN (16); - *(.eh_frame) - - /* - * Read-only data - */ - . = ALIGN (16); - _rodata_start = . ; - *(.rodata*) - KEEP (*(SORT(.rtemsroset.*))) - *(.gnu.linkonce.r*) - - . = ALIGN (16); - - *(.console_gdb_xfer) - *(.bootstrap_data) - } >flash - - .tdata : { - _TLS_Data_begin = .; - *(.tdata .tdata.* .gnu.linkonce.td.*) - _TLS_Data_end = .; - . = ALIGN(16); - _estuff = .; - PROVIDE (_etext = .); - } >flash - - .tbss : { - _TLS_BSS_begin = .; - *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) - _TLS_BSS_end = .; - } >flash - - _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; - _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; - _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; - _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; - _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; - _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); - - .data 0x20000400 : AT (_estuff) - { - PROVIDE( _data_dest_start = . ); - PROVIDE( _copy_start = .); - *(.data*) - KEEP (*(SORT(.rtemsrwset.*))) - *(.gnu.linkonce.d*) - *(.gcc_except_table*) - *(.jcr) - . = ALIGN (16); - PROVIDE (_edata = .); - PROVIDE (_copy_end = .); - PROVIDE (_data_dest_end = . ); - } >sram - - _data_src_start = _estuff; - _data_src_end = _data_dest_start + SIZEOF(.data); - - .bss : - { - PROVIDE (_clear_start = .); - *(.bss*) - *(COMMON) - . = ALIGN (16); - PROVIDE (_end = .); - PROVIDE (_clear_end = .); - } >sram - - .noinit (NOLOAD) : { - *(SORT_BY_NAME (SORT_BY_ALIGNMENT (.noinit*))) - } >sram - - .rtemsstack (NOLOAD) : { - *(SORT(.rtemsstack.*)) - PROVIDE(WorkAreaBase = .); - } >sram - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - - /* Addition to let linker know about custom section for GDB pretty-printing support. */ - .debug_gdb_scripts 0 : { *(.debug_gdb_scripts) } - - PROVIDE (end_of_all = .); -} diff --git a/bsps/m68k/mcf5225x/start/start.S b/bsps/m68k/mcf5225x/start/start.S deleted file mode 100644 index f62e53f590..0000000000 --- a/bsps/m68k/mcf5225x/start/start.S +++ /dev/null @@ -1,467 +0,0 @@ -/* SPDX-License-Identifier: BSD-2-Clause */ - -/* - * dpu-mcf52258 startup code - * - * This file contains the entry point for the application. - * The name of this entry point is compiler dependent. - * It jumps to the BSP which is responsible for performing - * all initialization. - * - * COPYRIGHT (c) 1989-1998. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -BEGIN_CODE - - PUBLIC (_INTERRUPT_VECTOR) -SYM(_INTERRUPT_VECTOR): - - .long _ISR_Stack_area_end /* 00 Initial 'SSP' */ - .long SYM(start) /* 01 Initial PC */ - .long SYM(_uhoh) /* 02 Access Error */ - .long SYM(_uhoh) /* 03 Address Error */ - .long SYM(_uhoh) /* 04 Illegal Instruction */ - .long SYM(_uhoh) /* 05 Divide by Zero */ - .long SYM(_uhoh) /* 06 Reserved */ - .long SYM(_uhoh) /* 07 Reserved */ - .long SYM(_uhoh) /* 08 Privilege Violation */ - .long SYM(_uhoh) /* 09 Trace */ - .long SYM(_uhoh) /* 10 Unimplemented A-Line */ - .long SYM(_uhoh) /* 11 Unimplemented F-Line */ - .long SYM(_uhoh) /* 12 Debug Interrupt */ - .long SYM(_uhoh) /* 13 Reserved */ - .long SYM(_uhoh) /* 14 Format Error */ - .long SYM(_uhoh) /* 15 Reserved */ - .long SYM(_uhoh) /* 16 Reserved */ - .long SYM(_uhoh) /* 17 Reserved */ - .long SYM(_uhoh) /* 18 Reserved */ - .long SYM(_uhoh) /* 19 Reserved */ - .long SYM(_uhoh) /* 20 Reserved */ - .long SYM(_uhoh) /* 21 Reserved */ - .long SYM(_uhoh) /* 22 Reserved */ - .long SYM(_uhoh) /* 23 Reserved */ - .long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */ - .long SYM(_uhoh) /* 25 Reserved */ - .long SYM(_uhoh) /* 26 Reserved */ - .long SYM(_uhoh) /* 27 Reserved */ - .long SYM(_uhoh) /* 28 Reserved */ - .long SYM(_uhoh) /* 29 Reserved */ - .long SYM(_uhoh) /* 30 Reserved */ - .long SYM(_uhoh) /* 31 Reserved */ - .long SYM(_uhoh) /* 32 TRAP #0 */ - .long SYM(_uhoh) /* 33 TRAP #1 */ - .long SYM(_uhoh) /* 34 TRAP #2 */ - .long SYM(_uhoh) /* 35 TRAP #3 */ - .long SYM(_uhoh) /* 36 TRAP #4 */ - .long SYM(_uhoh) /* 37 TRAP #5 */ - .long SYM(_uhoh) /* 38 TRAP #6 */ - .long SYM(_uhoh) /* 39 TRAP #7 */ - .long SYM(_uhoh) /* 40 TRAP #8 */ - .long SYM(_uhoh) /* 41 TRAP #9 */ - .long SYM(_uhoh) /* 42 TRAP #10 */ - .long SYM(_uhoh) /* 43 TRAP #11 */ - .long SYM(_uhoh) /* 44 TRAP #12 */ - .long SYM(_uhoh) /* 45 TRAP #13 */ - .long SYM(_uhoh) /* 46 TRAP #14 */ - .long SYM(_uhoh) /* 47 TRAP #15 */ - .long SYM(_uhoh) /* 48 Reserved */ - .long SYM(_uhoh) /* 49 Reserved */ - .long SYM(_uhoh) /* 50 Reserved */ - .long SYM(_uhoh) /* 51 Reserved */ - .long SYM(_uhoh) /* 52 Reserved */ - .long SYM(_uhoh) /* 53 Reserved */ - .long SYM(_uhoh) /* 54 Reserved */ - .long SYM(_uhoh) /* 55 Reserved */ - .long SYM(_uhoh) /* 56 Reserved */ - .long SYM(_uhoh) /* 57 Reserved */ - .long SYM(_uhoh) /* 58 Reserved */ - .long SYM(_uhoh) /* 59 Reserved */ - .long SYM(_uhoh) /* 60 Reserved */ - .long SYM(_uhoh) /* 61 Reserved */ - .long SYM(_uhoh) /* 62 Reserved */ - .long SYM(_uhoh) /* 63 Reserved */ - - /* INTC0 */ - - .long SYM(_uhoh) /* 64*/ - .long SYM(_uhoh) /* 65*/ - .long SYM(_uhoh) /* 66*/ - .long SYM(_uhoh) /* 67*/ - .long SYM(_uhoh) /* 68*/ - .long SYM(_uhoh) /* 69*/ - .long SYM(_uhoh) /* 70*/ - .long SYM(_uhoh) /* 71*/ - .long SYM(_uhoh) /* 72*/ - .long SYM(_uhoh) /* 73*/ - .long SYM(_uhoh) /* 74*/ - .long SYM(_uhoh) /* 75*/ - .long SYM(_uhoh) /* 76*/ - .long SYM(_uhoh) /* 77*/ - .long SYM(_uhoh) /* 78*/ - .long SYM(_uhoh) /* 79*/ - .long SYM(_uhoh) /* 80*/ - .long SYM(_uhoh) /* 81*/ - .long SYM(_uhoh) /* 82*/ - .long SYM(_uhoh) /* 83*/ - .long SYM(_uhoh) /* 84*/ - .long SYM(_uhoh) /* 85*/ - .long SYM(_uhoh) /* 86*/ - .long SYM(_uhoh) /* 87*/ - .long SYM(_uhoh) /* 88*/ - .long SYM(_uhoh) /* 89*/ - .long SYM(_uhoh) /* 90*/ - .long SYM(_uhoh) /* 91*/ - .long SYM(_uhoh) /* 92*/ - .long SYM(_uhoh) /* 93*/ - .long SYM(_uhoh) /* 94*/ - .long SYM(_uhoh) /* 95*/ - .long SYM(_uhoh) /* 96*/ - .long SYM(_uhoh) /* 97*/ - .long SYM(_uhoh) /* 98*/ - .long SYM(_uhoh) /* 99*/ - .long SYM(_uhoh) /* 100*/ - .long SYM(_uhoh) /* 101*/ - .long SYM(_uhoh) /* 102*/ - .long SYM(_uhoh) /* 103*/ - .long SYM(_uhoh) /* 104*/ - .long SYM(_uhoh) /* 105*/ - .long SYM(_uhoh) /* 106*/ - .long SYM(_uhoh) /* 107*/ - .long SYM(_uhoh) /* 108*/ - .long SYM(_uhoh) /* 109*/ - .long SYM(_uhoh) /* 110*/ - .long SYM(_uhoh) /* 111*/ - .long SYM(_uhoh) /* 112*/ - .long SYM(_uhoh) /* 113*/ - .long SYM(_uhoh) /* 114*/ - .long SYM(_uhoh) /* 115*/ - .long SYM(_uhoh) /* 116*/ - .long SYM(_uhoh) /* 117*/ - .long SYM(_uhoh) /* 118*/ - .long SYM(_uhoh) /* 119*/ - .long SYM(_uhoh) /* 120*/ - .long SYM(_uhoh) /* 121*/ - .long SYM(_uhoh) /* 122*/ - .long SYM(_uhoh) /* 123*/ - .long SYM(_uhoh) /* 124*/ - .long SYM(_uhoh) /* 125*/ - .long SYM(_uhoh) /* 126*/ - .long SYM(_uhoh) /* 127*/ - - /* INTC1 */ - - .long SYM(_uhoh) /* 128*/ - .long SYM(_uhoh) /* 129*/ - .long SYM(_uhoh) /* 130*/ - .long SYM(_uhoh) /* 131*/ - .long SYM(_uhoh) /* 132*/ - .long SYM(_uhoh) /* 133*/ - .long SYM(_uhoh) /* 134*/ - .long SYM(_uhoh) /* 135*/ - .long SYM(_uhoh) /* 136*/ - .long SYM(_uhoh) /* 137*/ - .long SYM(_uhoh) /* 138*/ - .long SYM(_uhoh) /* 139*/ - .long SYM(_uhoh) /* 140*/ - .long SYM(_uhoh) /* 141*/ - .long SYM(_uhoh) /* 142*/ - .long SYM(_uhoh) /* 143*/ - .long SYM(_uhoh) /* 144*/ - .long SYM(_uhoh) /* 145*/ - .long SYM(_uhoh) /* 146*/ - .long SYM(_uhoh) /* 147*/ - .long SYM(_uhoh) /* 148*/ - .long SYM(_uhoh) /* 149*/ - .long SYM(_uhoh) /* 150*/ - .long SYM(_uhoh) /* 151*/ - .long SYM(_uhoh) /* 152*/ - .long SYM(_uhoh) /* 153*/ - .long SYM(_uhoh) /* 154*/ - .long SYM(_uhoh) /* 155*/ - .long SYM(_uhoh) /* 156*/ - .long SYM(_uhoh) /* 157*/ - .long SYM(_uhoh) /* 158*/ - .long SYM(_uhoh) /* 159*/ - .long SYM(_uhoh) /* 160*/ - .long SYM(_uhoh) /* 161*/ - .long SYM(_uhoh) /* 162*/ - .long SYM(_uhoh) /* 163*/ - .long SYM(_uhoh) /* 164*/ - .long SYM(_uhoh) /* 165*/ - .long SYM(_uhoh) /* 166*/ - .long SYM(_uhoh) /* 167*/ - .long SYM(_uhoh) /* 168*/ - .long SYM(_uhoh) /* 169*/ - .long SYM(_uhoh) /* 170*/ - .long SYM(_uhoh) /* 171*/ - .long SYM(_uhoh) /* 172*/ - .long SYM(_uhoh) /* 173*/ - .long SYM(_uhoh) /* 174*/ - .long SYM(_uhoh) /* 175*/ - .long SYM(_uhoh) /* 176*/ - .long SYM(_uhoh) /* 177*/ - .long SYM(_uhoh) /* 178*/ - .long SYM(_uhoh) /* 179*/ - .long SYM(_uhoh) /* 180*/ - .long SYM(_uhoh) /* 181*/ - .long SYM(_uhoh) /* 182*/ - .long SYM(_uhoh) /* 183*/ - .long SYM(_uhoh) /* 184*/ - .long SYM(_uhoh) /* 185*/ - .long SYM(_uhoh) /* 186*/ - .long SYM(_uhoh) /* 187*/ - .long SYM(_uhoh) /* 188*/ - .long SYM(_uhoh) /* 189*/ - .long SYM(_uhoh) /* 190*/ - .long SYM(_uhoh) /* 191*/ - .long SYM(_uhoh) /* 192*/ - - /* */ - - .long SYM(_uhoh) /* 193*/ - .long SYM(_uhoh) /* 194*/ - .long SYM(_uhoh) /* 195*/ - .long SYM(_uhoh) /* 196*/ - .long SYM(_uhoh) /* 197*/ - .long SYM(_uhoh) /* 198*/ - .long SYM(_uhoh) /* 199*/ - .long SYM(_uhoh) /* 200*/ - .long SYM(_uhoh) /* 201*/ - .long SYM(_uhoh) /* 202*/ - .long SYM(_uhoh) /* 203*/ - .long SYM(_uhoh) /* 204*/ - .long SYM(_uhoh) /* 205*/ - .long SYM(_uhoh) /* 206*/ - .long SYM(_uhoh) /* 207*/ - .long SYM(_uhoh) /* 208*/ - .long SYM(_uhoh) /* 209*/ - .long SYM(_uhoh) /* 210*/ - .long SYM(_uhoh) /* 211*/ - .long SYM(_uhoh) /* 212*/ - .long SYM(_uhoh) /* 213*/ - .long SYM(_uhoh) /* 214*/ - .long SYM(_uhoh) /* 215*/ - .long SYM(_uhoh) /* 216*/ - .long SYM(_uhoh) /* 217*/ - .long SYM(_uhoh) /* 218*/ - .long SYM(_uhoh) /* 219*/ - .long SYM(_uhoh) /* 220*/ - .long SYM(_uhoh) /* 221*/ - .long SYM(_uhoh) /* 222*/ - .long SYM(_uhoh) /* 223*/ - .long SYM(_uhoh) /* 224*/ - .long SYM(_uhoh) /* 225*/ - .long SYM(_uhoh) /* 226*/ - .long SYM(_uhoh) /* 227*/ - .long SYM(_uhoh) /* 228*/ - .long SYM(_uhoh) /* 229*/ - .long SYM(_uhoh) /* 230*/ - .long SYM(_uhoh) /* 231*/ - .long SYM(_uhoh) /* 232*/ - .long SYM(_uhoh) /* 233*/ - .long SYM(_uhoh) /* 234*/ - .long SYM(_uhoh) /* 235*/ - .long SYM(_uhoh) /* 236*/ - .long SYM(_uhoh) /* 237*/ - .long SYM(_uhoh) /* 238*/ - .long SYM(_uhoh) /* 239*/ - .long SYM(_uhoh) /* 240*/ - .long SYM(_uhoh) /* 241*/ - .long SYM(_uhoh) /* 242*/ - .long SYM(_uhoh) /* 243*/ - .long SYM(_uhoh) /* 244*/ - .long SYM(_uhoh) /* 245*/ - .long SYM(_uhoh) /* 246*/ - .long SYM(_uhoh) /* 247*/ - .long SYM(_uhoh) /* 248*/ - .long SYM(_uhoh) /* 249*/ - .long SYM(_uhoh) /* 250*/ - .long SYM(_uhoh) /* 251*/ - .long SYM(_uhoh) /* 252*/ - .long SYM(_uhoh) /* 253*/ - .long SYM(_uhoh) /* 254*/ - .long SYM(_uhoh) /* 255*/ - -/* - * We must write the flash configuration here. - This portion of RAM is shadowed - * by some flash registers, so we can't put code here! - */ - - PUBLIC (_FLASH_CONFIGURATION_FIELD) -SYM(_FLASH_CONFIGURATION_FIELD): - -_key_upper: .long 0x5a5a5a5a -_key_lower: .long 0x5a5a5a5a -_cfm_prot: .long 0x00000000 -_cfm_sacc: .long 0x00000000 -_cfm_dacc: .long 0x00000000 -_cfm_msec: .long 0x80000000 //enable the KEYEN bit to bypass security in backdoor mode - -/* - * Default trap handler - * With an oscilloscope you can see AS* stop - */ -.align 4 - PUBLIC (_uhoh) -SYM(_uhoh): - nop | Leave spot for breakpoint - stop #0x2700 | Stop with interrupts disabled - bra.w SYM(_uhoh) | Stuck forever - -/* - * Spurious Interrupt Handler - */ -.align 4 - PUBLIC (_spuriousInterrupt) -SYM(_spuriousInterrupt): - addql #1, SYM(_M68kSpuriousInterruptCount) - rte - -/* - * Write VBR Register - */ - -/* -.align 4 - PUBLIC (_wr_vbr) -SYM(_wr_vbr): - move.l 4(sp), d0 - movec d0, vbr - nop - rts -*/ - -/* - * Board startup - * Disable watchdog, interrupts - * Enable sram - */ -.align 4 - PUBLIC (start) -SYM(start): - - /* Mask off interupts */ - move.w #0x2700, sr - - /* Save off intial D0 and D1 to NOT scratched registers conforming to ABI C calling convention */ - move.l d0,d5; - move.l d1,d6; - - /* Initialize RAMBAR: locate SRAM and validate it */ - move.l #RamBase, d7 - add.l #0x21, d7 - movec d7, %rambar - - /* Locate Stack Pointer */ - move.l #_ISR_Stack_area_end, sp - - /* Initialize FLASHBAR */ - move.l #_FlashBase, d7 - cmp.l #0x00000000, d7 - bne _change_flashbar - add.l #0x61, d7 - movec d7, %flashbar - -_continue_startup: - - /* Locate Stack Pointer */ -// move.l #_ISR_Stack_area_end, sp //is done automatically by the CPU - - /* - * Remainder of the startup code is handled by C code - * This never returns - */ - - jmp SYM(Init5225x) - -_change_flashbar: - /* - * The following sequence is used to set FLASHBAR. Since we may - * be executing from Flash, we must put the routine into SRAM for - * execution and then jump back to Flash using the new address. - * - * The following instructions are coded into the SRAM: - * - * move.l #(__FLASH + 0x61),d0 - * movec d0, FLASHBAR - * jmp _continue_startup - * - * An arbitrary SRAM address is chosen until the real address - * can be loaded. - * - * This routine is not necessary if the default Flash address - * (0x00000000) is used. - * - * If running in SRAM, change_flashbar should not be executed - */ - - move.l #RamBase, a0 - - /* Code "move.l #(__FLASH + 0x61),d0" into SRAM */ - move.w #0x203C, d0 - move.w d0, (a0)+ - move.l #_FlashBase, d0 - add.l #0x61, d0 - move.l d0, (a0)+ - - /* Code "movec d0,FLASHBAR" into SRAM */ - move.l #0x4e7b0C04, d0 - move.l d0, (a0)+ - - /* Code "jmp _continue_startup" into SRAM */ - move.w #0x4EF9, d0 - move.w d0, (a0)+ - move.l #_continue_startup, d0 - move.l d0, (a0)+ - - /* Jump to code segment in internal SRAM */ - jmp RamBase - -END_CODE - - -BEGIN_DATA_DCL - - .align 4 - -PUBLIC (_M68kSpuriousInterruptCount) -SYM (_M68kSpuriousInterruptCount): - .long 0 - -PUBLIC (_d0_reset) -SYM (_d0_reset): - .long 0 - -PUBLIC (_d1_reset) -SYM (_d1_reset): - .long 0 - -END_DATA_DCL - -END - diff --git a/spec/build/bsps/m68k/mcf5225x/abi.yml b/spec/build/bsps/m68k/mcf5225x/abi.yml deleted file mode 100644 index efd6b90c50..0000000000 --- a/spec/build/bsps/m68k/mcf5225x/abi.yml +++ /dev/null @@ -1,18 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- get-string: null -- split: null -- env-append: null -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: -- enabled-by: true - value: - - -mcpu=52235 -description: | - ABI flags -enabled-by: true -links: [] -name: ABI_FLAGS -type: build diff --git a/spec/build/bsps/m68k/mcf5225x/bspmcf5225x.yml b/spec/build/bsps/m68k/mcf5225x/bspmcf5225x.yml deleted file mode 100644 index 8f7560fcb4..0000000000 --- a/spec/build/bsps/m68k/mcf5225x/bspmcf5225x.yml +++ /dev/null @@ -1,56 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -arch: m68k -bsp: mcf5225x -build-type: bsp -cflags: [] -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -family: mcf5225x -includes: [] -install: -- destination: ${BSP_INCLUDEDIR} - source: - - bsps/m68k/mcf5225x/include/bsp.h -- destination: ${BSP_INCLUDEDIR}/bsp - source: - - bsps/m68k/mcf5225x/include/bsp/irq.h -- destination: ${BSP_LIBDIR} - source: - - bsps/m68k/mcf5225x/start/linkcmds -links: -- role: build-dependency - uid: ../grp -- role: build-dependency - uid: abi -- role: build-dependency - uid: start -- role: build-dependency - uid: tstmcf5225x -- role: build-dependency - uid: ../../obj -- role: build-dependency - uid: ../../objirqdflt -- role: build-dependency - uid: ../../objmem -- role: build-dependency - uid: ../../opto2 -- role: build-dependency - uid: ../../bspopts -source: -- bsps/m68k/mcf5225x/btimer/btimer.c -- bsps/m68k/mcf5225x/clock/clock.c -- bsps/m68k/mcf5225x/console/console.c -- bsps/m68k/mcf5225x/console/debugio.c -- bsps/m68k/mcf5225x/start/bspstart.c -- bsps/m68k/mcf5225x/start/init5225x.c -- bsps/m68k/shared/cache/cache-mcf5225x.c -- bsps/m68k/shared/m68kidle.c -- bsps/m68k/shared/memProbe.c -- bsps/shared/dev/getentropy/getentropy-cpucounter.c -- bsps/shared/start/bspreset-loop.c -- bsps/shared/start/gettargethash-default.c -- bsps/shared/start/sbrk.c -- bsps/shared/start/setvec.c -type: build diff --git a/spec/build/bsps/m68k/mcf5225x/start.yml b/spec/build/bsps/m68k/mcf5225x/start.yml deleted file mode 100644 index becd71d946..0000000000 --- a/spec/build/bsps/m68k/mcf5225x/start.yml +++ /dev/null @@ -1,14 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -asflags: [] -build-type: start-file -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -cppflags: [] -enabled-by: true -includes: [] -install-path: ${BSP_LIBDIR} -links: [] -source: -- bsps/m68k/mcf5225x/start/start.S -target: start.o -type: build diff --git a/spec/build/bsps/m68k/mcf5225x/tstmcf5225x.yml b/spec/build/bsps/m68k/mcf5225x/tstmcf5225x.yml deleted file mode 100644 index 0f4021d5f3..0000000000 --- a/spec/build/bsps/m68k/mcf5225x/tstmcf5225x.yml +++ /dev/null @@ -1,19 +0,0 @@ -SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause -actions: -- set-test-state: - reason: null - state: exclude - tests: - - cdtest - - fileio - - iostream -build-type: option -copyrights: -- Copyright (C) 2020 embedded brains GmbH & Co. KG -default: [] -description: '' -enabled-by: true -links: -- role: build-dependency - uid: ../../tstsmallmem -type: build