From af75447c1a4f20dd3a44ccf70b8b562a634d45d3 Mon Sep 17 00:00:00 2001 From: Thomas Wucher Date: Tue, 4 Nov 2025 11:43:41 +0000 Subject: [PATCH] bsps/powerpc: Fix ppc_exc_interrupt not saving r3 correctly On SPE enabled builds the extended bits of r3 need to be saved separately to the stack. Make ppc_exc_interrupt to do that correctly. Fixes #5389 --- bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S b/bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S index 701fc20bbb..d6de0f939e 100644 --- a/bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S +++ b/bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S @@ -106,7 +106,7 @@ ppc_exc_interrupt: * Save high order part of SCRATCH_1_REGISTER here. The low order part * was saved in the minimal prologue. */ - evmergehi SCRATCH_1_REGISTER, SCRATCH_1_REGISTER, FRAME_REGISTER + evmergehi FRAME_REGISTER, SCRATCH_1_REGISTER, SCRATCH_1_REGISTER PPC_REG_STORE FRAME_REGISTER, GPR3_OFFSET(r1) #endif