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https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-28 00:23:44 +08:00
NGMP PCI: added support for NGMP prototype boards
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@@ -164,6 +164,7 @@ struct drvmgr_drv_ops gr_cpci_leon4_n2x_ops =
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struct pci_dev_id_match gr_cpci_leon4_n2x_ids[] =
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struct pci_dev_id_match gr_cpci_leon4_n2x_ids[] =
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{
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{
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PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_LEON4_N2X),
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PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_LEON4_N2X),
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PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_NGMP_PROTO),
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PCIID_END_TABLE /* Mark end of table */
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PCIID_END_TABLE /* Mark end of table */
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};
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};
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@@ -351,15 +352,17 @@ int gr_cpci_leon4_n2x_hw_init1(struct gr_cpci_leon4_n2x_priv *priv)
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/* Get extended Interrupt controller IRQ number */
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/* Get extended Interrupt controller IRQ number */
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priv->eirq = (priv->irq->mpstat >> 16) & 0xf;
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priv->eirq = (priv->irq->mpstat >> 16) & 0xf;
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/* Find first Clock-Gating unit, enable/disable the requested cores */
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/* Find first Clock-Gating unit, enable/disable the requested cores.
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* It is optional in order to support FPGA prototypes.
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*/
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priv->cg = NULL;
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tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus,
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tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus,
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(OPTIONS_ALL|OPTIONS_APB_SLVS),
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(OPTIONS_ALL|OPTIONS_APB_SLVS),
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VENDOR_GAISLER, GAISLER_CLKGATE,
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VENDOR_GAISLER, GAISLER_CLKGATE,
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ambapp_find_by_idx, NULL);
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ambapp_find_by_idx, NULL);
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if ( !tmp ) {
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if (tmp)
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return -5;
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priv->cg = (struct l4n2x_grcg_regs *)DEV_TO_APB(tmp)->start;
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}
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priv->cg = (struct l4n2x_grcg_regs *)DEV_TO_APB(tmp)->start;
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/* Do reset and enable sequence only if not already enabled */
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/* Do reset and enable sequence only if not already enabled */
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if (priv->cg && ((enabled = priv->cg->enable) != priv->cg_en_mask)) {
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if (priv->cg && ((enabled = priv->cg->enable) != priv->cg_en_mask)) {
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/* First disable already enabled cores */
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/* First disable already enabled cores */
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@@ -18,3 +18,4 @@
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#define PCIID_DEVICE_GR_TMTC_1553 0x0198 /* GR-TMTC-1553 */
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#define PCIID_DEVICE_GR_TMTC_1553 0x0198 /* GR-TMTC-1553 */
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#define PCIID_DEVICE_GR_RASTA_SPW_RTR 0x0062 /* GR-RASTA-SPW-ROUTER */
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#define PCIID_DEVICE_GR_RASTA_SPW_RTR 0x0062 /* GR-RASTA-SPW-ROUTER */
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#define PCIID_DEVICE_GR_LEON4_N2X 0x0061 /* GR-CPCI-LEON4-N2X */
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#define PCIID_DEVICE_GR_LEON4_N2X 0x0061 /* GR-CPCI-LEON4-N2X */
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#define PCIID_DEVICE_GR_NGMP_PROTO 0x0064 /* GR-NGMP_PROTO */
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