From a8d3868badc7b0ad7c1317208e3f56cf652bef82 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 17 Aug 2026 05:17:43 +0200 Subject: [PATCH] cpukit/score/cpu/or1k: Fix _CPU_ISR_Is_enabled() The level is a supervision register value and the predicate masked it with CPU_OR1K_SPR_SR. That is the number of the supervision register and not a bit in it, so the test looked at the supervisor mode and instruction cache bits instead of the interrupt enable bit and returned true for a level with the interrupts disabled. Update #5684. Assisted-by: Claude:claude-opus-5 claude-code Signed-off-by: Sebastian Huber --- cpukit/score/cpu/or1k/include/rtems/score/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h index c3aab1593f..ed36baa5f6 100644 --- a/cpukit/score/cpu/or1k/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/or1k/include/rtems/score/cpu.h @@ -319,7 +319,12 @@ static inline void or1k_interrupt_enable(uint32_t level) static inline bool _CPU_ISR_Is_enabled( uint32_t level ) { - return ( level & CPU_OR1K_SPR_SR ) != 0; + /* + * The level is a supervision register value. CPU_OR1K_SPR_SR is the + * number of that register and not a bit in it, so it must not be used as + * a mask here. + */ + return ( level & CPU_OR1K_SPR_SR_IEE ) != 0; } /*