From 9c1340a309b4b153e29f8b11779ab82603d8df69 Mon Sep 17 00:00:00 2001 From: Allan Hessenflow Date: Wed, 17 Dec 2025 16:38:37 -0800 Subject: [PATCH] bsps: add new BSP for Silicon Labs EFM32GG11 includes support for UART/USART, I2C, SPI, TRNG --- bsps/arm/efm32gg11/README.md | 7 + bsps/arm/efm32gg11/console/console.c | 806 ++++++++++++++++++ bsps/arm/efm32gg11/dma/efm32gg11_dma.c | 111 +++ bsps/arm/efm32gg11/gpio/efm32gg11_gpio.c | 242 ++++++ bsps/arm/efm32gg11/i2c/i2c.c | 419 +++++++++ bsps/arm/efm32gg11/include/bsp.h | 75 ++ .../efm32gg11/include/bsp/efm32gg11_clock.h | 57 ++ .../arm/efm32gg11/include/bsp/efm32gg11_dma.h | 48 ++ .../efm32gg11/include/bsp/efm32gg11_gpio.h | 66 ++ bsps/arm/efm32gg11/include/bsp/i2c.h | 43 + bsps/arm/efm32gg11/include/bsp/irq.h | 49 ++ bsps/arm/efm32gg11/include/bsp/processor.h | 80 ++ bsps/arm/efm32gg11/include/bsp/spi.h | 43 + bsps/arm/efm32gg11/include/tm27.h | 36 + bsps/arm/efm32gg11/spi/spi.c | 560 ++++++++++++ bsps/arm/efm32gg11/start/bspreset.c | 43 + bsps/arm/efm32gg11/start/bspstart.c | 49 ++ bsps/arm/efm32gg11/start/bspstarthook.c | 41 + bsps/arm/efm32gg11/start/efm32gg11_clock.c | 241 ++++++ bsps/arm/efm32gg11/start/linkcmds.intflash | 21 + bsps/arm/efm32gg11/start/linkcmds.intsram | 23 + bsps/arm/efm32gg11/trng/efm32gg11_trng.c | 91 ++ spec/build/bsps/arm/efm32gg11/abi.yml | 21 + spec/build/bsps/arm/efm32gg11/bspefm32g11.yml | 23 + spec/build/bsps/arm/efm32gg11/grp.yml | 323 +++++++ spec/build/bsps/arm/efm32gg11/linkcmds.yml | 11 + .../bsps/arm/efm32gg11/linkcmdsmemory.yml | 14 + spec/build/bsps/arm/efm32gg11/obj.yml | 123 +++ spec/build/bsps/arm/efm32gg11/optconcsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optconctrl.yml | 17 + .../build/bsps/arm/efm32gg11/optconctsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optconidx.yml | 17 + .../build/bsps/arm/efm32gg11/optconrtsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optconrxloc.yml | 17 + .../build/bsps/arm/efm32gg11/optcontiming.yml | 17 + spec/build/bsps/arm/efm32gg11/optcontxloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optcontype.yml | 17 + spec/build/bsps/arm/efm32gg11/optconvcom.yml | 17 + spec/build/bsps/arm/efm32gg11/optdevice.yml | 37 + .../build/bsps/arm/efm32gg11/opthfrcofreq.yml | 17 + spec/build/bsps/arm/efm32gg11/opthfxofreq.yml | 17 + .../bsps/arm/efm32gg11/opthfxotuning.yml | 17 + spec/build/bsps/arm/efm32gg11/opthfxotype.yml | 17 + spec/build/bsps/arm/efm32gg11/opti2c0idx.yml | 17 + .../bsps/arm/efm32gg11/opti2c0sclloc.yml | 17 + .../bsps/arm/efm32gg11/opti2c0sdaloc.yml | 17 + spec/build/bsps/arm/efm32gg11/opti2c1idx.yml | 17 + .../bsps/arm/efm32gg11/opti2c1sclloc.yml | 17 + .../bsps/arm/efm32gg11/opti2c1sdaloc.yml | 17 + spec/build/bsps/arm/efm32gg11/opti2c2idx.yml | 17 + .../bsps/arm/efm32gg11/opti2c2sclloc.yml | 17 + .../bsps/arm/efm32gg11/opti2c2sdaloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optincludes.yml | 16 + spec/build/bsps/arm/efm32gg11/optlfxofreq.yml | 17 + spec/build/bsps/arm/efm32gg11/optlfxogain.yml | 17 + .../bsps/arm/efm32gg11/optlfxotuning.yml | 17 + spec/build/bsps/arm/efm32gg11/optlfxotype.yml | 17 + spec/build/bsps/arm/efm32gg11/optlinkcmds.yml | 18 + .../bsps/arm/efm32gg11/optspi0clkloc.yml | 17 + .../bsps/arm/efm32gg11/optspi0cspins.yml | 17 + spec/build/bsps/arm/efm32gg11/optspi0idx.yml | 17 + .../build/bsps/arm/efm32gg11/optspi0rxdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi0rxloc.yml | 17 + .../build/bsps/arm/efm32gg11/optspi0txdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi0txloc.yml | 17 + .../bsps/arm/efm32gg11/optspi1clkloc.yml | 17 + .../bsps/arm/efm32gg11/optspi1cspins.yml | 17 + spec/build/bsps/arm/efm32gg11/optspi1idx.yml | 17 + .../build/bsps/arm/efm32gg11/optspi1rxdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi1rxloc.yml | 17 + .../build/bsps/arm/efm32gg11/optspi1txdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi1txloc.yml | 17 + .../bsps/arm/efm32gg11/optspi2clkloc.yml | 17 + .../bsps/arm/efm32gg11/optspi2cspins.yml | 17 + spec/build/bsps/arm/efm32gg11/optspi2idx.yml | 17 + .../build/bsps/arm/efm32gg11/optspi2rxdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi2rxloc.yml | 17 + .../build/bsps/arm/efm32gg11/optspi2txdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi2txloc.yml | 17 + .../bsps/arm/efm32gg11/optspi3clkloc.yml | 17 + .../bsps/arm/efm32gg11/optspi3cspins.yml | 17 + spec/build/bsps/arm/efm32gg11/optspi3idx.yml | 17 + .../build/bsps/arm/efm32gg11/optspi3rxdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi3rxloc.yml | 17 + .../build/bsps/arm/efm32gg11/optspi3txdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi3txloc.yml | 17 + .../bsps/arm/efm32gg11/optspi4clkloc.yml | 17 + .../bsps/arm/efm32gg11/optspi4cspins.yml | 17 + spec/build/bsps/arm/efm32gg11/optspi4idx.yml | 17 + .../build/bsps/arm/efm32gg11/optspi4rxdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi4rxloc.yml | 17 + .../build/bsps/arm/efm32gg11/optspi4txdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi4txloc.yml | 17 + .../bsps/arm/efm32gg11/optspi5clkloc.yml | 17 + .../bsps/arm/efm32gg11/optspi5cspins.yml | 17 + spec/build/bsps/arm/efm32gg11/optspi5idx.yml | 17 + .../build/bsps/arm/efm32gg11/optspi5rxdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi5rxloc.yml | 17 + .../build/bsps/arm/efm32gg11/optspi5txdma.yml | 17 + .../build/bsps/arm/efm32gg11/optspi5txloc.yml | 17 + .../bsps/arm/efm32gg11/optttys1csloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys1ctrl.yml | 17 + .../bsps/arm/efm32gg11/optttys1ctsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optttys1idx.yml | 17 + .../bsps/arm/efm32gg11/optttys1rtsloc.yml | 17 + .../bsps/arm/efm32gg11/optttys1rxloc.yml | 17 + .../bsps/arm/efm32gg11/optttys1timing.yml | 17 + .../bsps/arm/efm32gg11/optttys1txloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys1type.yml | 17 + .../bsps/arm/efm32gg11/optttys2csloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys2ctrl.yml | 17 + .../bsps/arm/efm32gg11/optttys2ctsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optttys2idx.yml | 17 + .../bsps/arm/efm32gg11/optttys2rtsloc.yml | 17 + .../bsps/arm/efm32gg11/optttys2rxloc.yml | 17 + .../bsps/arm/efm32gg11/optttys2timing.yml | 17 + .../bsps/arm/efm32gg11/optttys2txloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys2type.yml | 17 + .../bsps/arm/efm32gg11/optttys3csloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys3ctrl.yml | 17 + .../bsps/arm/efm32gg11/optttys3ctsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optttys3idx.yml | 17 + .../bsps/arm/efm32gg11/optttys3rtsloc.yml | 17 + .../bsps/arm/efm32gg11/optttys3rxloc.yml | 17 + .../bsps/arm/efm32gg11/optttys3timing.yml | 17 + .../bsps/arm/efm32gg11/optttys3txloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys3type.yml | 17 + .../bsps/arm/efm32gg11/optttys4csloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys4ctrl.yml | 17 + .../bsps/arm/efm32gg11/optttys4ctsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optttys4idx.yml | 17 + .../bsps/arm/efm32gg11/optttys4rtsloc.yml | 17 + .../bsps/arm/efm32gg11/optttys4rxloc.yml | 17 + .../bsps/arm/efm32gg11/optttys4timing.yml | 17 + .../bsps/arm/efm32gg11/optttys4txloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys4type.yml | 17 + .../bsps/arm/efm32gg11/optttys5csloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys5ctrl.yml | 17 + .../bsps/arm/efm32gg11/optttys5ctsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optttys5idx.yml | 17 + .../bsps/arm/efm32gg11/optttys5rtsloc.yml | 17 + .../bsps/arm/efm32gg11/optttys5rxloc.yml | 17 + .../bsps/arm/efm32gg11/optttys5timing.yml | 17 + .../bsps/arm/efm32gg11/optttys5txloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys5type.yml | 17 + .../bsps/arm/efm32gg11/optttys6csloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys6ctrl.yml | 17 + .../bsps/arm/efm32gg11/optttys6ctsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optttys6idx.yml | 17 + .../bsps/arm/efm32gg11/optttys6rtsloc.yml | 17 + .../bsps/arm/efm32gg11/optttys6rxloc.yml | 17 + .../bsps/arm/efm32gg11/optttys6timing.yml | 17 + .../bsps/arm/efm32gg11/optttys6txloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys6type.yml | 17 + .../bsps/arm/efm32gg11/optttys7csloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys7ctrl.yml | 17 + .../bsps/arm/efm32gg11/optttys7ctsloc.yml | 17 + spec/build/bsps/arm/efm32gg11/optttys7idx.yml | 17 + .../bsps/arm/efm32gg11/optttys7rtsloc.yml | 17 + .../bsps/arm/efm32gg11/optttys7rxloc.yml | 17 + .../bsps/arm/efm32gg11/optttys7timing.yml | 17 + .../bsps/arm/efm32gg11/optttys7txloc.yml | 17 + .../build/bsps/arm/efm32gg11/optttys7type.yml | 17 + .../build/bsps/arm/efm32gg11/tstefm32gg11.yml | 27 + spec/build/cpukit/optlibdebugger.yml | 1 + spec/build/testsuites/libtests/dl13.yml | 1 + 166 files changed, 6010 insertions(+) create mode 100644 bsps/arm/efm32gg11/README.md create mode 100644 bsps/arm/efm32gg11/console/console.c create mode 100644 bsps/arm/efm32gg11/dma/efm32gg11_dma.c create mode 100644 bsps/arm/efm32gg11/gpio/efm32gg11_gpio.c create mode 100644 bsps/arm/efm32gg11/i2c/i2c.c create mode 100644 bsps/arm/efm32gg11/include/bsp.h create mode 100644 bsps/arm/efm32gg11/include/bsp/efm32gg11_clock.h create mode 100644 bsps/arm/efm32gg11/include/bsp/efm32gg11_dma.h create mode 100644 bsps/arm/efm32gg11/include/bsp/efm32gg11_gpio.h create mode 100644 bsps/arm/efm32gg11/include/bsp/i2c.h create mode 100644 bsps/arm/efm32gg11/include/bsp/irq.h create mode 100644 bsps/arm/efm32gg11/include/bsp/processor.h create mode 100644 bsps/arm/efm32gg11/include/bsp/spi.h create mode 100644 bsps/arm/efm32gg11/include/tm27.h create mode 100644 bsps/arm/efm32gg11/spi/spi.c create mode 100644 bsps/arm/efm32gg11/start/bspreset.c create mode 100644 bsps/arm/efm32gg11/start/bspstart.c create mode 100644 bsps/arm/efm32gg11/start/bspstarthook.c create mode 100644 bsps/arm/efm32gg11/start/efm32gg11_clock.c create mode 100644 bsps/arm/efm32gg11/start/linkcmds.intflash create mode 100644 bsps/arm/efm32gg11/start/linkcmds.intsram create mode 100644 bsps/arm/efm32gg11/trng/efm32gg11_trng.c create mode 100644 spec/build/bsps/arm/efm32gg11/abi.yml create mode 100644 spec/build/bsps/arm/efm32gg11/bspefm32g11.yml create mode 100644 spec/build/bsps/arm/efm32gg11/grp.yml create mode 100644 spec/build/bsps/arm/efm32gg11/linkcmds.yml create mode 100644 spec/build/bsps/arm/efm32gg11/linkcmdsmemory.yml create mode 100644 spec/build/bsps/arm/efm32gg11/obj.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optconcsloc.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optconctrl.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optconctsloc.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optconidx.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optconrtsloc.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optconrxloc.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optcontiming.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optcontxloc.yml create mode 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create mode 100644 spec/build/bsps/arm/efm32gg11/optttys7ctsloc.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optttys7idx.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optttys7rtsloc.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optttys7rxloc.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optttys7timing.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optttys7txloc.yml create mode 100644 spec/build/bsps/arm/efm32gg11/optttys7type.yml create mode 100644 spec/build/bsps/arm/efm32gg11/tstefm32gg11.yml diff --git a/bsps/arm/efm32gg11/README.md b/bsps/arm/efm32gg11/README.md new file mode 100644 index 0000000000..d6965b68f7 --- /dev/null +++ b/bsps/arm/efm32gg11/README.md @@ -0,0 +1,7 @@ +# EFM32GG11 + +This BSP should be usable for any boards based on the Silicon Labs +EFM32GG11B family. The default configuration parameters match the +EFM32GG11 Giant Gecko Starter Kit: + +https://silabs.com/development-tools/mcu/32-bit/efm32gg11-starter-kit diff --git a/bsps/arm/efm32gg11/console/console.c b/bsps/arm/efm32gg11/console/console.c new file mode 100644 index 0000000000..92e3035f92 --- /dev/null +++ b/bsps/arm/efm32gg11/console/console.c @@ -0,0 +1,806 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 Console Driver + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#define PASTE2(a,b) a ## b +#define PASTE3(a,b,c) a ## b ## c +#define PASTE4(a,b,c,d) a ## b ## c ## d + +#define REGS(t, i) PASTE2(t, i) +#define TX_IRQN(t, i) PASTE3(t, i, _TX_IRQn) +#define RX_IRQN(t, i) PASTE3(t, i, _RX_IRQn) +#define TX_PORT(t, i, l) PASTE4(AF_, t, i, _TX_PORT)(l) +#define TX_PIN(t, i, l) PASTE4(AF_, t, i, _TX_PIN)(l) +#define RX_PORT(t, i, l) PASTE4(AF_, t, i, _RX_PORT)(l) +#define RX_PIN(t, i, l) PASTE4(AF_, t, i, _RX_PIN)(l) +#define CTS_PORT(t, i, l) PASTE4(AF_, t, i, _CTS_PORT)(l) +#define CTS_PIN(t, i, l) PASTE4(AF_, t, i, _CTS_PIN)(l) +#define RTS_PORT(t, i, l) PASTE4(AF_, t, i, _RTS_PORT)(l) +#define RTS_PIN(t, i, l) PASTE4(AF_, t, i, _RTS_PIN)(l) +#define CS_PORT(t, i, l) PASTE4(AF_, t, i, _CS_PORT)(l) +#define CS_PIN(t, i, l ) PASTE4(AF_, t, i, _CS_PIN)(l) +#define HFPERCLKEN0_MASK(t, i) PASTE3(CMU_HFPERCLKEN0_, t, i) + + +static struct usart_context_s { + rtems_termios_device_context base; /* must be first */ + const char *name; + USART_TypeDef *regs; + rtems_vector_number rx_irq; + rtems_vector_number tx_irq; + int tx_pin_loc; + int tx_port; + int tx_pin; + int rx_pin_loc; + int rx_port; + int rx_pin; + int cts_pin_loc; + int cts_port; + int cts_pin; + int rts_pin_loc; + int rts_port; + int rts_pin; + int cs_pin_loc; + int cs_port; + int cs_pin; + uint32_t ctrl; + uint32_t timing; + uint32_t hfperclken0_mask; +#ifdef BSP_CONSOLE_USE_INTERRUPTS + bool transmitting; +#endif +} usart_instances[] = { + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("console"), + .name = CONSOLE_DEVICE_NAME, + .regs = REGS(EFM32GG11_CONSOLE_TYPE, EFM32GG11_CONSOLE_DEVICE_INDEX), + .rx_irq = RX_IRQN(EFM32GG11_CONSOLE_TYPE, EFM32GG11_CONSOLE_DEVICE_INDEX), + .tx_irq = TX_IRQN(EFM32GG11_CONSOLE_TYPE, EFM32GG11_CONSOLE_DEVICE_INDEX), + .tx_pin_loc = EFM32GG11_CONSOLE_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_TX_LOC), + .rx_pin_loc = EFM32GG11_CONSOLE_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_RX_LOC), + .cts_pin_loc = EFM32GG11_CONSOLE_CTS_LOC, + .cts_port = CTS_PORT(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_CTS_LOC), + .cts_pin = CTS_PIN(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_CTS_LOC), + .rts_pin_loc = EFM32GG11_CONSOLE_RTS_LOC, + .rts_port = RTS_PORT(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_RTS_LOC), + .rts_pin = RTS_PIN(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_RTS_LOC), + .cs_pin_loc = EFM32GG11_CONSOLE_CS_LOC, + .cs_port = CS_PORT(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_CS_LOC), + .cs_pin = CS_PIN(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX, + EFM32GG11_CONSOLE_CS_LOC), + .ctrl = EFM32GG11_CONSOLE_CTRL, + .timing = EFM32GG11_CONSOLE_TIMING, + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_CONSOLE_TYPE, + EFM32GG11_CONSOLE_DEVICE_INDEX) + }, +#if defined(EFM32GG11_TTYS1_DEVICE_INDEX) && EFM32GG11_TTYS1_DEVICE_INDEX >= 0 + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("ttyS1"), + .name = "/dev/ttyS1", + .regs = REGS(EFM32GG11_TTYS1_TYPE, EFM32GG11_TTYS1_DEVICE_INDEX), + .rx_irq = RX_IRQN(EFM32GG11_TTYS1_TYPE, EFM32GG11_TTYS1_DEVICE_INDEX), + .tx_irq = TX_IRQN(EFM32GG11_TTYS1_TYPE, EFM32GG11_TTYS1_DEVICE_INDEX), + .tx_pin_loc = EFM32GG11_TTYS1_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_TX_LOC), + .rx_pin_loc = EFM32GG11_TTYS1_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_RX_LOC), + .cts_pin_loc = EFM32GG11_TTYS1_CTS_LOC, + .cts_port = CTS_PORT(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_CTS_LOC), + .cts_pin = CTS_PIN(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_CTS_LOC), + .rts_pin_loc = EFM32GG11_TTYS1_RTS_LOC, + .rts_port = RTS_PORT(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_RTS_LOC), + .rts_pin = RTS_PIN(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_RTS_LOC), + .cs_pin_loc = EFM32GG11_TTYS1_CS_LOC, + .cs_port = CS_PORT(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_CS_LOC), + .cs_pin = CS_PIN(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX, + EFM32GG11_TTYS1_CS_LOC), + .ctrl = EFM32GG11_TTYS1_CTRL, + .timing = EFM32GG11_TTYS1_TIMING, + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_TTYS1_TYPE, + EFM32GG11_TTYS1_DEVICE_INDEX) + }, +#endif +#if defined(EFM32GG11_TTYS2_DEVICE_INDEX) && EFM32GG11_TTYS2_DEVICE_INDEX >= 0 + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("ttyS2"), + .name = "/dev/ttyS2", + .regs = REGS(EFM32GG11_TTYS2_TYPE, EFM32GG11_TTYS2_DEVICE_INDEX), + .rx_irq = RX_IRQN(EFM32GG11_TTYS2_TYPE, EFM32GG11_TTYS2_DEVICE_INDEX), + .tx_irq = TX_IRQN(EFM32GG11_TTYS2_TYPE, EFM32GG11_TTYS2_DEVICE_INDEX), + .tx_pin_loc = EFM32GG11_TTYS2_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_TX_LOC), + .rx_pin_loc = EFM32GG11_TTYS2_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_RX_LOC), + .cts_pin_loc = EFM32GG11_TTYS2_CTS_LOC, + .cts_port = CTS_PORT(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_CTS_LOC), + .cts_pin = CTS_PIN(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_CTS_LOC), + .rts_pin_loc = EFM32GG11_TTYS2_RTS_LOC, + .rts_port = RTS_PORT(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_RTS_LOC), + .rts_pin = RTS_PIN(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_RTS_LOC), + .cs_pin_loc = EFM32GG11_TTYS2_CS_LOC, + .cs_port = CS_PORT(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_CS_LOC), + .cs_pin = CS_PIN(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX, + EFM32GG11_TTYS2_CS_LOC), + .ctrl = EFM32GG11_TTYS2_CTRL, + .timing = EFM32GG11_TTYS2_TIMING, + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_TTYS2_TYPE, + EFM32GG11_TTYS2_DEVICE_INDEX) + }, +#endif +#if defined(EFM32GG11_TTYS3_DEVICE_INDEX) && EFM32GG11_TTYS3_DEVICE_INDEX >= 0 + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("ttyS3"), + .name = "/dev/ttyS3", + .regs = REGS(EFM32GG11_TTYS3_TYPE, EFM32GG11_TTYS3_DEVICE_INDEX), + .rx_irq = RX_IRQN(EFM32GG11_TTYS3_TYPE, EFM32GG11_TTYS3_DEVICE_INDEX), + .tx_irq = TX_IRQN(EFM32GG11_TTYS3_TYPE, EFM32GG11_TTYS3_DEVICE_INDEX), + .tx_pin_loc = EFM32GG11_TTYS3_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_TX_LOC), + .rx_pin_loc = EFM32GG11_TTYS3_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_RX_LOC), + .cts_pin_loc = EFM32GG11_TTYS3_CTS_LOC, + .cts_port = CTS_PORT(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_CTS_LOC), + .cts_pin = CTS_PIN(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_CTS_LOC), + .rts_pin_loc = EFM32GG11_TTYS3_RTS_LOC, + .rts_port = RTS_PORT(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_RTS_LOC), + .rts_pin = RTS_PIN(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_RTS_LOC), + .cs_pin_loc = EFM32GG11_TTYS3_CS_LOC, + .cs_port = CS_PORT(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_CS_LOC), + .cs_pin = CS_PIN(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX, + EFM32GG11_TTYS3_CS_LOC), + .ctrl = EFM32GG11_TTYS3_CTRL, + .timing = EFM32GG11_TTYS3_TIMING, + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_TTYS3_TYPE, + EFM32GG11_TTYS3_DEVICE_INDEX) + }, +#endif +#if defined(EFM32GG11_TTYS4_DEVICE_INDEX) && EFM32GG11_TTYS4_DEVICE_INDEX >= 0 + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("ttyS4"), + .name = "/dev/ttyS4", + .regs = REGS(EFM32GG11_TTYS4_TYPE, EFM32GG11_TTYS4_DEVICE_INDEX), + .rx_irq = RX_IRQN(EFM32GG11_TTYS4_TYPE, EFM32GG11_TTYS4_DEVICE_INDEX), + .tx_irq = TX_IRQN(EFM32GG11_TTYS4_TYPE, EFM32GG11_TTYS4_DEVICE_INDEX), + .tx_pin_loc = EFM32GG11_TTYS4_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_TX_LOC), + .rx_pin_loc = EFM32GG11_TTYS4_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_RX_LOC), + .cts_pin_loc = EFM32GG11_TTYS4_CTS_LOC, + .cts_port = CTS_PORT(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_CTS_LOC), + .cts_pin = CTS_PIN(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_CTS_LOC), + .rts_pin_loc = EFM32GG11_TTYS4_RTS_LOC, + .rts_port = RTS_PORT(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_RTS_LOC), + .rts_pin = RTS_PIN(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_RTS_LOC), + .cs_pin_loc = EFM32GG11_TTYS4_CS_LOC, + .cs_port = CS_PORT(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_CS_LOC), + .cs_pin = CS_PIN(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX, + EFM32GG11_TTYS4_CS_LOC), + .ctrl = EFM32GG11_TTYS4_CTRL, + .timing = EFM32GG11_TTYS4_TIMING, + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_TTYS4_TYPE, + EFM32GG11_TTYS4_DEVICE_INDEX) + }, +#endif +#if defined(EFM32GG11_TTYS5_DEVICE_INDEX) && EFM32GG11_TTYS5_DEVICE_INDEX >= 0 + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("ttyS5"), + .name = "/dev/ttyS5", + .regs = REGS(EFM32GG11_TTYS5_TYPE, EFM32GG11_TTYS5_DEVICE_INDEX), + .rx_irq = RX_IRQN(EFM32GG11_TTYS5_TYPE, EFM32GG11_TTYS5_DEVICE_INDEX), + .tx_irq = TX_IRQN(EFM32GG11_TTYS5_TYPE, EFM32GG11_TTYS5_DEVICE_INDEX), + .tx_pin_loc = EFM32GG11_TTYS5_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_TX_LOC), + .rx_pin_loc = EFM32GG11_TTYS5_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_RX_LOC), + .cts_pin_loc = EFM32GG11_TTYS5_CTS_LOC, + .cts_port = CTS_PORT(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_CTS_LOC), + .cts_pin = CTS_PIN(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_CTS_LOC), + .rts_pin_loc = EFM32GG11_TTYS5_RTS_LOC, + .rts_port = RTS_PORT(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_RTS_LOC), + .rts_pin = RTS_PIN(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_RTS_LOC), + .cs_pin_loc = EFM32GG11_TTYS5_CS_LOC, + .cs_port = CS_PORT(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_CS_LOC), + .cs_pin = CS_PIN(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX, + EFM32GG11_TTYS5_CS_LOC), + .ctrl = EFM32GG11_TTYS5_CTRL, + .timing = EFM32GG11_TTYS5_TIMING, + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_TTYS5_TYPE, + EFM32GG11_TTYS5_DEVICE_INDEX) + }, +#endif +#if defined(EFM32GG11_TTYS6_DEVICE_INDEX) && EFM32GG11_TTYS6_DEVICE_INDEX >= 0 + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("ttyS6"), + .name = "/dev/ttyS6", + .regs = REGS(EFM32GG11_TTYS6_TYPE, EFM32GG11_TTYS6_DEVICE_INDEX), + .rx_irq = RX_IRQN(EFM32GG11_TTYS6_TYPE, EFM32GG11_TTYS6_DEVICE_INDEX), + .tx_irq = TX_IRQN(EFM32GG11_TTYS6_TYPE, EFM32GG11_TTYS6_DEVICE_INDEX), + .tx_pin_loc = EFM32GG11_TTYS6_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_TX_LOC), + .rx_pin_loc = EFM32GG11_TTYS6_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_RX_LOC), + .cts_pin_loc = EFM32GG11_TTYS6_CTS_LOC, + .cts_port = CTS_PORT(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_CTS_LOC), + .cts_pin = CTS_PIN(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_CTS_LOC), + .rts_pin_loc = EFM32GG11_TTYS6_RTS_LOC, + .rts_port = RTS_PORT(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_RTS_LOC), + .rts_pin = RTS_PIN(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_RTS_LOC), + .cs_pin_loc = EFM32GG11_TTYS6_CS_LOC, + .cs_port = CS_PORT(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_CS_LOC), + .cs_pin = CS_PIN(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX, + EFM32GG11_TTYS6_CS_LOC), + .ctrl = EFM32GG11_TTYS6_CTRL, + .timing = EFM32GG11_TTYS6_TIMING, + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_TTYS6_TYPE, + EFM32GG11_TTYS6_DEVICE_INDEX) + }, +#endif +#if defined(EFM32GG11_TTYS7_DEVICE_INDEX) && EFM32GG11_TTYS7_DEVICE_INDEX >= 0 + { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("ttyS7"), + .name = "/dev/ttyS7", + .regs = REGS(EFM32GG11_TTYS7_TYPE, EFM32GG11_TTYS7_DEVICE_INDEX), + .rx_irq = RX_IRQN(EFM32GG11_TTYS7_TYPE, EFM32GG11_TTYS7_DEVICE_INDEX), + .tx_irq = TX_IRQN(EFM32GG11_TTYS7_TYPE, EFM32GG11_TTYS7_DEVICE_INDEX), + .tx_pin_loc = EFM32GG11_TTYS7_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_TX_LOC), + .rx_pin_loc = EFM32GG11_TTYS7_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_RX_LOC), + .cts_pin_loc = EFM32GG11_TTYS7_CTS_LOC, + .cts_port = CTS_PORT(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_CTS_LOC), + .cts_pin = CTS_PIN(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_CTS_LOC), + .rts_pin_loc = EFM32GG11_TTYS7_RTS_LOC, + .rts_port = RTS_PORT(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_RTS_LOC), + .rts_pin = RTS_PIN(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_RTS_LOC), + .cs_pin_loc = EFM32GG11_TTYS7_CS_LOC, + .cs_port = CS_PORT(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_CS_LOC), + .cs_pin = CS_PIN(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX, + EFM32GG11_TTYS7_CS_LOC), + .ctrl = EFM32GG11_TTYS7_CTRL, + .timing = EFM32GG11_TTYS7_TIMING, + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_TTYS7_TYPE, + EFM32GG11_TTYS7_DEVICE_INDEX) + }, +#endif +}; + + +#ifdef BSP_CONSOLE_USE_INTERRUPTS +static void usart_rx_interrupt(void *arg) +{ + rtems_termios_tty *tty = (rtems_termios_tty *) arg; + struct usart_context_s *ctx = rtems_termios_get_device_context(tty); + USART_TypeDef *regs = ctx->regs; + + while (regs->STATUS & USART_STATUS_RXDATAV) + { + char data = regs->RXDATA; + rtems_termios_enqueue_raw_characters(tty, &data, sizeof(data)); + } +} + +static void usart_tx_interrupt(void *arg) +{ + rtems_termios_tty *tty = (rtems_termios_tty *) arg; + struct usart_context_s *ctx = rtems_termios_get_device_context(tty); + USART_TypeDef *regs = ctx->regs; + + while (ctx->transmitting && (regs->STATUS & USART_STATUS_TXBL)) + rtems_termios_dequeue_characters(tty, 1); +} +#endif /* BSP_CONSOLE_USE_INTERRUPTS */ + +static void attribs_init( + struct usart_context_s *ctx, + rtems_termios_baud_t baud, + tcflag_t c_cflag) +{ + USART_TypeDef *regs = ctx->regs; + uint32_t r; + + r = (regs == USART2) ? efm32gg11_clock.hfperbclk : efm32gg11_clock.hfperclk; + r = (16 * r + baud / 2) / baud - 256; + /* There seems to be a discrepancy of a factor of 8 between rev 1.2 of the + EFM32 Giant Gecko 11 Family Reference Manual and reality. */ + r = (r + 4) / 8; + + r <<= _USART_CLKDIV_DIV_SHIFT; + regs->CLKDIV = r; + + switch (c_cflag & CSIZE) { + case CS5: + r = USART_FRAME_DATABITS_FIVE; + break; + case CS6: + r = USART_FRAME_DATABITS_SIX; + break; + case CS7: + r = USART_FRAME_DATABITS_SEVEN; + break; + case CS8: + default: + r = USART_FRAME_DATABITS_EIGHT; + break; + } + + if (c_cflag & PARENB) { + if (c_cflag & PARODD) + r |= USART_FRAME_PARITY_ODD; + else + r |= USART_FRAME_PARITY_EVEN; + } else { + r |= USART_FRAME_PARITY_NONE; + } + + if (c_cflag & CSTOPB) + r |= USART_FRAME_STOPBITS_TWO; + else + r |= USART_FRAME_STOPBITS_ONE; + + regs->FRAME = r; + + regs->CTRLX = (c_cflag & CRTSCTS) ? USART_CTRLX_CTSEN : 0; + + regs->TIMING = ctx->timing; + + regs->CMD = USART_CMD_TXEN | + ((c_cflag & CREAD) ? USART_CMD_RXEN : USART_CMD_RXDIS); + +} + +static bool usart_set_attributes( + rtems_termios_device_context *base, + const struct termios *term +) +{ + attribs_init((struct usart_context_s *) base, + rtems_termios_baud_to_number(term->c_ospeed), + term->c_cflag); + + return true; +} + +static void pins_init(struct usart_context_s *ctx) +{ + USART_TypeDef *regs = ctx->regs; + rtems_interrupt_level level; + uint32_t r; + + rtems_interrupt_disable(level); + CMU->HFPERCLKEN0 |= ctx->hfperclken0_mask; + rtems_interrupt_enable(level); + + regs->IEN = 0; + regs->CTRL = USART_CTRL_TXBIL | USART_CTRL_OVS_X16 | ctx->ctrl; + regs->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX | + USART_CMD_RXDIS | USART_CMD_TXDIS; + + regs->ROUTELOC0 = ((ctx->tx_pin_loc << _USART_ROUTELOC0_TXLOC_SHIFT) & + _USART_ROUTELOC0_TXLOC_MASK) | + ((ctx->rx_pin_loc << _USART_ROUTELOC0_RXLOC_SHIFT) & + _USART_ROUTELOC0_RXLOC_MASK); + regs->ROUTELOC1 = ((ctx->cts_pin_loc << _USART_ROUTELOC1_CTSLOC_SHIFT) & + _USART_ROUTELOC1_CTSLOC_MASK) | + ((ctx->rts_pin_loc << _USART_ROUTELOC1_RTSLOC_SHIFT) & + _USART_ROUTELOC1_RTSLOC_MASK); + + r = 0; + if (ctx->tx_pin_loc >= 0) { + efm32gg11_gpio_clear_set(ctx->tx_port, 0, 1 << ctx->tx_pin); + efm32gg11_gpio_mode(ctx->tx_port, ctx->tx_pin, + GPIO_P_MODEL_MODE0_PUSHPULL); + r |= USART_ROUTEPEN_TXPEN; + } + if (ctx->rx_pin_loc >= 0) { + efm32gg11_gpio_clear_set(ctx->rx_port, 0, 1 << ctx->rx_pin); + efm32gg11_gpio_mode(ctx->rx_port, ctx->rx_pin, + GPIO_P_MODEL_MODE0_INPUTPULL); + r |= USART_ROUTEPEN_RXPEN; + } + if (ctx->cts_pin_loc >= 0) { + efm32gg11_gpio_clear_set(ctx->cts_port, 0, 1 << ctx->cts_pin); + efm32gg11_gpio_mode(ctx->cts_port, ctx->cts_pin, + GPIO_P_MODEL_MODE0_INPUTPULL); + r |= USART_ROUTEPEN_CTSPEN; + } + if (ctx->rts_pin_loc >= 0) { + efm32gg11_gpio_clear_set(ctx->rts_port, 0, 1 << ctx->rts_pin); + efm32gg11_gpio_mode(ctx->rts_port, ctx->rts_pin, + GPIO_P_MODEL_MODE0_PUSHPULL); + r |= USART_ROUTEPEN_RTSPEN; + } + if (ctx->cs_pin_loc >= 0) { + if (ctx->ctrl & USART_CTRL_CSINV) + efm32gg11_gpio_clear_set(ctx->cs_port, 1 << ctx->cs_pin, 0); + else + efm32gg11_gpio_clear_set(ctx->cs_port, 0, 1 << ctx->cs_pin); + efm32gg11_gpio_mode(ctx->cs_port, ctx->cs_pin, + GPIO_P_MODEL_MODE0_PUSHPULL); + r |= USART_ROUTEPEN_CSPEN; + } + regs->ROUTEPEN = r; + +#if EFM32GG11_CONSOLE_VCOM_ENABLE + if (ctx == &usart_instances[0]) { + /* connect usart to onboard segger */ + efm32gg11_gpio_clear_set(4, 0, (1 << 1)); + efm32gg11_gpio_mode(4, 1, GPIO_P_MODEL_MODE0_PUSHPULL); + } +#endif +} + +static bool usart_first_open( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + struct termios *term, + rtems_libio_open_close_args_t *args +) +{ + (void) args; + struct usart_context_s *ctx = (struct usart_context_s *) base; + USART_TypeDef *regs = ctx->regs; + + pins_init(ctx); + + rtems_termios_set_best_baud(term, BSP_CONSOLE_BAUD); + usart_set_attributes(base, term); + +#ifdef BSP_CONSOLE_USE_INTERRUPTS + rtems_interrupt_handler_install(ctx->rx_irq, "USART", + RTEMS_INTERRUPT_UNIQUE, + usart_rx_interrupt, tty); + rtems_interrupt_handler_install(ctx->tx_irq, "USART", + RTEMS_INTERRUPT_UNIQUE, + usart_tx_interrupt, tty); + regs->IEN |= USART_IEN_RXDATAV; +#else + (void) regs; + (void) tty; +#endif + + return true; +} + +static void usart_last_close( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + rtems_libio_open_close_args_t *args +) +{ + (void) args; + struct usart_context_s *ctx = (struct usart_context_s *) base; + USART_TypeDef *regs = ctx->regs; + +#ifdef BSP_CONSOLE_USE_INTERRUPTS + regs->IEN = 0; + __DSB(); + rtems_interrupt_handler_remove(ctx->tx_irq, usart_tx_interrupt, tty); + rtems_interrupt_handler_remove(ctx->rx_irq, usart_rx_interrupt, tty); +#else + (void) tty; + (void) regs; +#endif +} + +static void usart_write( + rtems_termios_device_context *base, + const char *buf, + size_t len) +{ + struct usart_context_s *ctx = (struct usart_context_s *) base; + USART_TypeDef *regs = ctx->regs; + +#ifdef BSP_CONSOLE_USE_INTERRUPTS + if (len > 0) { + ctx->transmitting = true; + regs->TXDATA = buf[0] & 0xff; + regs->IEN |= USART_IEN_TXBL; + } else { + ctx->transmitting = false; + regs->IEN &= ~USART_IEN_TXBL; + } + __DSB(); +#else + while (len--) { + while ((regs->STATUS & USART_STATUS_TXBL) == 0) + ; + regs->TXDATA = *buf++ & 0xff; + } +#endif +} + +#ifndef BSP_CONSOLE_USE_INTERRUPTS +static int usart_read(rtems_termios_device_context *base) +{ + struct usart_context_s *ctx = (struct usart_context_s *) base; + USART_TypeDef *regs = ctx->regs; + int data; + + if (regs->STATUS & USART_STATUS_RXDATAV) + data = regs->RXDATA; + else + data = -1; + + return data; +} +#endif + +static const rtems_termios_device_handler usart_handler = { + .first_open = usart_first_open, + .last_close = usart_last_close, + .write = usart_write, + .set_attributes = usart_set_attributes, +#ifdef BSP_CONSOLE_USE_INTERRUPTS + .mode = TERMIOS_IRQ_DRIVEN, +#else + .poll_read = usart_read, + .mode = TERMIOS_POLLED +#endif +}; + + +rtems_status_code console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ + size_t i; + (void) major; + (void) minor; + (void) arg; + + rtems_termios_initialize(); + + for (i = 0; i < RTEMS_ARRAY_SIZE(usart_instances); i++) { + rtems_termios_device_install(usart_instances[i].name, &usart_handler, + NULL, &usart_instances[i].base); + } + + return RTEMS_SUCCESSFUL; +} + + +static void output_char(char c) +{ + USART_TypeDef *regs = usart_instances[0].regs; + + while ((regs->STATUS & USART_STATUS_TXBL) == 0) + ; + regs->TXDATA = (uint32_t) c & 0xff; +} + +static void debug_console_init(void) +{ + if (BSP_output_char != output_char) { + pins_init(&usart_instances[0]); + attribs_init(&usart_instances[0], BSP_CONSOLE_BAUD, CS8 | CREAD); + BSP_output_char = output_char; + } +} + +static void output_char_early(char c) +{ + debug_console_init(); + output_char(c); +} + +BSP_output_char_function_type BSP_output_char = output_char_early; + +BSP_polling_getchar_function_type BSP_poll_char = NULL; + +RTEMS_SYSINIT_ITEM( + debug_console_init, + RTEMS_SYSINIT_BSP_START, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/bsps/arm/efm32gg11/dma/efm32gg11_dma.c b/bsps/arm/efm32gg11/dma/efm32gg11_dma.c new file mode 100644 index 0000000000..abce19c560 --- /dev/null +++ b/bsps/arm/efm32gg11/dma/efm32gg11_dma.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 LDMA Support + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + + +static struct dma_context_s { + struct { + void (*cb)(void *); + void *arg; + } ch[DMA_CHAN_COUNT]; +} dma_context; + + +static void dma_interrupt(void *arg) +{ + uint32_t iflags; + uint32_t mask; + int i; + + (void) arg; + iflags = LDMA->IF & LDMA->IEN; + LDMA->IFC = iflags; + mask = (iflags & _LDMA_IEN_DONE_MASK) >> _LDMA_IEN_DONE_SHIFT; + i = 0; + for (i = 0; mask && i < DMA_CHAN_COUNT; mask >>= 1, i++) { + if ((mask & 1) && dma_context.ch[i].cb) + dma_context.ch[i].cb(dma_context.ch[i].arg); + } +} + +void efm32gg11_dma_register(unsigned int channel, + void (*done_int)(void *), void *arg) +{ + if (channel < DMA_CHAN_COUNT) { + dma_context.ch[channel].arg = arg; + dma_context.ch[channel].cb = done_int; + } +} + +void efm32gg11_dma_int_enable(unsigned int channel, bool enable) +{ + rtems_interrupt_level level; + uint32_t mask; + + if (channel < DMA_CHAN_COUNT) { + mask = (uint32_t) 1 << (channel + _LDMA_IEN_DONE_SHIFT); + rtems_interrupt_disable(level); + if (enable) + LDMA->IEN |= mask; + else + LDMA->IEN &= ~mask; + __DSB(); + rtems_interrupt_enable(level); + } +} + +static void efm32gg11_dma_init(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_LDMA; + rtems_interrupt_enable(level); + + rtems_interrupt_handler_install(LDMA_IRQn, "DMA", + RTEMS_INTERRUPT_UNIQUE, + dma_interrupt, NULL); +} + +RTEMS_SYSINIT_ITEM( + efm32gg11_dma_init, + RTEMS_SYSINIT_DEVICE_DRIVERS, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/bsps/arm/efm32gg11/gpio/efm32gg11_gpio.c b/bsps/arm/efm32gg11/gpio/efm32gg11_gpio.c new file mode 100644 index 0000000000..e4ccb06bb6 --- /dev/null +++ b/bsps/arm/efm32gg11/gpio/efm32gg11_gpio.c @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 GPIO Support + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + + +static struct { + struct { + void (*cb)(void *); + void *arg; + } isr[32]; +} gpio_context; + + +static void gpio_interrupt(void *arg) +{ + bool odd = (bool) arg; + uint32_t mask; + int int_number; + + mask = odd ? 0xaaaaaaaa : 0x55555555; + mask &= GPIO->IF; + mask &= GPIO->IEN; + GPIO->IFC = mask; + __DSB(); + if (odd) { + int_number = 1; + mask >>= 1; + } else { + int_number = 0; + } + while (mask) { + if ((mask & 1) && gpio_context.isr[int_number].cb) + gpio_context.isr[int_number].cb(gpio_context.isr[int_number].arg); + int_number += 2; + mask >>= 2; + } +} + +void efm32gg11_gpio_init_0(void) +{ + CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO; +} + +void efm32gg11_gpio_init(void) +{ + rtems_interrupt_handler_install(GPIO_EVEN_IRQn, "GPIO_EVEN", + RTEMS_INTERRUPT_UNIQUE, + gpio_interrupt, (void *) false); + rtems_interrupt_handler_install(GPIO_ODD_IRQn, "GPIO_ODD", + RTEMS_INTERRUPT_UNIQUE, + gpio_interrupt, (void *) true); +} + +int efm32gg11_gpio_int_register(uint8_t port, uint8_t pin, + void (*cb)(void *), void *arg) +{ + rtems_interrupt_level level; + uint8_t shift; + int group; + uint32_t r; + int which; + int i; + + which = -1; + if (port < sizeof(GPIO->P) / sizeof(GPIO->P[0]) && pin < 16) { + group = pin / 4; + for (i = group * 4; i < group * 4 + 4 && which < 0; i++) { + rtems_interrupt_disable(level); + if (gpio_context.isr[i].cb == NULL) { + gpio_context.isr[i].arg = arg; + gpio_context.isr[i].cb = cb; + if (i >= 8) { + shift = (i - 8) * _GPIO_EXTIPSELH_EXTIPSEL9_SHIFT; + r = GPIO->EXTIPSELH; + r &= ~(_GPIO_EXTIPSELH_EXTIPSEL8_MASK << shift); + r |= (uint32_t) port << shift; + GPIO->EXTIPSELH = r; + + shift = (i - 8) * _GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT; + r = GPIO->EXTIPINSELH; + r &= ~(_GPIO_EXTIPINSELH_EXTIPINSEL8_MASK << shift); + r |= (uint32_t) (pin & 0x03) << shift; + GPIO->EXTIPINSELH = r; + } else { + shift = i * _GPIO_EXTIPSELL_EXTIPSEL1_SHIFT; + r = GPIO->EXTIPSELL; + r &= ~(_GPIO_EXTIPSELL_EXTIPSEL0_MASK << shift); + r |= (uint32_t) port << shift; + GPIO->EXTIPSELL = r; + + shift = i * _GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT; + r = GPIO->EXTIPINSELL; + r &= ~(_GPIO_EXTIPINSELL_EXTIPINSEL0_MASK << shift); + r |= (uint32_t) (pin & 0x03) << shift; + GPIO->EXTIPINSELH = r; + } + which = i; + } + rtems_interrupt_enable(level); + } + } + + return which; +} + +void efm32gg11_gpio_wake_pin_int_register(unsigned int which, + void (*cb)(void *), void *arg) +{ + + if (which >= 16 && which < 32) { + gpio_context.isr[which].arg = arg; + gpio_context.isr[which].cb = cb; + } +} + +void efm32gg11_gpio_int_mode(unsigned int which, bool rising, bool falling) +{ + rtems_interrupt_level level; + uint32_t mask; + + if (which < 16) { + mask = 1 << which; + rtems_interrupt_disable(level); + if (rising) + GPIO->EXTIRISE |= mask; + else + GPIO->EXTIRISE &= ~mask; + if (falling) + GPIO->EXTIFALL |= mask; + else + GPIO->EXTIFALL &= ~mask; + rtems_interrupt_enable(level); + } +} + +void efm32gg11_gpio_wake_pin_level(unsigned int which, bool high) +{ + rtems_interrupt_level level; + uint32_t mask; + + if (which >= 16 && which < 32) { + mask = 1 << which; + rtems_interrupt_disable(level); + if (high) + GPIO->EXTILEVEL |= mask; + else + GPIO->EXTILEVEL &= ~mask; + rtems_interrupt_enable(level); + } +} + +void efm32gg11_gpio_int_enable(unsigned int which, bool enable) +{ + rtems_interrupt_level level; + uint32_t mask; + + if (which < 32) { + mask = 1 << which; + rtems_interrupt_disable(level); + if (enable) + GPIO->IEN |= mask; + else + GPIO->IEN &= ~mask; + rtems_interrupt_enable(level); + } +} + +void efm32gg11_gpio_mode(uint8_t port, uint8_t pin, uint8_t mode) +{ + rtems_interrupt_level level; + uint32_t r; + bool high; + uint8_t shift; + + if (port < sizeof(GPIO->P) / sizeof(GPIO->P[0]) && + pin < 16 && + mode <= _GPIO_P_MODEL_MODE0_MASK) { + high = pin >= 8; + shift = (high ? pin - 8 : pin) * _GPIO_P_MODEL_MODE1_SHIFT; + rtems_interrupt_disable(level); + r = high ? GPIO->P[port].MODEH : GPIO->P[port].MODEL; + r &= ~(_GPIO_P_MODEL_MODE0_MASK << shift); + r |= (uint32_t) mode << shift; + if (high) + GPIO->P[port].MODEH = r; + else + GPIO->P[port].MODEL = r; + rtems_interrupt_enable(level); + } +} + +void efm32gg11_gpio_clear_set(uint8_t port, uint16_t clear, uint16_t set) +{ + rtems_interrupt_level level; + uint16_t r; + + if (port < sizeof(GPIO->P) / sizeof(GPIO->P[0])) { + rtems_interrupt_disable(level); + r = GPIO->P[port].DOUT; + r &= ~(uint32_t) clear; + r |= set; + GPIO->P[port].DOUT = r; + rtems_interrupt_enable(level); + } +} diff --git a/bsps/arm/efm32gg11/i2c/i2c.c b/bsps/arm/efm32gg11/i2c/i2c.c new file mode 100644 index 0000000000..5b304b49ca --- /dev/null +++ b/bsps/arm/efm32gg11/i2c/i2c.c @@ -0,0 +1,419 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 I2C Driver + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#define PASTE2(a,b) a ## b +#define PASTE3(a,b,c) a ## b ## c +#define PASTE4(a,b,c,d) a ## b ## c ## d + +#define REGS(i) PASTE2(I2C, i) +#define IRQN(i) PASTE3(I2C, i, _IRQn) +#define SCL_PORT(i, l) PASTE3(AF_I2C, i, _SCL_PORT)(l) +#define SCL_PIN(i, l) PASTE3(AF_I2C, i, _SCL_PIN)(l) +#define SDA_PORT(i, l) PASTE3(AF_I2C, i, _SDA_PORT)(l) +#define SDA_PIN(i, l) PASTE3(AF_I2C, i, _SDA_PIN)(l) +#define HFPERCLKEN0_MASK(i) PASTE2(CMU_HFPERCLKEN0_I2C, i) + + +static struct i2c_context_s { + i2c_bus bus; /* must be first */ + const char *name; + i2c_msg *msgs; + uint32_t msg_count; + uint8_t *buf_ptr; + uint16_t buf_remaining; + bool earlyStop; + int result; + rtems_binary_semaphore sem; + unsigned long clock; + I2C_TypeDef *regs; + rtems_vector_number irq; + int scl_pin_loc; + int scl_port; + int scl_pin; + int sda_pin_loc; + int sda_port; + int sda_pin; + uint32_t hfperclken0_mask; +} i2c_instances[] = { +#if defined(EFM32GG11_I2C_0_INDEX) && EFM32GG11_I2C_0_INDEX >= 0 + { + .name = "/dev/i2c-0", + .msgs = NULL, + .earlyStop = false, + .sem = RTEMS_BINARY_SEMAPHORE_INITIALIZER("i2c0"), + .clock = I2C_BUS_CLOCK_DEFAULT, + .regs = REGS(EFM32GG11_I2C_0_INDEX), + .irq = IRQN(EFM32GG11_I2C_0_INDEX), + .scl_pin_loc = EFM32GG11_I2C_0_SCL_LOC, + .scl_port = SCL_PORT(EFM32GG11_I2C_0_INDEX, EFM32GG11_I2C_0_SCL_LOC), + .scl_pin = SCL_PIN(EFM32GG11_I2C_0_INDEX, EFM32GG11_I2C_0_SCL_LOC), + .sda_pin_loc = EFM32GG11_I2C_0_SDA_LOC, + .sda_port = SDA_PORT(EFM32GG11_I2C_0_INDEX, EFM32GG11_I2C_0_SDA_LOC), + .sda_pin = SDA_PIN(EFM32GG11_I2C_0_INDEX, EFM32GG11_I2C_0_SDA_LOC), + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_I2C_0_INDEX) + }, +#endif +#if defined(EFM32GG11_I2C_1_INDEX) && EFM32GG11_I2C_1_INDEX >= 0 + { + .name = "/dev/i2c-1", + .msgs = NULL, + .earlyStop = false, + .sem = RTEMS_BINARY_SEMAPHORE_INITIALIZER("i2c1"), + .clock = I2C_BUS_CLOCK_DEFAULT, + .regs = REGS(EFM32GG11_I2C_1_INDEX), + .irq = IRQN(EFM32GG11_I2C_1_INDEX), + .scl_pin_loc = EFM32GG11_I2C_1_SCL_LOC, + .scl_port = SCL_PORT(EFM32GG11_I2C_1_INDEX, EFM32GG11_I2C_1_SCL_LOC), + .scl_pin = SCL_PIN(EFM32GG11_I2C_1_INDEX, EFM32GG11_I2C_1_SCL_LOC), + .sda_pin_loc = EFM32GG11_I2C_1_SDA_LOC, + .sda_port = SDA_PORT(EFM32GG11_I2C_1_INDEX, EFM32GG11_I2C_1_SDA_LOC), + .sda_pin = SDA_PIN(EFM32GG11_I2C_1_INDEX, EFM32GG11_I2C_1_SDA_LOC), + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_I2C_1_INDEX) + }, +#endif +#if defined(EFM32GG11_I2C_2_INDEX) && EFM32GG11_I2C_2_INDEX >= 0 + { + .name = "/dev/i2c-2", + .msgs = NULL, + .earlyStop = false, + .sem = RTEMS_BINARY_SEMAPHORE_INITIALIZER("i2c2"), + .clock = I2C_BUS_CLOCK_DEFAULT, + .regs = REGS(EFM32GG11_I2C_2_INDEX), + .irq = IRQN(EFM32GG11_I2C_2_INDEX), + .scl_pin_loc = EFM32GG11_I2C_2_SCL_LOC, + .scl_port = SCL_PORT(EFM32GG11_I2C_2_INDEX, EFM32GG11_I2C_2_SCL_LOC), + .scl_pin = SCL_PIN(EFM32GG11_I2C_2_INDEX, EFM32GG11_I2C_2_SCL_LOC), + .sda_pin_loc = EFM32GG11_I2C_2_SDA_LOC, + .sda_port = SDA_PORT(EFM32GG11_I2C_2_INDEX, EFM32GG11_I2C_2_SDA_LOC), + .sda_pin = SDA_PIN(EFM32GG11_I2C_2_INDEX, EFM32GG11_I2C_2_SDA_LOC), + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_I2C_2_INDEX) + }, +#endif +}; + + +static void start(struct i2c_context_s *ctx, uint32_t extra_commands) +{ + I2C_TypeDef *regs = ctx->regs; + rtems_interrupt_level level; + uint32_t r; + + r = ctx->msgs->addr << 1; + if (ctx->msgs->flags & I2C_M_RD) + r |= 0x01; + r = (r << _I2C_TXDATA_TXDATA_SHIFT) & _I2C_TXDATA_TXDATA_MASK; + rtems_interrupt_disable(level); + regs->CMD = I2C_CMD_START | extra_commands; + regs->TXDATA = r; + rtems_interrupt_enable(level); +} + +static void continuation_buffer(struct i2c_context_s *ctx) { + + while (ctx->msg_count > 1 && !(ctx->msgs->flags & I2C_M_STOP) && + (ctx->msgs[1].flags & I2C_M_NOSTART) && ctx->buf_remaining == 0) { + ctx->msgs++; + ctx->msg_count--; + ctx->buf_ptr = ctx->msgs->buf; + ctx->buf_remaining = ctx->msgs->len; + } +} + +static void next_message(struct i2c_context_s *ctx) { + + while (ctx->msg_count) { + ctx->msgs++; + ctx->msg_count--; + if (ctx->msgs->len || + (ctx->msgs->flags & I2C_M_STOP) || !(ctx->msgs->flags & I2C_M_NOSTART)) + break; + } + if (ctx->msg_count) { + ctx->buf_ptr = ctx->msgs->buf; + ctx->buf_remaining = ctx->msgs->len; + } else { + ctx->buf_remaining = 0; + } +} + +static void i2c_interrupt(void *arg) +{ + i2c_bus *bus = (i2c_bus *) arg; + struct i2c_context_s *ctx = (struct i2c_context_s *) bus; + I2C_TypeDef *regs = ctx->regs; + uint32_t iflags; + uint32_t r; + uint8_t c; + + iflags = regs->IF; + regs->IFC = iflags & (I2C_IF_CLERR | I2C_IF_RXFULL | I2C_IF_BUSERR | + I2C_IF_ARBLOST | I2C_IF_MSTOP | + I2C_IF_NACK | I2C_IF_ACK); + + if (iflags & (I2C_IF_RXDATAV | I2C_IF_RXFULL)) + c = regs->RXDATA; + + if (ctx->earlyStop) { + if (iflags & I2C_IF_MSTOP) { + ctx->result = -EIO; + ctx->earlyStop = false; + rtems_binary_semaphore_post(&ctx->sem); + } + } else if (iflags & (I2C_IF_ARBLOST | I2C_IF_CLERR | I2C_IF_BUSERR)) { + regs->CMD = I2C_CMD_ABORT; + ctx->result = -EIO; + rtems_binary_semaphore_post(&ctx->sem); + } else { + if (iflags & I2C_IF_RXDATAV) { + if (ctx->buf_remaining == 0) + continuation_buffer(ctx); + if (ctx->buf_remaining) { + *ctx->buf_ptr++ = c; + ctx->buf_remaining--; + if (ctx->buf_remaining == 0) + continuation_buffer(ctx); + } else { + /* it should be impossible to get here */ + } + if (ctx->buf_remaining) { + regs->CMD = I2C_CMD_ACK; + } else { + if (ctx->msg_count == 1 || (ctx->msgs->flags & I2C_M_STOP)) { + regs->CMD = I2C_CMD_NACK | I2C_CMD_STOP; + } else { + next_message(ctx); + start(ctx, I2C_CMD_NACK); + } + } + } + if ((iflags & I2C_IF_NACK) && + !(ctx->msgs->flags & I2C_M_IGNORE_NAK)) { + ctx->earlyStop = true; + regs->CMD = I2C_CMD_STOP; + } else if (iflags & (I2C_IF_ACK | I2C_IF_NACK)) { + if (ctx->buf_remaining == 0) + continuation_buffer(ctx); + if (ctx->buf_remaining == 0) { + if ((ctx->msgs->flags & I2C_M_STOP) || ctx->msg_count == 1) { + regs->CMD = I2C_CMD_STOP; + } else { + next_message(ctx); + start(ctx, 0); + } + } else if (!(ctx->msgs->flags & I2C_M_RD)) { + r = *ctx->buf_ptr++; + ctx->buf_remaining--; + r = (r << _I2C_TXDATA_TXDATA_SHIFT) & + _I2C_TXDATA_TXDATA_MASK; + regs->TXDATA = r; + } else { + /* address sent, transition to reading */ + if (iflags & I2C_IF_NACK) + regs->CMD = I2C_CMD_CONT; + } + } + if (iflags & I2C_IF_MSTOP) { + next_message(ctx); + if (ctx->msg_count == 0) { + ctx->result = 0; + rtems_binary_semaphore_post(&ctx->sem); + } else { + start(ctx, 0); + } + } + } +} + +#define NHIGH 4 +#define NLOW 4 + +static void clock_set(struct i2c_context_s *ctx) +{ + I2C_TypeDef *regs = ctx->regs; + uint32_t div; + + div = (efm32gg11_clock.hfpercclk - 8 * ctx->clock - 1) / + ((NHIGH + NLOW) * ctx->clock); + + regs->CLKDIV = div; +} + +static void i2c_init(struct i2c_context_s *ctx) +{ + I2C_TypeDef *regs = ctx->regs; + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + CMU->HFPERCLKEN0 |= ctx->hfperclken0_mask; + rtems_interrupt_enable(level); + + clock_set(ctx); + + regs->IEN = 0; +#if NHIGH != 4 || NLOW != 4 + /* should set CLHR based on these and only error out if they're an + unsupported combination */ +#error +#endif + regs->CTRL = + I2C_CTRL_CLTO_OFF | + I2C_CTRL_BITO_OFF | + I2C_CTRL_CLHR_STANDARD | + I2C_CTRL_TXBIL_EMPTY | + I2C_CTRL_EN; + regs->CMD = I2C_CMD_ABORT; + + regs->ROUTELOC0 = ((ctx->scl_pin_loc << _I2C_ROUTELOC0_SCLLOC_SHIFT) & + _I2C_ROUTELOC0_SCLLOC_MASK) | + ((ctx->sda_pin_loc << _I2C_ROUTELOC0_SDALOC_SHIFT) & + _I2C_ROUTELOC0_SDALOC_MASK); + + efm32gg11_gpio_clear_set(ctx->scl_port, 0, 1 << ctx->scl_pin); + efm32gg11_gpio_mode(ctx->scl_port, ctx->scl_pin, + GPIO_P_MODEL_MODE0_WIREDAND); + efm32gg11_gpio_clear_set(ctx->sda_port, 0, 1 << ctx->sda_pin); + efm32gg11_gpio_mode(ctx->sda_port, ctx->sda_pin, + GPIO_P_MODEL_MODE0_WIREDAND); + regs->ROUTEPEN = I2C_ROUTEPEN_SCLPEN | I2C_ROUTEPEN_SDAPEN; + + regs->IEN = I2C_IEN_CLERR | I2C_IEN_RXFULL | I2C_IEN_BUSERR | + I2C_IEN_ARBLOST | I2C_IEN_MSTOP | + I2C_IEN_NACK | I2C_IEN_ACK | + I2C_IEN_RXDATAV; +} + +static int i2c_transfer(i2c_bus *bus, i2c_msg *msgs, uint32_t msg_count) +{ + struct i2c_context_s *ctx = (struct i2c_context_s *) bus; + uint16_t prev_flags; + uint16_t supported_flags; + uint32_t i; + int sc; + + /* Several of the additional flags could be supported, but I don't + need them and even if I were to write code to support them I wouldn't + have a quick and easy way to test. */ + supported_flags = I2C_M_RD | I2C_M_STOP | I2C_M_IGNORE_NAK; + prev_flags = msgs[0].flags; /* silence compiler warning */ + for (i = 0; i < msg_count; i++) { + if (msgs[i].flags & ~supported_flags) + return -EINVAL; + if (msgs[i].flags & I2C_M_NOSTART) { + if ((prev_flags & I2C_M_RD) != (msgs[i].flags & I2C_M_RD) || + (prev_flags & I2C_M_STOP)) + return -EINVAL; + } + prev_flags = msgs[i].flags; + supported_flags |= I2C_M_NOSTART; + } + ctx->msgs = msgs; + ctx->msg_count = msg_count; + ctx->buf_ptr = msgs->buf; + ctx->buf_remaining = msgs->len; + ctx->result = 0; + + rtems_binary_semaphore_try_wait(&ctx->sem); + start(ctx, 0); + + sc = rtems_binary_semaphore_wait_timed_ticks(&ctx->sem, bus->timeout); + if (sc) { + ctx->regs->CMD = I2C_CMD_ABORT; + sc = -ETIMEDOUT; + } + + if (sc == 0) + sc = ctx->result; + + return sc; +} + +static int i2c_set_clock(i2c_bus *bus, unsigned long clock) +{ + struct i2c_context_s *ctx = (struct i2c_context_s *) bus; + + ctx->clock = clock; + clock_set(ctx); + + return 0; +} + +static void i2c_destroy(i2c_bus *bus) +{ + struct i2c_context_s *ctx = (struct i2c_context_s *) bus; + rtems_interrupt_level level; + + ctx->regs->IEN = 0; + ctx->regs->CTRL = 0; + __DSB(); + rtems_interrupt_handler_remove(ctx->irq, i2c_interrupt, bus); + rtems_binary_semaphore_destroy(&ctx->sem); + + rtems_interrupt_disable(level); + CMU->HFPERCLKEN0 &= ~ctx->hfperclken0_mask; + rtems_interrupt_enable(level); +} + +int efm32gg11_i2c_register() +{ + rtems_status_code sc; + struct i2c_context_s *ctx; + size_t i; + + sc = RTEMS_SUCCESSFUL; + for (i = 0; i < RTEMS_ARRAY_SIZE(i2c_instances); i++) { + ctx = &i2c_instances[i]; + i2c_bus_init(&ctx->bus); + rtems_interrupt_handler_install(ctx->irq, "I2C", RTEMS_INTERRUPT_UNIQUE, + i2c_interrupt, &ctx->bus); + i2c_init(ctx); + ctx->bus.transfer = i2c_transfer; + ctx->bus.set_clock = i2c_set_clock; + ctx->bus.destroy = i2c_destroy; + + sc = i2c_bus_register(&ctx->bus, ctx->name); + } + + return sc; +} diff --git a/bsps/arm/efm32gg11/include/bsp.h b/bsps/arm/efm32gg11/include/bsp.h new file mode 100644 index 0000000000..9be67fd54c --- /dev/null +++ b/bsps/arm/efm32gg11/include/bsp.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief Global BSP definitions. + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_EFM32GG11_BSP_H +#define LIBBSP_ARM_EFM32GG11_BSP_H + +/** + * @defgroup RTEMSBSPsARMEFM32GG11 EFM32GG11 + * + * @ingroup RTEMSBSPsARM + * + * @brief EFM32GG11 Board Support Package. + * + * @{ + */ + +#include +#include + +#include + +#include "bsp/efm32gg11_clock.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BSP_FEATURE_IRQ_EXTENSION + +#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4) + +#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4) + +#define BSP_ARMV7M_SYSTICK_FREQUENCY (efm32gg11_clock.hfcoreclk) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +/** @} */ + + +#endif /* LIBBSP_ARM_EFM32GG11_BSP_H */ diff --git a/bsps/arm/efm32gg11/include/bsp/efm32gg11_clock.h b/bsps/arm/efm32gg11/include/bsp/efm32gg11_clock.h new file mode 100644 index 0000000000..8184224cdd --- /dev/null +++ b/bsps/arm/efm32gg11/include/bsp/efm32gg11_clock.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 Clock Configuration + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_EFM32GG11_CLOCK_H +#define LIBBSP_ARM_EFM32GG11_CLOCK_H + +#include + +extern struct efm32gg11_clock_s { + uint32_t hfclk; + uint32_t hfcoreclk; + uint32_t hfbusclk; + uint32_t hfperclk; + uint32_t hfperbclk; + uint32_t hfpercclk; + uint32_t hfexpclk; + uint16_t lfaclk; + uint16_t lfbclk; + uint16_t lfcclk; + uint16_t lfeclk; +} efm32gg11_clock; + +void efm32gg11_clock_init(void); + +#endif /* LIBBSP_ARM_EFM32GG11_CLOCK_H */ diff --git a/bsps/arm/efm32gg11/include/bsp/efm32gg11_dma.h b/bsps/arm/efm32gg11/include/bsp/efm32gg11_dma.h new file mode 100644 index 0000000000..2809656fe7 --- /dev/null +++ b/bsps/arm/efm32gg11/include/bsp/efm32gg11_dma.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 LDMA Support + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_EFM32GG11_DMA_H +#define LIBBSP_ARM_EFM32GG11_DMA_H + +#include + + +void efm32gg11_dma_register(unsigned int channel, + void (*done_int)(void *), void *arg); + +void efm32gg11_dma_int_enable(unsigned int channel, bool enable); + + +#endif /* LIBBSP_ARM_EFM32GG11_DMA_H */ diff --git a/bsps/arm/efm32gg11/include/bsp/efm32gg11_gpio.h b/bsps/arm/efm32gg11/include/bsp/efm32gg11_gpio.h new file mode 100644 index 0000000000..a084113d28 --- /dev/null +++ b/bsps/arm/efm32gg11/include/bsp/efm32gg11_gpio.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 GPIO Support + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_EFM32GG11_GPIO_H +#define LIBBSP_ARM_EFM32GG11_GPIO_H + +#include + +void efm32gg11_gpio_init_0(void); +void efm32gg11_gpio_init(void); + +/* returns a non-negative number on success indicating the interrupt + number assigned, or a negative number on failure. */ +int efm32gg11_gpio_int_register(uint8_t port, uint8_t pin, + void (*cb)(void *), void *arg); + +/* which is the bit number from the em4 wakeup pin registers, range 16 - 31 */ +void efm32gg11_gpio_wake_pin_int_register(unsigned int which, + void (*cb)(void *), void *arg); + +/* which is the interrupt number provided by efm32gg11_gpio_int_register() */ +void efm32gg11_gpio_int_mode(unsigned int which, bool rising, bool falling); + +/* which is the bit number from the em4 wakeup pin registers, range 16 - 31 */ +void efm32gg11_gpio_wake_pin_level(unsigned int which, bool high); + +/* which is the interrupt number provided by efm32gg11_gpio_int_register() */ +void efm32gg11_gpio_int_enable(unsigned int which, bool enable); + +void efm32gg11_gpio_mode(uint8_t port, uint8_t pin, uint8_t mode); + +void efm32gg11_gpio_clear_set(uint8_t port, uint16_t clear, uint16_t set); + +#endif /* LIBBSP_ARM_EFM32GG11_GPIO_H */ diff --git a/bsps/arm/efm32gg11/include/bsp/i2c.h b/bsps/arm/efm32gg11/include/bsp/i2c.h new file mode 100644 index 0000000000..24976582b2 --- /dev/null +++ b/bsps/arm/efm32gg11/include/bsp/i2c.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 I2C Driver + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_EFM32GG11_I2C_H +#define LIBBSP_ARM_EFM32GG11_I2C_H + +#include + +int efm32gg11_i2c_register(void); + +#endif /* LIBBSP_ARM_EFM32GG11_I2C_H */ diff --git a/bsps/arm/efm32gg11/include/bsp/irq.h b/bsps/arm/efm32gg11/include/bsp/irq.h new file mode 100644 index 0000000000..21aa40b0cf --- /dev/null +++ b/bsps/arm/efm32gg11/include/bsp/irq.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 Interrupt Config + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_EFM32GG11_IRQ_H +#define LIBBSP_ARM_EFM32GG11_IRQ_H + +#include + +#ifndef ASM + #include + #include + #include +#endif + +#define BSP_INTERRUPT_VECTOR_COUNT 68 + +#endif /* LIBBSP_ARM_EFM32GG11_IRQ_H */ diff --git a/bsps/arm/efm32gg11/include/bsp/processor.h b/bsps/arm/efm32gg11/include/bsp/processor.h new file mode 100644 index 0000000000..d8b8facb69 --- /dev/null +++ b/bsps/arm/efm32gg11/include/bsp/processor.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 Processor Definitions + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_EFM32GG11_PROCESSOR_H +#define LIBBSP_ARM_EFM32GG11_PROCESSOR_H + +#include + +#define EFM32GG11B110 0x11b110 +#define EFM32GG11B120 0x11b120 +#define EFM32GG11B310 0x11b310 +#define EFM32GG11B320 0x11b320 +#define EFM32GG11B420 0x11b420 +#define EFM32GG11B510 0x11b510 +#define EFM32GG11B520 0x11b520 +#define EFM32GG11B820 0x11b820 +#define EFM32GG11B840 0x11b840 + + +#if defined(EFM32GG11_DEVICE) + +#if EFM32GG11_DEVICE == EFM32GG11B110 +#include "efm32gg11b110f2048gm64.h" +#elif EFM32GG11_DEVICE == EFM32GG11B120 +#include "efm32gg11b120f2048gm64.h" +#elif EFM32GG11_DEVICE == EFM32GG11B310 +#include "efm32gg11b310f2048gl112.h" +#elif EFM32GG11_DEVICE == EFM32GG11B320 +#include "efm32gg11b320f2048gl112.h" +#elif EFM32GG11_DEVICE == EFM32GG11B420 +#include "efm32gg11b420f2048gl120.h" +#elif EFM32GG11_DEVICE == EFM32GG11B510 +#include "efm32gg11b510f2048gl120.h" +#elif EFM32GG11_DEVICE == EFM32GG11B520 +#include "efm32gg11b520f2048gl120.h" +#elif EFM32GG11_DEVICE == EFM32GG11B820 +#include "efm32gg11b820f2048gl192.h" +#elif EFM32GG11_DEVICE == EFM32GG11B840 +#include "efm32gg11b840f1024gl192.h" +#else +#error unknown device +#endif + +#else +#error EFM32GG11_DEVICE not defined +#endif + +#endif /* LIBBSP_ARM_EFM32GG11_PROCESSOR_H */ diff --git a/bsps/arm/efm32gg11/include/bsp/spi.h b/bsps/arm/efm32gg11/include/bsp/spi.h new file mode 100644 index 0000000000..addbef893d --- /dev/null +++ b/bsps/arm/efm32gg11/include/bsp/spi.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 SPI Driver + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_ARM_EFM32GG11_SPI_H +#define LIBBSP_ARM_EFM32GG11_SPI_H + +#include + +int efm32gg11_spi_register(void); + +#endif /* LIBBSP_ARM_EFM32GG11_SPI_H */ diff --git a/bsps/arm/efm32gg11/include/tm27.h b/bsps/arm/efm32gg11/include/tm27.h new file mode 100644 index 0000000000..28530645ab --- /dev/null +++ b/bsps/arm/efm32gg11/include/tm27.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief This header file includes the generic tm27 support implementation. + */ + +/* + * Copyright (C) 2017 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include diff --git a/bsps/arm/efm32gg11/spi/spi.c b/bsps/arm/efm32gg11/spi/spi.c new file mode 100644 index 0000000000..8e0ec049e8 --- /dev/null +++ b/bsps/arm/efm32gg11/spi/spi.c @@ -0,0 +1,560 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 SPI Driver + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define PASTE2(a,b) a ## b +#define PASTE3(a,b,c) a ## b ## c +#define PASTE4(a,b,c,d) a ## b ## c ## d + +#define REGS(i) PASTE2(USART, i) +#define TX_DMA_REQ(i) PASTE3(DMAREQ_USART, i, _TXBL) +#define RX_DMA_REQ(i) PASTE3(DMAREQ_USART, i, _RXDATAV) +#define CLK_PORT(i, l) PASTE3(AF_USART, i, _CLK_PORT)(l) +#define CLK_PIN(i, l) PASTE3(AF_USART, i, _CLK_PIN)(l) +#define TX_PORT(i, l) PASTE3(AF_USART, i, _TX_PORT)(l) +#define TX_PIN(i, l) PASTE3(AF_USART, i, _TX_PIN)(l) +#define RX_PORT(i, l) PASTE3(AF_USART, i, _RX_PORT)(l) +#define RX_PIN(i, l) PASTE3(AF_USART, i, _RX_PIN)(l) +#define HFPERCLKEN0_MASK(i) PASTE2(CMU_HFPERCLKEN0_USART, i) + + +struct spi_cs_pin_s { + uint8_t port; + uint8_t pin; + uint8_t high_true; + uint8_t cs_setup_bits; +}; + +#if defined(EFM32GG11_SPI_0_INDEX) && EFM32GG11_SPI_0_INDEX >= 0 +static struct spi_cs_pin_s spi_0_cs_pins[] = EFM32GG11_SPI_0_CS_PINS; +#endif +#if defined(EFM32GG11_SPI_1_INDEX) && EFM32GG11_SPI_1_INDEX >= 0 +static struct spi_cs_pin_s spi_1_cs_pins[] = EFM32GG11_SPI_1_CS_PINS; +#endif +#if defined(EFM32GG11_SPI_2_INDEX) && EFM32GG11_SPI_2_INDEX >= 0 +static struct spi_cs_pin_s spi_2_cs_pins[] = EFM32GG11_SPI_2_CS_PINS; +#endif +#if defined(EFM32GG11_SPI_3_INDEX) && EFM32GG11_SPI_3_INDEX >= 0 +static struct spi_cs_pin_s spi_3_cs_pins[] = EFM32GG11_SPI_3_CS_PINS; +#endif +#if defined(EFM32GG11_SPI_4_INDEX) && EFM32GG11_SPI_4_INDEX >= 0 +static struct spi_cs_pin_s spi_4_cs_pins[] = EFM32GG11_SPI_4_CS_PINS; +#endif +#if defined(EFM32GG11_SPI_5_INDEX) && EFM32GG11_SPI_5_INDEX >= 0 +static struct spi_cs_pin_s spi_5_cs_pins[] = EFM32GG11_SPI_5_CS_PINS; +#endif + +static struct spi_context_s { + spi_bus bus; /* must be first */ + const char *name; + const uint8_t *tx_ptr; + uint8_t *rx_ptr; + uint32_t xfer_count; + rtems_binary_semaphore sem; + USART_TypeDef *regs; + int tx_dma_channel; + int rx_dma_channel; + uint32_t tx_dma_req; + uint32_t rx_dma_req; + struct spi_cs_pin_s *cs_pins; + int cs_pin_count; + int clk_pin_loc; + int clk_port; + int clk_pin; + int tx_pin_loc; + int tx_port; + int tx_pin; + int rx_pin_loc; + int rx_port; + int rx_pin; + uint32_t hfperclken0_mask; + uint32_t routeloc0; + uint32_t routepen; + uint32_t tx_dummy; + uint32_t rx_dummy; +} spi_instances[] = { +#if defined(EFM32GG11_SPI_0_INDEX) && EFM32GG11_SPI_0_INDEX >= 0 + { + .name = "/dev/spi-0", + .sem = RTEMS_BINARY_SEMAPHORE_INITIALIZER("spi0"), + .regs = REGS(EFM32GG11_SPI_0_INDEX), + .tx_dma_channel = EFM32GG11_SPI_0_TX_DMA_CHANNEL, + .rx_dma_channel = EFM32GG11_SPI_0_RX_DMA_CHANNEL, + .tx_dma_req = TX_DMA_REQ(EFM32GG11_SPI_0_INDEX), + .rx_dma_req = RX_DMA_REQ(EFM32GG11_SPI_0_INDEX), + .cs_pins = spi_0_cs_pins, + .cs_pin_count = sizeof(spi_0_cs_pins) / sizeof(spi_0_cs_pins[0]), + .clk_pin_loc = EFM32GG11_SPI_0_CLK_LOC, + .clk_port = CLK_PORT(EFM32GG11_SPI_0_INDEX, EFM32GG11_SPI_0_CLK_LOC), + .clk_pin = CLK_PIN(EFM32GG11_SPI_0_INDEX, EFM32GG11_SPI_0_CLK_LOC), + .tx_pin_loc = EFM32GG11_SPI_0_TX_LOC, + .tx_port = TX_PORT(EFM32GG11_SPI_0_INDEX, EFM32GG11_SPI_0_TX_LOC), + .tx_pin = TX_PIN(EFM32GG11_SPI_0_INDEX, EFM32GG11_SPI_0_TX_LOC), + .rx_pin_loc = EFM32GG11_SPI_0_RX_LOC, + .rx_port = RX_PORT(EFM32GG11_SPI_0_INDEX, EFM32GG11_SPI_0_RX_LOC), + .rx_pin = RX_PIN(EFM32GG11_SPI_0_INDEX, EFM32GG11_SPI_0_RX_LOC), + .hfperclken0_mask = HFPERCLKEN0_MASK(EFM32GG11_SPI_0_INDEX) + }, +#endif +}; + + +static void xfer_start(struct spi_context_s *ctx) +{ + uint32_t count; + int bytes_per_transfer; + uint32_t dma_ctrl_base; + + count = ctx->xfer_count; + if (count > (_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1) + count = (_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1; + ctx->xfer_count -= count; + + if (ctx->bus.bits_per_word > 8) { + bytes_per_transfer = 2; + dma_ctrl_base = LDMA_CH_CTRL_SIZE_HALFWORD; + LDMA->CH[ctx->rx_dma_channel].SRC = (uint32_t) &ctx->regs->RXDOUBLE; + LDMA->CH[ctx->tx_dma_channel].DST = (uint32_t) &ctx->regs->TXDOUBLE; + } else { + bytes_per_transfer = 1; + dma_ctrl_base = LDMA_CH_CTRL_SIZE_BYTE; + LDMA->CH[ctx->rx_dma_channel].SRC = (uint32_t) &ctx->regs->RXDATA; + LDMA->CH[ctx->tx_dma_channel].DST = (uint32_t) &ctx->regs->TXDATA; + } + + if (ctx->rx_ptr) { + LDMA->CH[ctx->rx_dma_channel].DST = (uint32_t) ctx->rx_ptr; + ctx->rx_ptr += bytes_per_transfer * count; + LDMA->CH[ctx->rx_dma_channel].CTRL = LDMA_CH_CTRL_DSTINC_ONE | + dma_ctrl_base | + LDMA_CH_CTRL_SRCINC_NONE | + LDMA_CH_CTRL_REQMODE_BLOCK | + LDMA_CH_CTRL_DONEIFSEN | + LDMA_CH_CTRL_BLOCKSIZE_UNIT1 | + ((count - 1) << + _LDMA_CH_CTRL_XFERCNT_SHIFT); + } else { + LDMA->CH[ctx->rx_dma_channel].DST = (uint32_t) &ctx->rx_dummy; + LDMA->CH[ctx->rx_dma_channel].CTRL = LDMA_CH_CTRL_DSTINC_NONE | + dma_ctrl_base | + LDMA_CH_CTRL_SRCINC_NONE | + LDMA_CH_CTRL_REQMODE_BLOCK | + LDMA_CH_CTRL_DONEIFSEN | + LDMA_CH_CTRL_BLOCKSIZE_UNIT1 | + ((count - 1) << + _LDMA_CH_CTRL_XFERCNT_SHIFT); + } + + if (ctx->tx_ptr) { + LDMA->CH[ctx->tx_dma_channel].SRC = (uint32_t) ctx->tx_ptr; + ctx->tx_ptr += bytes_per_transfer * count; + LDMA->CH[ctx->tx_dma_channel].CTRL = LDMA_CH_CTRL_DSTINC_NONE | + dma_ctrl_base | + LDMA_CH_CTRL_SRCINC_ONE | + LDMA_CH_CTRL_REQMODE_BLOCK | + LDMA_CH_CTRL_BLOCKSIZE_UNIT1 | + ((count - 1) << + _LDMA_CH_CTRL_XFERCNT_SHIFT); + } else { + LDMA->CH[ctx->tx_dma_channel].SRC = (uint32_t) &ctx->tx_dummy; + LDMA->CH[ctx->tx_dma_channel].CTRL = LDMA_CH_CTRL_DSTINC_NONE | + dma_ctrl_base | + LDMA_CH_CTRL_SRCINC_NONE | + LDMA_CH_CTRL_REQMODE_BLOCK | + LDMA_CH_CTRL_BLOCKSIZE_UNIT1 | + ((count - 1) << + _LDMA_CH_CTRL_XFERCNT_SHIFT); + } + /* bit set */ + ((LDMA_TypeDef *) (LDMA_BASE + 0x06000000))->CHEN = + 1 << (ctx->rx_dma_channel + _LDMA_CHEN_CHEN_SHIFT) | + 1 << (ctx->tx_dma_channel + _LDMA_CHEN_CHEN_SHIFT); +} + +static void rx_done_int(void *arg) +{ + struct spi_context_s *ctx = (struct spi_context_s *) arg; + + if (ctx->xfer_count) + xfer_start(ctx); + else + rtems_binary_semaphore_post(&ctx->sem); +} + +static void cs_control(struct spi_context_s *ctx, unsigned int cs, + bool assert) +{ + struct spi_cs_pin_s *pin; + uint16_t mask; + + if (cs < ctx->cs_pin_count) { + pin = &ctx->cs_pins[cs]; + mask = 1 << pin->pin; + if ((assert && pin->high_true) || (!assert && !pin->high_true)) + efm32gg11_gpio_clear_set(pin->port, 0, mask); + else + efm32gg11_gpio_clear_set(pin->port, mask, 0); + } +} + +static uint32_t clock_max(struct spi_context_s *ctx) +{ + + return ((ctx->regs == USART2) ? efm32gg11_clock.hfperbclk : + efm32gg11_clock.hfperclk) / 2; +} + +static void clock_set(struct spi_bus *bus) +{ + struct spi_context_s *ctx = (struct spi_context_s *) bus; + USART_TypeDef *regs = ctx->regs; + uint32_t r; + + r = (regs == USART2) ? efm32gg11_clock.hfperbclk : efm32gg11_clock.hfperclk; + /* There seems to be a discrepancy of a factor of 8 between rev 1.2 of the + EFM32 Giant Gecko 11 Family Reference Manual and reality. */ + r = (16 * r) / bus->speed_hz; + if (r > 32) + r -= 32; + else + r = 0; + + r <<= _USART_CLKDIV_DIV_SHIFT; + regs->CLKDIV = r; +} + +static void frame_set(struct spi_bus *bus) +{ + struct spi_context_s *ctx = (struct spi_context_s *) bus; + USART_TypeDef *regs = ctx->regs; + uint32_t r; + + r = regs->FRAME & ~_USART_FRAME_DATABITS_MASK; + switch (bus->bits_per_word) { + case 4: + r |= USART_FRAME_DATABITS_FOUR; + break; + case 5: + r |= USART_FRAME_DATABITS_FIVE; + break; + case 6: + r |= USART_FRAME_DATABITS_SIX; + break; + case 7: + r |= USART_FRAME_DATABITS_SEVEN; + break; + case 8: + r |= USART_FRAME_DATABITS_EIGHT; + break; + case 9: + r |= USART_FRAME_DATABITS_NINE; + break; + case 10: + r |= USART_FRAME_DATABITS_TEN; + break; + case 11: + r |= USART_FRAME_DATABITS_ELEVEN; + break; + case 12: + r |= USART_FRAME_DATABITS_TWELVE; + break; + case 13: + r |= USART_FRAME_DATABITS_THIRTEEN; + break; + case 14: + r |= USART_FRAME_DATABITS_FOURTEEN; + break; + case 15: + r |= USART_FRAME_DATABITS_FIFTEEN; + break; + case 16: + r |= USART_FRAME_DATABITS_SIXTEEN; + break; + default: + r |= USART_FRAME_DATABITS_EIGHT; + break; + } + regs->FRAME = r; +} + +static void mode_set(struct spi_bus *bus) +{ + struct spi_context_s *ctx = (struct spi_context_s *) bus; + USART_TypeDef *regs = ctx->regs; + uint32_t r; + + r = regs->CTRL; + r &= ~(USART_CTRL_MSBF | + USART_CTRL_CLKPHA | USART_CTRL_CLKPOL); + if (!bus->lsb_first) + r |= USART_CTRL_MSBF; + if (bus->mode & SPI_CPHA) + r |= USART_CTRL_CLKPHA; + if (bus->mode & SPI_CPOL) + r |= USART_CTRL_CLKPOL; + regs->CTRL = r; +} + +static int spi_setup(spi_bus *bus) +{ + struct spi_context_s *ctx = (struct spi_context_s *) bus; + int result; + + result = 0; + if ((bus->cs >= ctx->cs_pin_count && !(bus->mode & SPI_NO_CS)) || + bus->bits_per_word < 4 || bus->bits_per_word > 16) + result = -EINVAL; + + if (result == 0) { + clock_set(bus); + frame_set(bus); + mode_set(bus); + } + + return result; +} + +static int spi_transfer(spi_bus *bus, + const spi_ioc_transfer *msgs, + uint32_t msg_count) +{ + struct spi_context_s *ctx = (struct spi_context_s *) bus; + USART_TypeDef *regs = ctx->regs; + bool cs_asserted; + uint8_t setup; + int sc; + + sc = 0; + cs_asserted = false; + while (msg_count && sc == 0) { + bus->cs = msgs->cs; + bus->mode = msgs->mode; + bus->speed_hz = msgs->speed_hz; + bus->bits_per_word = msgs->bits_per_word; + bus->lsb_first = (msgs->mode & SPI_LSB_FIRST) ? true : false; + bus->delay_usecs = msgs->delay_usecs; + sc = spi_setup(bus); + + if (sc == 0) { + ctx->tx_ptr = msgs->tx_buf; + ctx->rx_ptr = msgs->rx_buf; + if (bus->bits_per_word > 8) + ctx->xfer_count = msgs->len / 2; + else + ctx->xfer_count = msgs->len; + + rtems_binary_semaphore_try_wait(&ctx->sem); + if (!cs_asserted && !(msgs->mode & SPI_NO_CS)) { + setup = ctx->cs_pins[bus->cs].cs_setup_bits; + if (setup) { + regs->TIMECMP0 = USART_TIMECMP0_RESTARTEN_DEFAULT | + USART_TIMECMP0_TSTOP_DEFAULT | + USART_TIMECMP0_TSTART_DISABLE | + ((setup << _USART_TIMECMP0_TCMPVAL_SHIFT) & + _USART_TIMECMP0_TCMPVAL_MASK); + regs->TIMING = USART_TIMING_CSHOLD_ZERO | + USART_TIMING_ICS_ZERO | + USART_TIMING_CSSETUP_TCMP0 | + USART_TIMING_TXDELAY_DISABLE; + } else { + regs->TIMING = USART_TIMING_CSHOLD_ZERO | + USART_TIMING_ICS_ZERO | + USART_TIMING_CSSETUP_ZERO | + USART_TIMING_TXDELAY_DISABLE; + } + cs_asserted = true; + cs_control(ctx, bus->cs, true); + } + xfer_start(ctx); + rtems_binary_semaphore_wait(&ctx->sem); + } + if ((msgs->cs_change || msg_count == 1 || sc) && + !(msgs->mode & SPI_NO_CS)) { + cs_control(ctx, bus->cs, false); + cs_asserted = false; + } + msgs++; + msg_count--; + } + + return sc; +} + +static void usart_init(struct spi_context_s *ctx) +{ + USART_TypeDef *regs = ctx->regs; + + regs->IEN = 0; + regs->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX | + USART_CMD_RXDIS | USART_CMD_TXDIS; + + regs->CTRL = USART_CTRL_SYNC; + regs->FRAME = USART_FRAME_STOPBITS_DEFAULT | + USART_FRAME_PARITY_NONE | + USART_FRAME_DATABITS_EIGHT; + regs->TIMING = USART_TIMING_CSHOLD_ZERO | + USART_TIMING_ICS_ZERO | + USART_TIMING_CSSETUP_ZERO | + USART_TIMING_TXDELAY_DISABLE; + + regs->CMD = USART_CMD_MASTEREN | USART_CMD_RXEN | USART_CMD_TXEN; +} + +static void pins_init(struct spi_context_s *ctx) +{ + USART_TypeDef *regs = ctx->regs; + int i; + uint32_t r; + + for (i = 0; i < ctx->cs_pin_count; i++) { + cs_control(ctx, i, false); + efm32gg11_gpio_mode(ctx->cs_pins[i].port, ctx->cs_pins[i].pin, + GPIO_P_MODEL_MODE0_PUSHPULL); + } + + regs->ROUTELOC0 = ((ctx->clk_pin_loc << _USART_ROUTELOC0_CLKLOC_SHIFT) & + _USART_ROUTELOC0_CLKLOC_MASK) | + ((ctx->tx_pin_loc << _USART_ROUTELOC0_TXLOC_SHIFT) & + _USART_ROUTELOC0_TXLOC_MASK) | + ((ctx->rx_pin_loc << _USART_ROUTELOC0_RXLOC_SHIFT) & + _USART_ROUTELOC0_RXLOC_MASK); + + r = 0; + if (ctx->clk_pin_loc >= 0) { + efm32gg11_gpio_clear_set(ctx->clk_port, 1 << ctx->clk_pin, 0); + efm32gg11_gpio_mode(ctx->clk_port, ctx->clk_pin, + GPIO_P_MODEL_MODE0_PUSHPULL); + r |= USART_ROUTEPEN_CLKPEN; + } + if (ctx->tx_pin_loc >= 0) { + efm32gg11_gpio_clear_set(ctx->tx_port, 1 << ctx->tx_pin, 0); + efm32gg11_gpio_mode(ctx->tx_port, ctx->tx_pin, + GPIO_P_MODEL_MODE0_PUSHPULL); + r |= USART_ROUTEPEN_TXPEN; + } + if (ctx->rx_pin_loc >= 0) { + efm32gg11_gpio_mode(ctx->rx_port, ctx->rx_pin, + GPIO_P_MODEL_MODE0_INPUT); + r |= USART_ROUTEPEN_RXPEN; + } + regs->ROUTEPEN = r; +} + +static void dma_init(struct spi_context_s *ctx) +{ + + LDMA->CH[ctx->tx_dma_channel].REQSEL = ctx->tx_dma_req; + LDMA->CH[ctx->tx_dma_channel].CFG = LDMA_CH_CFG_SRCINCSIGN_POSITIVE | + LDMA_CH_CFG_ARBSLOTS_ONE; + LDMA->CH[ctx->tx_dma_channel].LOOP = LDMA_CH_LOOP_LOOPCNT_DEFAULT; + LDMA->CH[ctx->tx_dma_channel].LINK = 0; + + LDMA->CH[ctx->rx_dma_channel].REQSEL = ctx->rx_dma_req; + LDMA->CH[ctx->rx_dma_channel].CFG = LDMA_CH_CFG_DSTINCSIGN_POSITIVE | + LDMA_CH_CFG_ARBSLOTS_ONE; + LDMA->CH[ctx->rx_dma_channel].LOOP = LDMA_CH_LOOP_LOOPCNT_DEFAULT; + LDMA->CH[ctx->rx_dma_channel].LINK = 0; + + efm32gg11_dma_register(ctx->rx_dma_channel, rx_done_int, ctx); + LDMA->IFC = 1 << (ctx->rx_dma_channel + _LDMA_IFC_DONE_SHIFT); + efm32gg11_dma_int_enable(ctx->rx_dma_channel, true); +} + +static void spi_destroy(spi_bus *bus) +{ + struct spi_context_s *ctx = (struct spi_context_s *) bus; + USART_TypeDef *regs = ctx->regs; + rtems_interrupt_level level; + + regs->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS; + regs->IEN = 0; + + efm32gg11_dma_int_enable(ctx->tx_dma_channel, false); + efm32gg11_dma_int_enable(ctx->rx_dma_channel, false); + __DSB(); + rtems_binary_semaphore_destroy(&ctx->sem); + + rtems_interrupt_disable(level); + CMU->HFPERCLKEN0 &= ~ctx->hfperclken0_mask; + rtems_interrupt_enable(level); +} + +int efm32gg11_spi_register() +{ + rtems_status_code sc; + struct spi_context_s *ctx; + rtems_interrupt_level level; + size_t i; + + sc = RTEMS_SUCCESSFUL; + for (i = 0; + i < RTEMS_ARRAY_SIZE(spi_instances) && sc == RTEMS_SUCCESSFUL; + i++) { + ctx = &spi_instances[i]; + spi_bus_init(&ctx->bus); + + rtems_interrupt_disable(level); + CMU->HFPERCLKEN0 |= ctx->hfperclken0_mask; + rtems_interrupt_enable(level); + usart_init(ctx); + pins_init(ctx); + dma_init(ctx); + + ctx->bus.transfer = spi_transfer; + ctx->bus.destroy = spi_destroy; + ctx->bus.setup = spi_setup; + ctx->bus.max_speed_hz = clock_max(ctx); + ctx->bus.speed_hz = ctx->bus.max_speed_hz; + ctx->bus.bits_per_word = 8; + ctx->bus.cs = 0; + + spi_setup(&ctx->bus); + + sc = spi_bus_register(&ctx->bus, ctx->name); + } + + return sc; +} diff --git a/bsps/arm/efm32gg11/start/bspreset.c b/bsps/arm/efm32gg11/start/bspreset.c new file mode 100644 index 0000000000..535dbb5be0 --- /dev/null +++ b/bsps/arm/efm32gg11/start/bspreset.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2012 Sebastian Huber + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include + +void bsp_reset( rtems_fatal_source source, rtems_fatal_code code ) +{ + rtems_interrupt_level level; + + (void) source; + (void) code; + + rtems_interrupt_disable(level); + (void) level; + + while (1); +} diff --git a/bsps/arm/efm32gg11/start/bspstart.c b/bsps/arm/efm32gg11/start/bspstart.c new file mode 100644 index 0000000000..23106964c4 --- /dev/null +++ b/bsps/arm/efm32gg11/start/bspstart.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 BSP Initialization + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + + +void bsp_start(void) +{ + bsp_interrupt_initialize(); + + efm32gg11_gpio_init(); +} diff --git a/bsps/arm/efm32gg11/start/bspstarthook.c b/bsps/arm/efm32gg11/start/bspstarthook.c new file mode 100644 index 0000000000..39e076c82f --- /dev/null +++ b/bsps/arm/efm32gg11/start/bspstarthook.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2012 Sebastian Huber + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +void BSP_START_TEXT_SECTION bsp_start_hook_1(void) +{ + bsp_start_copy_sections(); + bsp_start_clear_bss(); + + /* At this point we can use objects outside the .start section */ + efm32gg11_clock_init(); + efm32gg11_gpio_init_0(); +} diff --git a/bsps/arm/efm32gg11/start/efm32gg11_clock.c b/bsps/arm/efm32gg11/start/efm32gg11_clock.c new file mode 100644 index 0000000000..eb6575b09d --- /dev/null +++ b/bsps/arm/efm32gg11/start/efm32gg11_clock.c @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 System Clocks Setup + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +#define HFRCO_FREQ_DEFAULT 19000000 + +#define PASTE2(a,b) a ## b +#define PASTE3(a,b,c) a ## b ## c +#define PASTE4(a,b,c,d) a ## b ## c ## d + +#define HFXO_MODE(t) PASTE2(CMU_HFXOCTRL_MODE_, t) +#define LFXO_MODE(t) PASTE2(CMU_LFXOCTRL_MODE_, t) + + +struct efm32gg11_clock_s efm32gg11_clock; + + +#if EFM32GG11_HFRCO_FREQ > 0 +static struct { + int32_t freq; + const volatile uint32_t *cal; +} hfrco_calib[] = { + {4000000, &DEVINFO->HFRCOCAL0}, + {7000000, &DEVINFO->HFRCOCAL3}, + {13000000, &DEVINFO->HFRCOCAL6}, + {16000000, &DEVINFO->HFRCOCAL7}, + {19000000, &DEVINFO->HFRCOCAL8}, + {26000000, &DEVINFO->HFRCOCAL10}, + {32000000, &DEVINFO->HFRCOCAL11}, + {38000000, &DEVINFO->HFRCOCAL12}, + {48000000, &DEVINFO->HFRCOCAL13}, + {56000000, &DEVINFO->HFRCOCAL14}, + {64000000, &DEVINFO->HFRCOCAL15}, + {72000000, &DEVINFO->HFRCOCAL16} +}; +#endif + + +static void ws_config(void) +{ + uint32_t r; + + MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK; + + r = MSC->READCTRL & ~_MSC_READCTRL_MODE_MASK; + if (efm32gg11_clock.hfclk > 54000000) + r |= MSC_READCTRL_MODE_WS3; + else if (efm32gg11_clock.hfclk > 36000000) + r |= MSC_READCTRL_MODE_WS2; + else if (efm32gg11_clock.hfclk > 18000000) + r |= MSC_READCTRL_MODE_WS1; + else + r |= MSC_READCTRL_MODE_WS0; + MSC->READCTRL = r; + + r = MSC->CTRL & ~_MSC_CTRL_WAITMODE_MASK; + if (efm32gg11_clock.hfclk > 50000000) + r |= MSC_CTRL_WAITMODE_WS1; + else + r |= MSC_CTRL_WAITMODE_WS0; + MSC->CTRL = r; + + r = MSC->RAMCTRL; + if (efm32gg11_clock.hfclk > 38000000) + r |= MSC_RAMCTRL_RAMWSEN | MSC_RAMCTRL_RAM1WSEN | MSC_RAMCTRL_RAM2WSEN; + else + r &= ~(MSC_RAMCTRL_RAMWSEN | MSC_RAMCTRL_RAM1WSEN | MSC_RAMCTRL_RAM2WSEN); + MSC->RAMCTRL = r; + + r = CMU->CTRL; + if (efm32gg11_clock.hfclk > 32000000) + r |= CMU_CTRL_WSHFLE; + else + r &= ~CMU_CTRL_WSHFLE; + CMU->CTRL = r; +} + +static void divisors_config(void) +{ + uint32_t divisor; + + divisor = 1; + CMU->HFCOREPRESC = (divisor - 1) << _CMU_HFCOREPRESC_PRESC_SHIFT; + efm32gg11_clock.hfcoreclk = efm32gg11_clock.hfclk / divisor; + + divisor = (efm32gg11_clock.hfclk > 50000000) ? 2 : 1; + CMU->HFBUSPRESC = (divisor - 1) << _CMU_HFBUSPRESC_PRESC_SHIFT; + efm32gg11_clock.hfbusclk = efm32gg11_clock.hfclk / divisor; + + divisor = (efm32gg11_clock.hfclk > 50000000) ? 2 : 1; + CMU->HFPERPRESC = (divisor - 1) << _CMU_HFPERPRESC_PRESC_SHIFT; + efm32gg11_clock.hfperclk = efm32gg11_clock.hfclk / divisor; + + divisor = 1; + CMU->HFPERPRESCB = (divisor - 1) << _CMU_HFPERPRESCB_PRESC_SHIFT; + efm32gg11_clock.hfperbclk = efm32gg11_clock.hfclk / divisor; + + divisor = (efm32gg11_clock.hfclk > 50000000) ? 2 : 1; + CMU->HFPERPRESCC = (divisor - 1) << _CMU_HFPERPRESCC_PRESC_SHIFT; + efm32gg11_clock.hfpercclk = efm32gg11_clock.hfclk / divisor; + + divisor = 2; + CMU->HFEXPPRESC = (divisor - 1) << _CMU_HFEXPPRESC_PRESC_SHIFT; + efm32gg11_clock.hfexpclk = efm32gg11_clock.hfclk / divisor; +} + +void efm32gg11_clock_init(void) +{ + uint32_t hfrco_ctrl; + int i; + + CMU->CTRL = CMU_CTRL_HFPERCLKEN; + +#if EFM32GG11_LFXO_FREQ > 0 + CMU->FREEZE = 0; + if (!(CMU->STATUS & CMU_STATUS_LFXOENS)) { + while (CMU->SYNCBUSY & CMU_SYNCBUSY_LFXOBSY) + ; + CMU->LFXOCTRL = + (EFM32GG11_LFXO_TUNING << _CMU_LFXOCTRL_TUNING_SHIFT) | + LFXO_MODE(EFM32GG11_LFXO_TYPE) | + (EFM32GG11_LFXO_GAIN << _CMU_LFXOCTRL_GAIN_SHIFT) | + CMU_LFXOCTRL_HIGHAMPL_DEFAULT | + CMU_LFXOCTRL_AGC_DEFAULT | + CMU_LFXOCTRL_CUR_DEFAULT | + CMU_LFXOCTRL_BUFCUR_DEFAULT | + CMU_LFXOCTRL_TIMEOUT_DEFAULT; + while (CMU->SYNCBUSY & CMU_SYNCBUSY_LFXOBSY) + ; + CMU->OSCENCMD = CMU_OSCENCMD_LFXOEN; + } + EMU->EM4CTRL |= EMU_EM4CTRL_RETAINLFXO; + CMU->LFACLKSEL = CMU_LFACLKSEL_LFA_LFXO; + efm32gg11_clock.lfaclk = EFM32GG11_LFXO_FREQ; + CMU->LFBCLKSEL = CMU_LFBCLKSEL_LFB_LFXO; + efm32gg11_clock.lfbclk = EFM32GG11_LFXO_FREQ; + CMU->LFCCLKSEL = CMU_LFCCLKSEL_LFC_LFXO; + efm32gg11_clock.lfcclk = EFM32GG11_LFXO_FREQ; +#else + CMU->OSCENCMD = CMU_OSCENCMD_LFRCOEN; + CMU->LFACLKSEL = CMU_LFACLKSEL_LFA_LFRCO; + efm32gg11_clock.lfaclk = 32768; + CMU->LFBCLKSEL = CMU_LFBCLKSEL_LFB_LFRCO; + efm32gg11_clock.lfbclk = 32768; + CMU->LFCCLKSEL = CMU_LFCCLKSEL_LFC_LFRCO; + efm32gg11_clock.lfcclk = 32768; +#endif + + CMU->LFECLKSEL = CMU_LFECLKSEL_LFE_ULFRCO; + efm32gg11_clock.lfeclk = 1000; + + efm32gg11_clock.hfclk = HFRCO_FREQ_DEFAULT; + +#if EFM32GG11_HFXO_FREQ > 0 + efm32gg11_clock.hfclk = EFM32GG11_HFXO_FREQ; + CMU->HFXOCTRL = CMU_HFXOCTRL_AUTOSTARTSELEM0EM1_DEFAULT | + CMU_HFXOCTRL_AUTOSTARTEM0EM1_DEFAULT | + CMU_HFXOCTRL_LFTIMEOUT_DEFAULT | + CMU_HFXOCTRL_PEAKDETMODE_DEFAULT | +#if EFM32GG11_HFXO_FREQ <= 25000000 + CMU_HFXOCTRL_HFXOX2EN | +#endif + HFXO_MODE(EFM32GG11_HFXO_TYPE); + CMU->HFXOSTARTUPCTRL = + EFM32GG11_HFXO_TUNING << _CMU_HFXOSTARTUPCTRL_CTUNE_SHIFT | + CMU_HFXOSTARTUPCTRL_IBTRIMXOCORE_DEFAULT; + CMU->HFXOSTEADYSTATECTRL = + EFM32GG11_HFXO_TUNING << _CMU_HFXOSTEADYSTATECTRL_CTUNE_SHIFT | + CMU_HFXOSTEADYSTATECTRL_IBTRIMXOCORE_DEFAULT; + CMU->OSCENCMD = CMU_OSCENCMD_HFXOEN; +#endif + +#if EFM32GG11_HFRCO_FREQ > 0 + for (i = 0; i < sizeof(hfrco_calib) / sizeof(hfrco_calib[0]) - 1; i++) { + if (abs(hfrco_calib[i + 1].freq - EFM32GG11_HFRCO_FREQ) > + abs(hfrco_calib[i].freq - EFM32GG11_HFRCO_FREQ)) + break; + } + efm32gg11_clock.hfclk = hfrco_calib[i].freq; + hfrco_ctrl = *hfrco_calib[i].cal; +#else + (void) i; + (void) hfrco_ctrl; +#endif + + if (efm32gg11_clock.hfclk > HFRCO_FREQ_DEFAULT) { + ws_config(); + divisors_config(); + } + +#if EFM32GG11_HFRCO_FREQ > 0 + CMU->HFRCOCTRL = hfrco_ctrl; +#elif EFM32GG11_HFXO_FREQ > 0 + while (!(CMU->STATUS & CMU_STATUS_HFXORDY)) + ; + CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO; + CMU->OSCENCMD = CMU_OSCENCMD_HFRCODIS; +#endif + + if (efm32gg11_clock.hfclk <= HFRCO_FREQ_DEFAULT) { + ws_config(); + divisors_config(); + } +} diff --git a/bsps/arm/efm32gg11/start/linkcmds.intflash b/bsps/arm/efm32gg11/start/linkcmds.intflash new file mode 100644 index 0000000000..cae019a913 --- /dev/null +++ b/bsps/arm/efm32gg11/start/linkcmds.intflash @@ -0,0 +1,21 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", INTFLASH); +REGION_ALIAS ("REGION_VECTOR", INTSRAM); +REGION_ALIAS ("REGION_TEXT", INTFLASH); +REGION_ALIAS ("REGION_TEXT_LOAD", INTFLASH); +REGION_ALIAS ("REGION_RODATA", INTFLASH); +REGION_ALIAS ("REGION_RODATA_LOAD", INTFLASH); +REGION_ALIAS ("REGION_DATA", INTSRAM); +REGION_ALIAS ("REGION_DATA_LOAD", INTFLASH); +REGION_ALIAS ("REGION_FAST_TEXT", INTSRAM); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", INTFLASH); +REGION_ALIAS ("REGION_FAST_DATA", INTSRAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", INTFLASH); +REGION_ALIAS ("REGION_BSS", INTSRAM); +REGION_ALIAS ("REGION_WORK", INTSRAM); +REGION_ALIAS ("REGION_STACK", INTSRAM); +REGION_ALIAS ("REGION_NOCACHE", INTSRAM); +REGION_ALIAS ("REGION_NOCACHE_LOAD", INTSRAM); + +INCLUDE linkcmds.armv7m diff --git a/bsps/arm/efm32gg11/start/linkcmds.intsram b/bsps/arm/efm32gg11/start/linkcmds.intsram new file mode 100644 index 0000000000..b7c95b1d1c --- /dev/null +++ b/bsps/arm/efm32gg11/start/linkcmds.intsram @@ -0,0 +1,23 @@ +INCLUDE linkcmds.memory + +bsp_vector_table_in_start_section = 1; + +REGION_ALIAS ("REGION_START", INTSRAM); +REGION_ALIAS ("REGION_VECTOR", INTSRAM); +REGION_ALIAS ("REGION_TEXT", INTSRAM); +REGION_ALIAS ("REGION_TEXT_LOAD", INTSRAM); +REGION_ALIAS ("REGION_RODATA", INTSRAM); +REGION_ALIAS ("REGION_RODATA_LOAD", INTSRAM); +REGION_ALIAS ("REGION_DATA", INTSRAM); +REGION_ALIAS ("REGION_DATA_LOAD", INTSRAM); +REGION_ALIAS ("REGION_FAST_TEXT", INTSRAM); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", INTSRAM); +REGION_ALIAS ("REGION_FAST_DATA", INTSRAM); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", INTSRAM); +REGION_ALIAS ("REGION_BSS", INTSRAM); +REGION_ALIAS ("REGION_WORK", INTSRAM); +REGION_ALIAS ("REGION_STACK", INTSRAM); +REGION_ALIAS ("REGION_NOCACHE", INTSRAM); +REGION_ALIAS ("REGION_NOCACHE_LOAD", INTSRAM); + +INCLUDE linkcmds.armv7m diff --git a/bsps/arm/efm32gg11/trng/efm32gg11_trng.c b/bsps/arm/efm32gg11/trng/efm32gg11_trng.c new file mode 100644 index 0000000000..f6c01547db --- /dev/null +++ b/bsps/arm/efm32gg11/trng/efm32gg11_trng.c @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMEFM32GG11 + * + * @brief EFM32GG11 TRNG getentropy() Implementation + */ + +/* + * Copyright (C) 2025 Allan N. Hessenflow + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +static void efm32gg11_trng_enable(void) +{ + rtems_interrupt_level level; + + rtems_interrupt_disable(level); + CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_TRNG0; + rtems_interrupt_enable(level); + + TRNG0->CONTROL = TRNG_CONTROL_ENABLE; + + while (TRNG0->FIFOLEVEL < 4) + ; + TRNG0->KEY0 = TRNG0->FIFO; + TRNG0->KEY1 = TRNG0->FIFO; + TRNG0->KEY2 = TRNG0->FIFO; + TRNG0->KEY3 = TRNG0->FIFO; + + TRNG0->CONTROL = TRNG_CONTROL_SOFTRESET | TRNG_CONTROL_ENABLE; + TRNG0->CONTROL = TRNG_CONTROL_ENABLE; +} + +int getentropy(void *ptr, size_t n) +{ + union { + uint8_t b[4]; + uint32_t g; + } v; + int i; + + while (n) { + /* How fast is the TRNG? Maybe we should block until the FIFO is + full (64 x 32 bits) (the only data available related interrupt + for the module is fifo full), or maybe delay for a tick inside + the wait loop */ + while (TRNG0->FIFOLEVEL == 0) + ; + v.g = TRNG0->FIFO; + for (i = 0; i < 4 && n; i++, n--) + *(uint8_t *)ptr++ = v.b[i]; + } + + return 0; +} + +RTEMS_SYSINIT_ITEM( + efm32gg11_trng_enable, + RTEMS_SYSINIT_DEVICE_DRIVERS, + RTEMS_SYSINIT_ORDER_LAST_BUT_5 +); diff --git a/spec/build/bsps/arm/efm32gg11/abi.yml b/spec/build/bsps/arm/efm32gg11/abi.yml new file mode 100644 index 0000000000..3809816010 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/abi.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: + - -mcpu=cortex-m4 + - -mthumb + - -mfloat-abi=hard + - -mfpu=auto +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/arm/efm32gg11/bspefm32g11.yml b/spec/build/bsps/arm/efm32gg11/bspefm32g11.yml new file mode 100644 index 0000000000..46ac4d8b0d --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/bspefm32g11.yml @@ -0,0 +1,23 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: arm +bsp: efm32gg11 +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +cppflags: [] +enabled-by: true +family: efm32gg11 +includes: [] +install: [] +links: +- role: build-dependency + uid: ../../opto2 +- role: build-dependency + uid: ../../tstsmallmem +- role: build-dependency + uid: tstefm32gg11 +- role: build-dependency + uid: grp +source: [] +type: build diff --git a/spec/build/bsps/arm/efm32gg11/grp.yml b/spec/build/bsps/arm/efm32gg11/grp.yml new file mode 100644 index 0000000000..1158afd235 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/grp.yml @@ -0,0 +1,323 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +cflags: [] +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: [] +ldflags: [] +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: abi +- role: build-dependency + uid: obj +- role: build-dependency + uid: optdevice +- role: build-dependency + uid: optconcsloc +- role: build-dependency + uid: optconctrl +- role: build-dependency + uid: optconidx +- role: build-dependency + uid: optcontiming +- role: build-dependency + uid: optcontype +- role: build-dependency + uid: optcontxloc +- role: build-dependency + uid: optconrxloc +- role: build-dependency + uid: optconctsloc +- role: build-dependency + uid: optconrtsloc +- role: build-dependency + uid: optconvcom +- role: build-dependency + uid: opti2c0idx +- role: build-dependency + uid: opti2c0sclloc +- role: build-dependency + uid: opti2c0sdaloc +- role: build-dependency + uid: opti2c1idx +- role: build-dependency + uid: opti2c1sclloc +- role: build-dependency + uid: opti2c1sdaloc +- role: build-dependency + uid: opti2c2idx +- role: build-dependency + uid: opti2c2sclloc +- role: build-dependency + uid: opti2c2sdaloc +- role: build-dependency + uid: optspi0idx +- role: build-dependency + uid: optspi0cspins +- role: build-dependency + uid: optspi0clkloc +- role: build-dependency + uid: optspi0rxloc +- role: build-dependency + uid: optspi0txloc +- role: build-dependency + uid: optspi0rxdma +- role: build-dependency + uid: optspi0txdma +- role: build-dependency + uid: optspi1idx +- role: build-dependency + uid: optspi1cspins +- role: build-dependency + uid: optspi1clkloc +- role: build-dependency + uid: optspi1rxloc +- role: build-dependency + uid: optspi1txloc +- role: build-dependency + uid: optspi1rxdma +- role: build-dependency + uid: optspi1txdma +- role: build-dependency + uid: optspi1idx +- role: build-dependency + uid: optspi1cspins +- role: build-dependency + uid: optspi1clkloc +- role: build-dependency + uid: optspi1rxloc +- role: build-dependency + uid: optspi1txloc +- role: build-dependency + uid: optspi1rxdma +- role: build-dependency + uid: optspi1txdma +- role: build-dependency + uid: optspi2idx +- role: build-dependency + uid: optspi2cspins +- role: build-dependency + uid: optspi2clkloc +- role: build-dependency + uid: optspi2rxloc +- role: build-dependency + uid: optspi2txloc +- role: build-dependency + uid: optspi2rxdma +- role: build-dependency + uid: optspi2txdma +- role: build-dependency + uid: optspi3idx +- role: build-dependency + uid: optspi3cspins +- role: build-dependency + uid: optspi3clkloc +- role: build-dependency + uid: optspi3rxloc +- role: build-dependency + uid: optspi3txloc +- role: build-dependency + uid: optspi3rxdma +- role: build-dependency + uid: optspi3txdma +- role: build-dependency + uid: optspi4idx +- role: build-dependency + uid: optspi4cspins +- role: build-dependency + uid: optspi4clkloc +- role: build-dependency + uid: optspi4rxloc +- role: build-dependency + uid: optspi4txloc +- role: build-dependency + uid: optspi4rxdma +- role: build-dependency + uid: optspi4txdma +- role: build-dependency + uid: optspi5idx +- role: build-dependency + uid: optspi5cspins +- role: build-dependency + uid: optspi5clkloc +- role: build-dependency + uid: optspi5rxloc +- role: build-dependency + uid: optspi5txloc +- role: build-dependency + uid: optspi5rxdma +- role: build-dependency + uid: optspi5txdma +- role: build-dependency + uid: optttys1csloc +- role: build-dependency + uid: optttys1ctrl +- role: build-dependency + uid: optttys1idx +- role: build-dependency + uid: optttys1timing +- role: build-dependency + uid: optttys1type +- role: build-dependency + uid: optttys1txloc +- role: build-dependency + uid: optttys1rxloc +- role: build-dependency + uid: optttys1ctsloc +- role: build-dependency + uid: optttys1rtsloc +- role: build-dependency + uid: optttys2csloc +- role: build-dependency + uid: optttys2ctrl +- role: build-dependency + uid: optttys2idx +- role: build-dependency + uid: optttys2timing +- role: build-dependency + uid: optttys2type +- role: build-dependency + uid: optttys2txloc +- role: build-dependency + uid: optttys2rxloc +- role: build-dependency + uid: optttys2ctsloc +- role: build-dependency + uid: optttys2rtsloc +- role: build-dependency + uid: optttys3csloc +- role: build-dependency + uid: optttys3ctrl +- role: build-dependency + uid: optttys3idx +- role: build-dependency + uid: optttys3timing +- role: build-dependency + uid: optttys3type +- role: build-dependency + uid: optttys3txloc +- role: build-dependency + uid: optttys3rxloc +- role: build-dependency + uid: optttys3ctsloc +- role: build-dependency + uid: optttys3rtsloc +- role: build-dependency + uid: optttys4csloc +- role: build-dependency + uid: optttys4ctrl +- role: build-dependency + uid: optttys4idx +- role: build-dependency + uid: optttys4timing +- role: build-dependency + uid: optttys4type +- role: build-dependency + uid: optttys4txloc +- role: build-dependency + uid: optttys4rxloc +- role: build-dependency + uid: optttys4ctsloc +- role: build-dependency + uid: optttys4rtsloc +- role: build-dependency + uid: optttys5csloc +- role: build-dependency + uid: optttys5ctrl +- role: build-dependency + uid: optttys5idx +- role: build-dependency + uid: optttys5timing +- role: build-dependency + uid: optttys5type +- role: build-dependency + uid: optttys5txloc +- role: build-dependency + uid: optttys5rxloc +- role: build-dependency + uid: optttys5ctsloc +- role: build-dependency + uid: optttys5rtsloc +- role: build-dependency + uid: optttys6csloc +- role: build-dependency + uid: optttys6ctrl +- role: build-dependency + uid: optttys6idx +- role: build-dependency + uid: optttys6timing +- role: build-dependency + uid: optttys6type +- role: build-dependency + uid: optttys6txloc +- role: build-dependency + uid: optttys6rxloc +- role: build-dependency + uid: optttys6ctsloc +- role: build-dependency + uid: optttys6rtsloc +- role: build-dependency + uid: optttys7csloc +- role: build-dependency + uid: optttys7ctrl +- role: build-dependency + uid: optttys7idx +- role: build-dependency + uid: optttys7timing +- role: build-dependency + uid: optttys7type +- role: build-dependency + uid: optttys7txloc +- role: build-dependency + uid: optttys7rxloc +- role: build-dependency + uid: optttys7ctsloc +- role: build-dependency + uid: optttys7rtsloc +- role: build-dependency + uid: optlfxofreq +- role: build-dependency + uid: optlfxogain +- role: build-dependency + uid: optlfxotuning +- role: build-dependency + uid: optlfxotype +- role: build-dependency + uid: opthfrcofreq +- role: build-dependency + uid: opthfxofreq +- role: build-dependency + uid: opthfxotuning +- role: build-dependency + uid: opthfxotype +- role: build-dependency + uid: optlinkcmds +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: linkcmdsmemory +- role: build-dependency + uid: ../../optconsolebaud +- role: build-dependency + uid: ../../optconsoleirq +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: optincludes +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/arm/efm32gg11/linkcmds.yml b/spec/build/bsps/arm/efm32gg11/linkcmds.yml new file mode 100644 index 0000000000..21f89306ce --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/linkcmds.yml @@ -0,0 +1,11 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + INCLUDE ${EFM32GG11_DEFAULT_LINKCMDS} +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build diff --git a/spec/build/bsps/arm/efm32gg11/linkcmdsmemory.yml b/spec/build/bsps/arm/efm32gg11/linkcmdsmemory.yml new file mode 100644 index 0000000000..8ea0624dec --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/linkcmdsmemory.yml @@ -0,0 +1,14 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + MEMORY { + INTFLASH : ORIGIN = 0x00000000, LENGTH = ${EFM32GG11_MEMORY_INTFLASH_SIZE} + INTSRAM : ORIGIN = 0x20000000, LENGTH = ${EFM32GG11_MEMORY_INTSRAM_SIZE} + } +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds.memory +type: build diff --git a/spec/build/bsps/arm/efm32gg11/obj.yml b/spec/build/bsps/arm/efm32gg11/obj.yml new file mode 100644 index 0000000000..47735b102b --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/obj.yml @@ -0,0 +1,123 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/arm/efm32gg11/include/bsp.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/arm/efm32gg11/include/bsp/i2c.h + - bsps/arm/efm32gg11/include/bsp/irq.h + - bsps/arm/efm32gg11/include/bsp/spi.h + - bsps/arm/efm32gg11/include/bsp/efm32gg11_clock.h + - bsps/arm/efm32gg11/include/bsp/efm32gg11_dma.h + - bsps/arm/efm32gg11/include/bsp/efm32gg11_gpio.h + - contrib/bsps/arm/efm32gg11/efm32gg11b110f2048gm64.h + - contrib/bsps/arm/efm32gg11/efm32gg11b120f2048gm64.h + - contrib/bsps/arm/efm32gg11/efm32gg11b310f2048gl112.h + - contrib/bsps/arm/efm32gg11/efm32gg11b320f2048gl112.h + - contrib/bsps/arm/efm32gg11/efm32gg11b420f2048gl120.h + - contrib/bsps/arm/efm32gg11/efm32gg11b510f2048gl120.h + - contrib/bsps/arm/efm32gg11/efm32gg11b520f2048gl120.h + - contrib/bsps/arm/efm32gg11/efm32gg11b820f2048gl192.h + - contrib/bsps/arm/efm32gg11/efm32gg11b840f1024gl192.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_acmp.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_adc.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_af_pins.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_af_ports.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_can.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_can_mir.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_cmu.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_cryotimer.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_crypto.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_csen.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_devinfo.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_dma_descriptor.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_dmareq.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_ebi.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_emu.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_eth.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_etm.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_fpueh.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_gpcrc.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_gpio.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_gpio_p.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_i2c.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_idac.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_lcd.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_ldma_ch.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_ldma.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_lesense_buf.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_lesense_ch.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_lesense.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_lesense_st.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_letimer.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_leuart.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_msc.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_pcnt.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_prs_ch.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_prs.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_prs_signals.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_qspi.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_rmu.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_romtable.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_rtcc_cc.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_rtcc.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_rtc_comp.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_rtcc_ret.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_rtc.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_sdio.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_smu.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_timer_cc.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_timer.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_trng.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_uart.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_usart.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_usb_diep.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_usb_doep.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_usb.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_usb_hc.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_vdac.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_vdac_opa.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_wdog.h + - contrib/bsps/arm/efm32gg11/efm32gg11b_wdog_pch.h + - contrib/bsps/arm/efm32gg11/system_efm32gg11b.h + - bsps/arm/efm32gg11/include/bsp/processor.h +- destination: ${BSP_LIBDIR} + source: + - bsps/arm/efm32gg11/start/linkcmds.intflash + - bsps/arm/efm32gg11/start/linkcmds.intsram +links: [] +source: +- bsps/arm/efm32gg11/console/console.c +- bsps/arm/efm32gg11/dma/efm32gg11_dma.c +- bsps/arm/efm32gg11/gpio/efm32gg11_gpio.c +- bsps/arm/efm32gg11/i2c/i2c.c +- bsps/arm/efm32gg11/spi/spi.c +- bsps/arm/efm32gg11/start/bspreset.c +- bsps/arm/efm32gg11/start/bspstart.c +- bsps/arm/efm32gg11/start/bspstarthook.c +- bsps/arm/efm32gg11/start/efm32gg11_clock.c +- bsps/arm/efm32gg11/trng/efm32gg11_trng.c +- bsps/arm/shared/clock/clock-armv7m.c +- bsps/arm/shared/irq/irq-armv7m.c +- bsps/arm/shared/irq/irq-dispatch-armv7m.c +- bsps/arm/shared/start/bsp-start-memcpy.S +- bsps/arm/shared/start/bspstarthook0-empty.c +- bsps/shared/cache/nocache.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/dev/cpucounter/cpucounterfrequency.c +- bsps/shared/dev/cpucounter/cpucounterread.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optconcsloc.yml b/spec/build/bsps/arm/efm32gg11/optconcsloc.yml new file mode 100644 index 0000000000..6fb910cd03 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optconcsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + console cs pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_CS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optconctrl.yml b/spec/build/bsps/arm/efm32gg11/optconctrl.yml new file mode 100644 index 0000000000..58e17feb07 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optconctrl.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + console usart extra ctl register bits (e.g. USART_CTRL_AUTOCS) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_CTRL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optconctsloc.yml b/spec/build/bsps/arm/efm32gg11/optconctsloc.yml new file mode 100644 index 0000000000..ec8c208d31 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optconctsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 4 +description: | + console cts pin alt function location (default 4) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_CTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optconidx.yml b/spec/build/bsps/arm/efm32gg11/optconidx.yml new file mode 100644 index 0000000000..bb8b493bf9 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optconidx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 4 +description: | + device index for /dev/console (default 4, e.g. USART4) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_DEVICE_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optconrtsloc.yml b/spec/build/bsps/arm/efm32gg11/optconrtsloc.yml new file mode 100644 index 0000000000..f4ddd423a5 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optconrtsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 4 +description: | + console rts pin alt function location (default 4) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_RTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optconrxloc.yml b/spec/build/bsps/arm/efm32gg11/optconrxloc.yml new file mode 100644 index 0000000000..c61dd0eff7 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optconrxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 4 +description: | + console rx pin alt function location (default 4) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optcontiming.yml b/spec/build/bsps/arm/efm32gg11/optcontiming.yml new file mode 100644 index 0000000000..a69912d58a --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optcontiming.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + console usart timing register +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_TIMING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optcontxloc.yml b/spec/build/bsps/arm/efm32gg11/optcontxloc.yml new file mode 100644 index 0000000000..9e3ed4b3bf --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optcontxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 4 +description: | + console tx pin alt function location (default 4) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optcontype.yml b/spec/build/bsps/arm/efm32gg11/optcontype.yml new file mode 100644 index 0000000000..6f68e7c710 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optcontype.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: USART +description: | + device type for /dev/console (UART or USART) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optconvcom.yml b/spec/build/bsps/arm/efm32gg11/optconvcom.yml new file mode 100644 index 0000000000..523bf7723e --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optconvcom.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 1 +description: | + connect console port to board controller +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_CONSOLE_VCOM_ENABLE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optdevice.yml b/spec/build/bsps/arm/efm32gg11/optdevice.yml new file mode 100644 index 0000000000..a4dda7d2c2 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optdevice.yml @@ -0,0 +1,37 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +- script: | + c = (0x00200000, 0x00080000) + chips = { + "EFM32GG11B110": (0x00200000, 0x00060000), + "EFM32GG11B120": (0x00200000, 0x00080000), + "EFM32GG11B310": (0x00200000, 0x00060000), + "EFM32GG11B320": (0x00200000, 0x00080000), + "EFM32GG11B420": (0x00200000, 0x00080000), + "EFM32GG11B510": (0x00200000, 0x00060000), + "EFM32GG11B520": (0x00200000, 0x00080000), + "EFM32GG11B820": c, + "EFM32GG11B840": (0x00100000, 0x00080000), + } + if value: + try: + c = chips[value] + except: + conf.fatal("Unknown chip variant '{}'".format(value)) + conf.env["EFM32GG11_MEMORY_INTFLASH_SIZE"] = c[0] + conf.env["EFM32GG11_MEMORY_INTSRAM_SIZE"] = c[1] +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: EFM32GG11B820 +description: | + Device type +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_DEVICE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opthfrcofreq.yml b/spec/build/bsps/arm/efm32gg11/opthfrcofreq.yml new file mode 100644 index 0000000000..3db24af8a4 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opthfrcofreq.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + HFRCO frequency in Hz (uses closest pre-calibrated frequency) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_HFRCO_FREQ +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opthfxofreq.yml b/spec/build/bsps/arm/efm32gg11/opthfxofreq.yml new file mode 100644 index 0000000000..ffc318a43f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opthfxofreq.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 50000000 +description: | + HFXO frequency in Hz +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_HFXO_FREQ +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opthfxotuning.yml b/spec/build/bsps/arm/efm32gg11/opthfxotuning.yml new file mode 100644 index 0000000000..3fba5acc2f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opthfxotuning.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 182 +description: | + HFXO tuning (0 - 511) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_HFXO_TUNING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opthfxotype.yml b/spec/build/bsps/arm/efm32gg11/opthfxotype.yml new file mode 100644 index 0000000000..9fcec68b75 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opthfxotype.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: XTAL +description: | + hfxo type (XTAL, ACBUFEXTCLK, DCBUFEXTCLK, or DIGEXTCLK) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_HFXO_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c0idx.yml b/spec/build/bsps/arm/efm32gg11/opti2c0idx.yml new file mode 100644 index 0000000000..cd89ed89bf --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c0idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 2 +description: | + device index for /dev/i2c-0 (default 2, e.g. I2C2) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_0_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c0sclloc.yml b/spec/build/bsps/arm/efm32gg11/opti2c0sclloc.yml new file mode 100644 index 0000000000..01dc541b21 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c0sclloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 7 +description: | + i2c-0 scl pin alt function location (default 7) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_0_SCL_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c0sdaloc.yml b/spec/build/bsps/arm/efm32gg11/opti2c0sdaloc.yml new file mode 100644 index 0000000000..c55875ecc9 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c0sdaloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 7 +description: | + i2c-0 sda pin alt function location (default 7) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_0_SDA_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c1idx.yml b/spec/build/bsps/arm/efm32gg11/opti2c1idx.yml new file mode 100644 index 0000000000..57d7699cee --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c1idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/i2c-1 (-1 to disable, 0 for I2C0, etc.) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_1_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c1sclloc.yml b/spec/build/bsps/arm/efm32gg11/opti2c1sclloc.yml new file mode 100644 index 0000000000..fe99680dfe --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c1sclloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + i2c-1 scl pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_1_SCL_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c1sdaloc.yml b/spec/build/bsps/arm/efm32gg11/opti2c1sdaloc.yml new file mode 100644 index 0000000000..e6084f2c04 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c1sdaloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + i2c-1 sda pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_1_SDA_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c2idx.yml b/spec/build/bsps/arm/efm32gg11/opti2c2idx.yml new file mode 100644 index 0000000000..8e449234d7 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c2idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/i2c-2 (-1 to disable, 0 for I2C0, etc.) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_2_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c2sclloc.yml b/spec/build/bsps/arm/efm32gg11/opti2c2sclloc.yml new file mode 100644 index 0000000000..8baa864c63 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c2sclloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + i2c-2 scl pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_2_SCL_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/opti2c2sdaloc.yml b/spec/build/bsps/arm/efm32gg11/opti2c2sdaloc.yml new file mode 100644 index 0000000000..a927245bc5 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/opti2c2sdaloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + i2c-2 sda pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_I2C_2_SDA_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optincludes.yml b/spec/build/bsps/arm/efm32gg11/optincludes.yml new file mode 100644 index 0000000000..2b4e8965e2 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optincludes.yml @@ -0,0 +1,16 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- set-value: | + bsps/include bsps/${ARCH}/include bsps/${ARCH}/${BSP_FAMILY}/include bsps/${ARCH}/${BSP_FAMILY}/${BSP_NAME}/include contrib/bsps/arm/efm32gg11 +- substitute: null +- split: null +- env-assign: null +build-type: option +copyrights: +- Copwyright (C) 2026 Allan N. Hessenflow +default: [] +description: '' +enabled-by: true +links: [] +name: BSP_INCLUDES +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optlfxofreq.yml b/spec/build/bsps/arm/efm32gg11/optlfxofreq.yml new file mode 100644 index 0000000000..2e8e0d6bfc --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optlfxofreq.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 32768 +description: | + LFXO frequency in Hz +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_LFXO_FREQ +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optlfxogain.yml b/spec/build/bsps/arm/efm32gg11/optlfxogain.yml new file mode 100644 index 0000000000..26ce0ead3f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optlfxogain.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 2 +description: | + LFXO gain (0 - 3) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_LFXO_GAIN +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optlfxotuning.yml b/spec/build/bsps/arm/efm32gg11/optlfxotuning.yml new file mode 100644 index 0000000000..37e8b72f1f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optlfxotuning.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 48 +description: | + LFXO tuning (0 - 127) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_LFXO_TUNING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optlfxotype.yml b/spec/build/bsps/arm/efm32gg11/optlfxotype.yml new file mode 100644 index 0000000000..d6d7878bba --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optlfxotype.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: XTAL +description: | + lfxo type (XTAL, BUFEXTCLK, or DIGEXTCLK) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_LFXO_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optlinkcmds.yml b/spec/build/bsps/arm/efm32gg11/optlinkcmds.yml new file mode 100644 index 0000000000..e1742fe821 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optlinkcmds.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- env-assign: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: linkcmds.intflash +description: | + The default linker command file. Must be linkcmds.intflash or + inkcmds.intsram. +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_DEFAULT_LINKCMDS +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi0clkloc.yml b/spec/build/bsps/arm/efm32gg11/optspi0clkloc.yml new file mode 100644 index 0000000000..c2ab55ea3f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi0clkloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 3 +description: | + spi-0 clk pin alt function location (default 3) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_0_CLK_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi0cspins.yml b/spec/build/bsps/arm/efm32gg11/optspi0cspins.yml new file mode 100644 index 0000000000..14ae46c4df --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi0cspins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: "{{2, 14, true, 12}}" +description: | + spi-0 cs pins +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_0_CS_PINS +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi0idx.yml b/spec/build/bsps/arm/efm32gg11/optspi0idx.yml new file mode 100644 index 0000000000..b77ba42238 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi0idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 1 +description: | + device index for /dev/spi-0 (default 1, e.g. USART1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_0_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi0rxdma.yml b/spec/build/bsps/arm/efm32gg11/optspi0rxdma.yml new file mode 100644 index 0000000000..fb1a5f9224 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi0rxdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 1 +description: | + spi-0 rx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_0_RX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi0rxloc.yml b/spec/build/bsps/arm/efm32gg11/optspi0rxloc.yml new file mode 100644 index 0000000000..c479bbfc10 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi0rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-0 rx pin alt function location (default disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_0_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi0txdma.yml b/spec/build/bsps/arm/efm32gg11/optspi0txdma.yml new file mode 100644 index 0000000000..e6010a6f51 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi0txdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-0 tx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_0_TX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi0txloc.yml b/spec/build/bsps/arm/efm32gg11/optspi0txloc.yml new file mode 100644 index 0000000000..5ebbcfac02 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi0txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 6 +description: | + spi-0 tx pin alt function location (default 6) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_0_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi1clkloc.yml b/spec/build/bsps/arm/efm32gg11/optspi1clkloc.yml new file mode 100644 index 0000000000..683f695456 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi1clkloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-1 clk pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_1_CLK_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi1cspins.yml b/spec/build/bsps/arm/efm32gg11/optspi1cspins.yml new file mode 100644 index 0000000000..ba5eca0f52 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi1cspins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: "{{-1, 0, false, 0}}" +description: | + spi-1 cs pins +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_1_CS_PINS +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi1idx.yml b/spec/build/bsps/arm/efm32gg11/optspi1idx.yml new file mode 100644 index 0000000000..123fdd9d08 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi1idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/spi-1 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_1_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi1rxdma.yml b/spec/build/bsps/arm/efm32gg11/optspi1rxdma.yml new file mode 100644 index 0000000000..99f45cde63 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi1rxdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-1 rx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_1_RX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi1rxloc.yml b/spec/build/bsps/arm/efm32gg11/optspi1rxloc.yml new file mode 100644 index 0000000000..d5cada2b63 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi1rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-1 rx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_1_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi1txdma.yml b/spec/build/bsps/arm/efm32gg11/optspi1txdma.yml new file mode 100644 index 0000000000..761b76d891 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi1txdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-1 tx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_1_TX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi1txloc.yml b/spec/build/bsps/arm/efm32gg11/optspi1txloc.yml new file mode 100644 index 0000000000..90ff6555fb --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi1txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-1 tx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_1_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi2clkloc.yml b/spec/build/bsps/arm/efm32gg11/optspi2clkloc.yml new file mode 100644 index 0000000000..b1cd4110c5 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi2clkloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-2 clk pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_2_CLK_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi2cspins.yml b/spec/build/bsps/arm/efm32gg11/optspi2cspins.yml new file mode 100644 index 0000000000..04c3da48f4 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi2cspins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: "{{-1, 0, false, 0}}" +description: | + spi-2 cs pins +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_2_CS_PINS +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi2idx.yml b/spec/build/bsps/arm/efm32gg11/optspi2idx.yml new file mode 100644 index 0000000000..de47cc124b --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi2idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/spi-2 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_2_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi2rxdma.yml b/spec/build/bsps/arm/efm32gg11/optspi2rxdma.yml new file mode 100644 index 0000000000..a13d712656 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi2rxdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-2 rx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_2_RX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi2rxloc.yml b/spec/build/bsps/arm/efm32gg11/optspi2rxloc.yml new file mode 100644 index 0000000000..be62d93c6c --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi2rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-2 rx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_2_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi2txdma.yml b/spec/build/bsps/arm/efm32gg11/optspi2txdma.yml new file mode 100644 index 0000000000..4b25128c91 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi2txdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-2 tx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_2_TX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi2txloc.yml b/spec/build/bsps/arm/efm32gg11/optspi2txloc.yml new file mode 100644 index 0000000000..eb8863c59a --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi2txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-2 tx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_2_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi3clkloc.yml b/spec/build/bsps/arm/efm32gg11/optspi3clkloc.yml new file mode 100644 index 0000000000..ebf118ad46 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi3clkloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-3 clk pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_3_CLK_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi3cspins.yml b/spec/build/bsps/arm/efm32gg11/optspi3cspins.yml new file mode 100644 index 0000000000..582c9d77af --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi3cspins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: "{{-1, 0, false, 0}}" +description: | + spi-3 cs pins +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_3_CS_PINS +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi3idx.yml b/spec/build/bsps/arm/efm32gg11/optspi3idx.yml new file mode 100644 index 0000000000..c4297c881a --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi3idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/spi-3 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_3_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi3rxdma.yml b/spec/build/bsps/arm/efm32gg11/optspi3rxdma.yml new file mode 100644 index 0000000000..38aff39e19 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi3rxdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-3 rx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_3_RX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi3rxloc.yml b/spec/build/bsps/arm/efm32gg11/optspi3rxloc.yml new file mode 100644 index 0000000000..bd3dcd13f8 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi3rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-3 rx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_3_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi3txdma.yml b/spec/build/bsps/arm/efm32gg11/optspi3txdma.yml new file mode 100644 index 0000000000..25f39cc8cc --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi3txdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-3 tx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_3_TX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi3txloc.yml b/spec/build/bsps/arm/efm32gg11/optspi3txloc.yml new file mode 100644 index 0000000000..6bdbe91e6e --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi3txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-3 tx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_3_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi4clkloc.yml b/spec/build/bsps/arm/efm32gg11/optspi4clkloc.yml new file mode 100644 index 0000000000..7cbdf11556 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi4clkloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-4 clk pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_4_CLK_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi4cspins.yml b/spec/build/bsps/arm/efm32gg11/optspi4cspins.yml new file mode 100644 index 0000000000..5da6867360 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi4cspins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: "{{-1, 0, false, 0}}" +description: | + spi-4 cs pins +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_4_CS_PINS +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi4idx.yml b/spec/build/bsps/arm/efm32gg11/optspi4idx.yml new file mode 100644 index 0000000000..926d12dc36 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi4idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/spi-4 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_4_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi4rxdma.yml b/spec/build/bsps/arm/efm32gg11/optspi4rxdma.yml new file mode 100644 index 0000000000..a8170f5fdd --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi4rxdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-4 rx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_4_RX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi4rxloc.yml b/spec/build/bsps/arm/efm32gg11/optspi4rxloc.yml new file mode 100644 index 0000000000..d18620a122 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi4rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-4 rx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_4_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi4txdma.yml b/spec/build/bsps/arm/efm32gg11/optspi4txdma.yml new file mode 100644 index 0000000000..5feccf7434 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi4txdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-4 tx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_4_TX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi4txloc.yml b/spec/build/bsps/arm/efm32gg11/optspi4txloc.yml new file mode 100644 index 0000000000..fce1ffa6a1 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi4txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-4 tx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_4_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi5clkloc.yml b/spec/build/bsps/arm/efm32gg11/optspi5clkloc.yml new file mode 100644 index 0000000000..d79843d28f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi5clkloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-5 clk pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_5_CLK_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi5cspins.yml b/spec/build/bsps/arm/efm32gg11/optspi5cspins.yml new file mode 100644 index 0000000000..f634ed8604 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi5cspins.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: "{{-1, 0, false, 0}}" +description: | + spi-5 cs pins +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_5_CS_PINS +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi5idx.yml b/spec/build/bsps/arm/efm32gg11/optspi5idx.yml new file mode 100644 index 0000000000..3f991c2696 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi5idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/spi-5 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_5_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi5rxdma.yml b/spec/build/bsps/arm/efm32gg11/optspi5rxdma.yml new file mode 100644 index 0000000000..e6f51d7617 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi5rxdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-5 rx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_5_RX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi5rxloc.yml b/spec/build/bsps/arm/efm32gg11/optspi5rxloc.yml new file mode 100644 index 0000000000..2119bae055 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi5rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-5 rx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_5_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi5txdma.yml b/spec/build/bsps/arm/efm32gg11/optspi5txdma.yml new file mode 100644 index 0000000000..4d85441dcd --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi5txdma.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + spi-5 tx dma channel +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_5_TX_DMA_CHANNEL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optspi5txloc.yml b/spec/build/bsps/arm/efm32gg11/optspi5txloc.yml new file mode 100644 index 0000000000..b206c61a5f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optspi5txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + spi-5 tx pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_SPI_5_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1csloc.yml b/spec/build/bsps/arm/efm32gg11/optttys1csloc.yml new file mode 100644 index 0000000000..7a0c401312 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1csloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys1 cs pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_CS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1ctrl.yml b/spec/build/bsps/arm/efm32gg11/optttys1ctrl.yml new file mode 100644 index 0000000000..cf1d4fc636 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1ctrl.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys1 usart extra ctl register bits (e.g. USART_CTRL_AUTOCS) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_CTRL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1ctsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys1ctsloc.yml new file mode 100644 index 0000000000..cce9d51151 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1ctsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys1 cts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_CTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1idx.yml b/spec/build/bsps/arm/efm32gg11/optttys1idx.yml new file mode 100644 index 0000000000..9667c282e7 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/ttyS1 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_DEVICE_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1rtsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys1rtsloc.yml new file mode 100644 index 0000000000..e63f89d8f3 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1rtsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys1 rts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_RTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1rxloc.yml b/spec/build/bsps/arm/efm32gg11/optttys1rxloc.yml new file mode 100644 index 0000000000..621850e453 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys1 rx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1timing.yml b/spec/build/bsps/arm/efm32gg11/optttys1timing.yml new file mode 100644 index 0000000000..11b6640b5f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1timing.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys1 usart timing register +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_TIMING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1txloc.yml b/spec/build/bsps/arm/efm32gg11/optttys1txloc.yml new file mode 100644 index 0000000000..1d31438630 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys1 tx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys1type.yml b/spec/build/bsps/arm/efm32gg11/optttys1type.yml new file mode 100644 index 0000000000..de3c3d3c78 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys1type.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: USART +description: | + device type for /dev/ttyS1 (UART or USART) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS1_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2csloc.yml b/spec/build/bsps/arm/efm32gg11/optttys2csloc.yml new file mode 100644 index 0000000000..fa0364a83b --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2csloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys2 cs pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_CS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2ctrl.yml b/spec/build/bsps/arm/efm32gg11/optttys2ctrl.yml new file mode 100644 index 0000000000..2818faf0c6 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2ctrl.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys2 usart extra ctl register bits (e.g. USART_CTRL_AUTOCS) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_CTRL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2ctsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys2ctsloc.yml new file mode 100644 index 0000000000..4bed8b9575 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2ctsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys2 cts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_CTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2idx.yml b/spec/build/bsps/arm/efm32gg11/optttys2idx.yml new file mode 100644 index 0000000000..3c69acb3dd --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/ttyS2 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_DEVICE_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2rtsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys2rtsloc.yml new file mode 100644 index 0000000000..0ed9b0c5ed --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2rtsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys2 rts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_RTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2rxloc.yml b/spec/build/bsps/arm/efm32gg11/optttys2rxloc.yml new file mode 100644 index 0000000000..21cdd48a6c --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys2 rx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2timing.yml b/spec/build/bsps/arm/efm32gg11/optttys2timing.yml new file mode 100644 index 0000000000..0270f152cc --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2timing.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys2 usart timing register +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_TIMING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2txloc.yml b/spec/build/bsps/arm/efm32gg11/optttys2txloc.yml new file mode 100644 index 0000000000..6507992310 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys2 tx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys2type.yml b/spec/build/bsps/arm/efm32gg11/optttys2type.yml new file mode 100644 index 0000000000..48b19f68ea --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys2type.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: USART +description: | + device type for /dev/ttyS2 (UART or USART) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS2_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3csloc.yml b/spec/build/bsps/arm/efm32gg11/optttys3csloc.yml new file mode 100644 index 0000000000..61dfc7ff91 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3csloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys3 cs pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_CS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3ctrl.yml b/spec/build/bsps/arm/efm32gg11/optttys3ctrl.yml new file mode 100644 index 0000000000..3f82000a39 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3ctrl.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys3 usart extra ctl register bits (e.g. USART_CTRL_AUTOCS) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_CTRL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3ctsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys3ctsloc.yml new file mode 100644 index 0000000000..a9bafc9f17 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3ctsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys3 cts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_CTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3idx.yml b/spec/build/bsps/arm/efm32gg11/optttys3idx.yml new file mode 100644 index 0000000000..569fb143d0 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/ttyS3 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_DEVICE_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3rtsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys3rtsloc.yml new file mode 100644 index 0000000000..cacf521bdb --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3rtsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys3 rts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_RTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3rxloc.yml b/spec/build/bsps/arm/efm32gg11/optttys3rxloc.yml new file mode 100644 index 0000000000..c31e7e9d95 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys3 rx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3timing.yml b/spec/build/bsps/arm/efm32gg11/optttys3timing.yml new file mode 100644 index 0000000000..7a2c015c1a --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3timing.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys3 usart timing register +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_TIMING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3txloc.yml b/spec/build/bsps/arm/efm32gg11/optttys3txloc.yml new file mode 100644 index 0000000000..bdf9e71d18 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys3 tx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys3type.yml b/spec/build/bsps/arm/efm32gg11/optttys3type.yml new file mode 100644 index 0000000000..3de6c10b34 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys3type.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: USART +description: | + device type for /dev/ttyS3 (UART or USART) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS3_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4csloc.yml b/spec/build/bsps/arm/efm32gg11/optttys4csloc.yml new file mode 100644 index 0000000000..18d4e661e3 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4csloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys4 cs pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_CS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4ctrl.yml b/spec/build/bsps/arm/efm32gg11/optttys4ctrl.yml new file mode 100644 index 0000000000..7da855876e --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4ctrl.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys4 usart extra ctl register bits (e.g. USART_CTRL_AUTOCS) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_CTRL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4ctsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys4ctsloc.yml new file mode 100644 index 0000000000..f7ae5954ca --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4ctsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys4 cts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_CTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4idx.yml b/spec/build/bsps/arm/efm32gg11/optttys4idx.yml new file mode 100644 index 0000000000..4151b9e1d1 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/ttyS4 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_DEVICE_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4rtsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys4rtsloc.yml new file mode 100644 index 0000000000..7a1292c764 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4rtsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys4 rts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_RTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4rxloc.yml b/spec/build/bsps/arm/efm32gg11/optttys4rxloc.yml new file mode 100644 index 0000000000..585376c8a2 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys4 rx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4timing.yml b/spec/build/bsps/arm/efm32gg11/optttys4timing.yml new file mode 100644 index 0000000000..e96550601f --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4timing.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys4 usart timing register +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_TIMING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4txloc.yml b/spec/build/bsps/arm/efm32gg11/optttys4txloc.yml new file mode 100644 index 0000000000..bf8df1da73 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys4 tx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys4type.yml b/spec/build/bsps/arm/efm32gg11/optttys4type.yml new file mode 100644 index 0000000000..290bd5bbca --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys4type.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: USART +description: | + device type for /dev/ttyS4 (UART or USART) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS4_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5csloc.yml b/spec/build/bsps/arm/efm32gg11/optttys5csloc.yml new file mode 100644 index 0000000000..bd985575d4 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5csloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys5 cs pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_CS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5ctrl.yml b/spec/build/bsps/arm/efm32gg11/optttys5ctrl.yml new file mode 100644 index 0000000000..2eb9968681 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5ctrl.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys5 usart extra ctl register bits (e.g. USART_CTRL_AUTOCS) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_CTRL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5ctsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys5ctsloc.yml new file mode 100644 index 0000000000..3f244192ee --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5ctsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys5 cts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_CTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5idx.yml b/spec/build/bsps/arm/efm32gg11/optttys5idx.yml new file mode 100644 index 0000000000..4d3357239a --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/ttyS5 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_DEVICE_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5rtsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys5rtsloc.yml new file mode 100644 index 0000000000..c39b7aa1b7 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5rtsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys5 rts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_RTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5rxloc.yml b/spec/build/bsps/arm/efm32gg11/optttys5rxloc.yml new file mode 100644 index 0000000000..5fe7b71dde --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys5 rx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5timing.yml b/spec/build/bsps/arm/efm32gg11/optttys5timing.yml new file mode 100644 index 0000000000..baa7b7be18 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5timing.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys5 usart timing register +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_TIMING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5txloc.yml b/spec/build/bsps/arm/efm32gg11/optttys5txloc.yml new file mode 100644 index 0000000000..f18ea0d121 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys5 tx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys5type.yml b/spec/build/bsps/arm/efm32gg11/optttys5type.yml new file mode 100644 index 0000000000..27c15b5f2b --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys5type.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: USART +description: | + device type for /dev/ttyS5 (UART or USART) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS5_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6csloc.yml b/spec/build/bsps/arm/efm32gg11/optttys6csloc.yml new file mode 100644 index 0000000000..acf65c22c3 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6csloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys6 cs pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_CS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6ctrl.yml b/spec/build/bsps/arm/efm32gg11/optttys6ctrl.yml new file mode 100644 index 0000000000..daf8faa699 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6ctrl.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys6 usart extra ctl register bits (e.g. USART_CTRL_AUTOCS) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_CTRL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6ctsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys6ctsloc.yml new file mode 100644 index 0000000000..8c0fc362dc --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6ctsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys6 cts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_CTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6idx.yml b/spec/build/bsps/arm/efm32gg11/optttys6idx.yml new file mode 100644 index 0000000000..b4fb226208 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/ttyS6 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_DEVICE_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6rtsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys6rtsloc.yml new file mode 100644 index 0000000000..064806434e --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6rtsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys6 rts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_RTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6rxloc.yml b/spec/build/bsps/arm/efm32gg11/optttys6rxloc.yml new file mode 100644 index 0000000000..9c3187561c --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys6 rx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6timing.yml b/spec/build/bsps/arm/efm32gg11/optttys6timing.yml new file mode 100644 index 0000000000..2f16541bec --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6timing.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys6 usart timing register +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_TIMING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6txloc.yml b/spec/build/bsps/arm/efm32gg11/optttys6txloc.yml new file mode 100644 index 0000000000..b551b7bdd9 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys6 tx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys6type.yml b/spec/build/bsps/arm/efm32gg11/optttys6type.yml new file mode 100644 index 0000000000..dd063d836b --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys6type.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: USART +description: | + device type for /dev/ttyS6 (UART or USART) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS6_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7csloc.yml b/spec/build/bsps/arm/efm32gg11/optttys7csloc.yml new file mode 100644 index 0000000000..8cb2e3bdd5 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7csloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys7 cs pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_CS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7ctrl.yml b/spec/build/bsps/arm/efm32gg11/optttys7ctrl.yml new file mode 100644 index 0000000000..7540f0a8f1 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7ctrl.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys7 usart extra ctl register bits (e.g. USART_CTRL_AUTOCS) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_CTRL +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7ctsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys7ctsloc.yml new file mode 100644 index 0000000000..f9e6665514 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7ctsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys7 cts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_CTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7idx.yml b/spec/build/bsps/arm/efm32gg11/optttys7idx.yml new file mode 100644 index 0000000000..3d5cf8bf98 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7idx.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + device index for /dev/ttyS7 (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_DEVICE_INDEX +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7rtsloc.yml b/spec/build/bsps/arm/efm32gg11/optttys7rtsloc.yml new file mode 100644 index 0000000000..ee058c9c67 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7rtsloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys7 rts pin alt function location (disabled -1) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_RTS_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7rxloc.yml b/spec/build/bsps/arm/efm32gg11/optttys7rxloc.yml new file mode 100644 index 0000000000..beda6c39e0 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7rxloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys7 rx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_RX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7timing.yml b/spec/build/bsps/arm/efm32gg11/optttys7timing.yml new file mode 100644 index 0000000000..a360b2f5a7 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7timing.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: 0 +description: | + ttys7 usart timing register +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_TIMING +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7txloc.yml b/spec/build/bsps/arm/efm32gg11/optttys7txloc.yml new file mode 100644 index 0000000000..dd78d576d4 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7txloc.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: -1 +description: | + ttys7 tx pin alt function location +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_TX_LOC +type: build diff --git a/spec/build/bsps/arm/efm32gg11/optttys7type.yml b/spec/build/bsps/arm/efm32gg11/optttys7type.yml new file mode 100644 index 0000000000..a2936e9790 --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/optttys7type.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- define-unquoted: null +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: +- enabled-by: true + value: USART +description: | + device type for /dev/ttyS7 (UART or USART) +enabled-by: true +format: '{}' +links: [] +name: EFM32GG11_TTYS7_TYPE +type: build diff --git a/spec/build/bsps/arm/efm32gg11/tstefm32gg11.yml b/spec/build/bsps/arm/efm32gg11/tstefm32gg11.yml new file mode 100644 index 0000000000..b4e21511ab --- /dev/null +++ b/spec/build/bsps/arm/efm32gg11/tstefm32gg11.yml @@ -0,0 +1,27 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- set-test-state: + reason: null + state: exclude + tests: + - fsfatfssync01 + - fsfatfsformat01 + - fatfsfserror + - fatfsfspatheval + - fatfsfsrdwr + - fatfsfsrename + - fatfsfsrenamelongname + - fatfsfsrenameexisting + - fatfsfsrenamemaxlinks + - fatfsfsrmdirparent + - fatfsfsscandir01 + - fatfsfsstatvfs + - fatfsfstime +build-type: option +copyrights: +- Copyright (C) 2025 Allan N. Hessenflow +default: [] +description: '' +enabled-by: true +links: [] +type: build diff --git a/spec/build/cpukit/optlibdebugger.yml b/spec/build/cpukit/optlibdebugger.yml index 446a6be7e3..b610acad64 100644 --- a/spec/build/cpukit/optlibdebugger.yml +++ b/spec/build/cpukit/optlibdebugger.yml @@ -12,6 +12,7 @@ enabled-by: - and: - arm - not: bsps/arm/atsam + - not: bsps/arm/efm32gg11 - not: bsps/arm/imxrt - not: bsps/arm/lm3s69xx - not: bsps/arm/lpc176x diff --git a/spec/build/testsuites/libtests/dl13.yml b/spec/build/testsuites/libtests/dl13.yml index b0924af1ef..e6ebf14f53 100644 --- a/spec/build/testsuites/libtests/dl13.yml +++ b/spec/build/testsuites/libtests/dl13.yml @@ -29,6 +29,7 @@ enabled-by: - BUILD_LIBDL - arm - not: bsps/arm/atsam + - not: bsps/arm/efm32gg11 - not: bsps/arm/imxrt - not: bsps/arm/lm3s69xx - not: bsps/arm/lpc176x