From 8224b76f1a1d73c75e4f1b6963ad22cc5283b9b2 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Wed, 16 Feb 2011 08:27:14 +0000 Subject: [PATCH] 2011-02-16 Sebastian Huber * rtems/powerpc/registers.h: Added FSL_EIS_ATBL, FSL_EIS_ATBL, and FSL_EIS_SPEFSCR defines. --- cpukit/score/cpu/powerpc/ChangeLog | 5 +++++ cpukit/score/cpu/powerpc/rtems/powerpc/registers.h | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog index ef9bc12796..1d9117764e 100644 --- a/cpukit/score/cpu/powerpc/ChangeLog +++ b/cpukit/score/cpu/powerpc/ChangeLog @@ -1,3 +1,8 @@ +2011-02-16 Sebastian Huber + + * rtems/powerpc/registers.h: Added FSL_EIS_ATBL, FSL_EIS_ATBL, and + FSL_EIS_SPEFSCR defines. + 2011-02-15 Sebastian Huber * rtems/powerpc/registers.h: Added MSR_UCLE, MSR_SPE, MSR_WE, and diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h index b482abd345..fa193472dd 100644 --- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h +++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @@ -409,6 +409,15 @@ lidate */ #define FSL_EIS_L1CSR0 1010 #define FSL_EIS_L1CSR1 1011 +/* Freescale Book E Implementation Standards (EIS): Timer */ + +#define FSL_EIS_ATBL 526 +#define FSL_EIS_ATBU 527 + +/* Freescale Book E Implementation Standards (EIS): Signal Processing Engine (SPE) */ + +#define FSL_EIS_SPEFSCR 512 + /** * @brief Default value for the interrupt disable mask. *