From 6e83c388510913f5c272b7427b7e94475e89ec63 Mon Sep 17 00:00:00 2001 From: Mohamed Ayman Date: Sun, 15 Mar 2026 22:38:33 +0200 Subject: [PATCH] bsps/arm/stm32f4: fix HPRE bitfield Possible Bug in STM32F4 RCC header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix HPRE macro in cfgr register: original spanned bits 4–15, accidentally overwriting APB1/APB2 prescaler bits (10–15). Corrected range to 4–7, matching hardware specification. --- bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h index 97867f84a3..09a31ad9b7 100644 --- a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_rcc.h @@ -128,7 +128,7 @@ typedef struct { #define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5) #define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6) #define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7) -#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar +#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 7) // AHB prescalar #define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7) #define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) #define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0)