mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
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can: move drivers from cpukit to bsps/shared
Move CAN controllers from cputik to bsps/shared directory. This will allow to use BSP level interface which may be needed for some controllers. Generic CAN stack implementation is still kept in the original directory as this shoudl be independent from the low level driver interface. Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit is contained in:
Michal Lenc
committed by
Kinsey Moore
Kinsey Moore
parent
641f589b37
commit
5ebf57e2af
@@ -0,0 +1,281 @@
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/* SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0 OR GPL-2.0-or-later */
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/**
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* @file
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*
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* @ingroup CANVirtual
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*
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* @brief This file implements virtual CAN chip.
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*
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* Implementation is based on original LinCAN - Linux CAN bus driver
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* Part of OrtCAN project https://ortcan.sourceforge.net/
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*/
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/*
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* Copyright (C) 2023-2024 Michal Lenc <michallenc@seznam.cz>
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* Copyright (C) 2002-2009 DCE FEE CTU Prague
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* Copyright (C) 2002-2024 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**************************************************************************/
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#include <stdlib.h>
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#include <rtems.h>
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#include <rtems/malloc.h>
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#include <rtems/score/basedefs.h>
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#include <dev/can/can-virtual.h>
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#include <dev/can/can-helpers.h>
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#include <dev/can/can-devcommon.h>
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#include <dev/can/can.h>
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#define CAN_VIRTUAL_PRIORITY 120
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static rtems_task virtual_worker( rtems_task_argument arg )
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{
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struct rtems_can_chip *chip = (struct rtems_can_chip *) arg;
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struct rtems_can_queue_ends_dev *qends_dev = chip->qends_dev;
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struct rtems_can_queue_ends *qends = &qends_dev->base;
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struct rtems_can_queue_edge *qedge;
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struct rtems_can_queue_slot *slot;
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int cmd;
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while ( 1 ) {
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while (
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( cmd = rtems_can_queue_test_outslot( qends, &qedge, &slot ) ) >= 0
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) {
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if ( rtems_can_test_bit( RTEMS_CAN_CHIP_RUNNING, &chip->flags ) == 0 ) {
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if ( cmd >= 0 ) {
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rtems_can_queue_filter_frame_to_edges(
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qends,
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qedge,
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&slot->frame,
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CAN_FRAME_TXERR
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);
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rtems_can_stats_add_tx_error( &chip->chip_stats );
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} else {
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rtems_binary_semaphore_post( &chip->stop_sem );
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}
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} else if ( cmd >= 0 ) {
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/* fill CAN message timestamp */
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slot->frame.header.timestamp = rtems_can_fill_timestamp();
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rtems_can_queue_filter_frame_to_edges(
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qends,
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qedge,
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&slot->frame,
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CAN_FRAME_LOCAL
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);
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rtems_can_stats_add_tx_done( &chip->chip_stats );
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rtems_can_stats_add_rx_done( &chip->chip_stats );
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}
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rtems_can_queue_free_outslot( qends, qedge, slot );
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}
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rtems_binary_semaphore_wait( &qends_dev->worker_sem );
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}
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}
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static int virtual_get_chip_info( struct rtems_can_chip *chip, int what )
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{
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int ret;
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switch ( what ) {
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case RTEMS_CAN_CHIP_BITRATE:
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case RTEMS_CAN_CHIP_DBITRATE:
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ret = -EINVAL;
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break;
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case RTEMS_CAN_CHIP_NUSERS:
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ret = atomic_load( &chip->used );
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break;
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case RTEMS_CAN_CHIP_FLAGS:
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ret = atomic_load( &chip->flags );
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/**
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* @brief This function implements chip specific ioctl calls.
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*
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* @param chip Pointer to chip structure.
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* @param command IOCTL command
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* @param arg Void pointer to IOCL argument
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*
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* @return Negative value on error.
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*/
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static int virtual_chip_ioctl(
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struct rtems_can_chip *chip,
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ioctl_command_t command,
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void *arg
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)
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{
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(void) chip;
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(void) arg;
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int ret;
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switch ( command ) {
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int virtual_stop_chip(
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struct rtems_can_chip *chip,
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struct timespec *ts
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)
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{
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rtems_interval timeout;
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struct timespec curr;
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struct timespec final;
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struct timespec towait;
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int ret;
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rtems_mutex_lock( &chip->lock );
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if ( rtems_can_test_bit( RTEMS_CAN_CHIP_RUNNING, &chip->flags ) == 0 ) {
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/* Already stopped, return. */
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rtems_mutex_unlock( &chip->lock );
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return 0;
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}
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rtems_can_clear_bit( RTEMS_CAN_CHIP_RUNNING, &chip->flags );
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rtems_binary_semaphore_post( &chip->qends_dev->worker_sem );
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if ( ts != NULL ) {
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/* Get absolute monotonic final time */
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clock_gettime( CLOCK_MONOTONIC, &final );
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rtems_timespec_add_to( &final, ts );
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clock_gettime( CLOCK_MONOTONIC, &curr );
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rtems_timespec_subtract( &curr, &final, &towait );
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if ( towait.tv_sec < 0 ) {
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ret = rtems_binary_semaphore_try_wait( &chip->stop_sem );
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} else {
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timeout = rtems_timespec_to_ticks( &towait );
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ret = rtems_binary_semaphore_wait_timed_ticks(
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&chip->stop_sem,
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timeout
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);
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}
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} else {
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ret = rtems_binary_semaphore_try_wait( &chip->stop_sem );
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}
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if ( ret < 0 ) {
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rtems_can_queue_ends_flush_outlist( &chip->qends_dev->base );
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}
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rtems_binary_semaphore_post( &chip->qends_dev->worker_sem );
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rtems_can_stats_set_state( &chip->chip_stats, CAN_STATE_STOPPED );
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rtems_can_bus_notify_chip_stop( chip );
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rtems_mutex_unlock( &chip->lock );
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return 0;
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}
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static int virtual_start_chip( struct rtems_can_chip *chip )
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{
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rtems_mutex_lock( &chip->lock );
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if ( rtems_can_test_bit( RTEMS_CAN_CHIP_RUNNING, &chip->flags ) ) {
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/* Chip was already started, skip */
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rtems_mutex_unlock( &chip->lock );
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return 0;
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}
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rtems_can_set_bit( RTEMS_CAN_CHIP_RUNNING, &chip->flags );
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rtems_can_stats_reset( &chip->chip_stats );
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rtems_can_stats_set_state( &chip->chip_stats, CAN_STATE_ERROR_ACTIVE );
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rtems_mutex_unlock( &chip->lock );
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return 0;
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}
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static void virtual_register( struct rtems_can_chip_ops *chip_ops )
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{
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chip_ops->start_chip = virtual_start_chip;
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chip_ops->stop_chip = virtual_stop_chip;
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chip_ops->chip_ioctl = virtual_chip_ioctl;
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chip_ops->get_chip_timestamp = NULL;
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chip_ops->get_chip_info = virtual_get_chip_info;
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}
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struct rtems_can_chip *rtems_can_virtual_initialize( void )
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{
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rtems_id worker_task_id;
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rtems_status_code sc;
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struct rtems_can_chip *chip;
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chip = calloc( 1, sizeof( struct rtems_can_chip ) );
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if ( !chip ) {
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return NULL;
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}
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chip->type = CAN_VIRTUAL_TYPE;
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chip->capabilities = RTEMS_CAN_CHIP_CAPABILITIES_FD;
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chip->irq = 0;
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chip->qends_dev = calloc( 1, sizeof( struct rtems_can_queue_ends_dev ) );
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if ( !chip->qends_dev ) {
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free( chip );
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return NULL;
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}
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rtems_mutex_init( &chip->lock, "virtual_lock" );
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rtems_binary_semaphore_init( &chip->stop_sem, "can_virtual_stop_sem" );
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rtems_can_queue_ends_init_chip( chip, "can_virtual_worker" );
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sc = rtems_task_create(
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rtems_build_name( 'C', 'A', 'N', 'V' ),
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CAN_VIRTUAL_PRIORITY,
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RTEMS_MINIMUM_STACK_SIZE + 0x1000,
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RTEMS_DEFAULT_MODES,
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RTEMS_DEFAULT_ATTRIBUTES,
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&worker_task_id
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);
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if ( sc != RTEMS_SUCCESSFUL ) {
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free( chip->qends_dev );
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free( chip );
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return NULL;
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}
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rtems_task_start(
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worker_task_id,
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virtual_worker,
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(rtems_task_argument) chip
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);
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virtual_register( &chip->chip_ops );
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rtems_can_set_bit( RTEMS_CAN_CHIP_CONFIGURED, &chip->flags );
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rtems_can_stats_set_state( &chip->chip_stats, CAN_STATE_STOPPED );
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return chip;
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,146 @@
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/* SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0 OR GPL-2.0-or-later */
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/**
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* @file
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*
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* @ingroup CTUCANFD
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*
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* @brief This file is part of CTU CAN FD core driver implementation.
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*/
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/*
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* Copyright (C) 2023-2024 Michal Lenc <michallenc@seznam.cz>
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* Implementation is based on Linux CTU CAN FD driver
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* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
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* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
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* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
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* Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CTUCANFD_INTERNAL_H
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#define __CTUCANFD_INTERNAL_H
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#include <dev/can/can-queue.h>
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#include <dev/can/can-helpers.h>
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#include <dev/can/ctucanfd.h>
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#include "ctucanfd_kregs.h"
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/**
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* @brief This represents one HW transmission buffer.
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*/
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struct ctucanfd_txb_info {
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/**
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* @brief This holds the pointer to the slot the buffer acquired.
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*
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* The stack does not free the slot immediately after it is assigned to
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* the buffer, but waits for successful transmission (or error/abort). Hence
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* the buffer has to keep the information about the slot it acquired to
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* provide correct error reporting or to schedule it for later processing.
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*/
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struct rtems_can_queue_slot *slot;
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/**
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* @brief This holds the pointer to the edge from which the slot was
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* acquired.
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*
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* This information is useful for future filtering of echo frames back to
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* sending instances.
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*/
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struct rtems_can_queue_edge *edge;
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};
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/**
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* @brief This represents internal CTU CAN FD structure.
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*
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* This structure is CTU CAN FD controller dependent and provides
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* access to non generic parts that do not belong to generic
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* @ref rtems_can_chip structure.
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*/
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struct ctucanfd_internal {
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/**
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* @brief Base memory address.
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*/
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uintptr_t base;
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/**
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* @brief This member holds the enabled interrupts.
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*/
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uint32_t int_ena;
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/**
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* @brief This member holds the masked out interrupts.
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*/
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uint32_t int_mask;
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/**
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* @brief This member holds the array of @ref ctucanfd_txb_info structures.
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*/
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struct ctucanfd_txb_info txb_info[ RTEMS_CTUCANFD_NTXBUFS_MAX ];
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/**
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* @brief This member holds tails for mapping of priority classes to bufders.
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*
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* These are the positions where buffers with frames from given priority
|
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* class should be inserted.
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*/
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uint8_t txb_prio_tail[ RTEMS_CAN_QUEUE_PRIO_NR ];
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/**
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* @brief This member holds the order in which the buffers should be
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* scheduled for transmisison.
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*/
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uint32_t txb_order;
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/**
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* @brief This member holds the number of TX buffers for given core.
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*/
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unsigned int ntxbufs;
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};
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static inline void ctucanfd_write32(
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struct ctucanfd_internal *internal,
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enum ctu_can_fd_can_registers reg,
|
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uint32_t val
|
||||
)
|
||||
{
|
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*(volatile uint32_t *) ( internal->base + reg ) = val;
|
||||
}
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static inline uint32_t ctucanfd_read32(
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struct ctucanfd_internal *internal,
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enum ctu_can_fd_can_registers reg
|
||||
)
|
||||
{
|
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return *(volatile uint32_t *) ( internal->base + reg );
|
||||
}
|
||||
|
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static inline void ctucanfd_write_txt_buf(
|
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struct ctucanfd_internal *internal,
|
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enum ctu_can_fd_can_registers buf_base,
|
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uint32_t offset,
|
||||
uint32_t val
|
||||
)
|
||||
{
|
||||
*(volatile uint32_t *) ( internal->base + buf_base + offset ) = val;
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||||
}
|
||||
|
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#define CTU_CAN_FD_ENABLED( internal ) \
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( !!FIELD_GET( REG_MODE_ENA, ctucanfd_read32( internal, CTUCANFD_MODE ) ) )
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#endif /* __CTUCANFD_PRIV_H */
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@@ -0,0 +1,77 @@
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/* SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0 OR GPL-2.0-or-later */
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/*******************************************************************************
|
||||
*
|
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* CTU CAN FD IP Core
|
||||
*
|
||||
* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
|
||||
* Copyright (C) 2018-2021 Ondrej Ille <ondrej.ille@gmail.com> self-funded
|
||||
* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
|
||||
* Copyright (C) 2018-2021 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
|
||||
*
|
||||
* Project advisors:
|
||||
* Jiri Novak <jnovak@fel.cvut.cz>
|
||||
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
||||
*
|
||||
* Department of Measurement (http://meas.fel.cvut.cz/)
|
||||
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
|
||||
* Czech Technical University (http://www.cvut.cz/)
|
||||
******************************************************************************/
|
||||
|
||||
/* This file is autogenerated, DO NOT EDIT! */
|
||||
|
||||
#ifndef __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
|
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#define __CTU_CAN_FD_CAN_FD_FRAME_FORMAT__
|
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|
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#include <dev/can/can-helpers.h>
|
||||
|
||||
/* CAN_Frame_format memory map */
|
||||
enum ctu_can_fd_can_frame_format {
|
||||
CTUCANFD_FRAME_FORMAT_W = 0x0,
|
||||
CTUCANFD_IDENTIFIER_W = 0x4,
|
||||
CTUCANFD_TIMESTAMP_L_W = 0x8,
|
||||
CTUCANFD_TIMESTAMP_U_W = 0xc,
|
||||
CTUCANFD_DATA_1_4_W = 0x10,
|
||||
CTUCANFD_DATA_5_8_W = 0x14,
|
||||
CTUCANFD_DATA_61_64_W = 0x4c,
|
||||
};
|
||||
|
||||
/* CAN_FD_Frame_format memory region */
|
||||
|
||||
/* FRAME_FORMAT_W registers */
|
||||
#define REG_FRAME_FORMAT_W_DLC GENMASK( 3, 0 )
|
||||
#define REG_FRAME_FORMAT_W_RTR BIT( 5 )
|
||||
#define REG_FRAME_FORMAT_W_IDE BIT( 6 )
|
||||
#define REG_FRAME_FORMAT_W_FDF BIT( 7 )
|
||||
#define REG_FRAME_FORMAT_W_BRS BIT( 9 )
|
||||
#define REG_FRAME_FORMAT_W_ESI_RSV BIT( 10 )
|
||||
#define REG_FRAME_FORMAT_W_RWCNT GENMASK( 15, 11 )
|
||||
|
||||
/* IDENTIFIER_W registers */
|
||||
#define REG_IDENTIFIER_W_IDENTIFIER_EXT GENMASK( 17, 0 )
|
||||
#define REG_IDENTIFIER_W_IDENTIFIER_BASE GENMASK( 28, 18 )
|
||||
|
||||
/* TIMESTAMP_L_W registers */
|
||||
#define REG_TIMESTAMP_L_W_TIME_STAMP_L_W GENMASK( 31, 0 )
|
||||
|
||||
/* TIMESTAMP_U_W registers */
|
||||
#define REG_TIMESTAMP_U_W_TIMESTAMP_U_W GENMASK( 31, 0 )
|
||||
|
||||
/* DATA_1_4_W registers */
|
||||
#define REG_DATA_1_4_W_DATA_1 GENMASK( 7, 0 )
|
||||
#define REG_DATA_1_4_W_DATA_2 GENMASK( 15, 8 )
|
||||
#define REG_DATA_1_4_W_DATA_3 GENMASK( 23, 16 )
|
||||
#define REG_DATA_1_4_W_DATA_4 GENMASK( 31, 24 )
|
||||
|
||||
/* DATA_5_8_W registers */
|
||||
#define REG_DATA_5_8_W_DATA_5 GENMASK( 7, 0 )
|
||||
#define REG_DATA_5_8_W_DATA_6 GENMASK( 15, 8 )
|
||||
#define REG_DATA_5_8_W_DATA_7 GENMASK( 23, 16 )
|
||||
#define REG_DATA_5_8_W_DATA_8 GENMASK( 31, 24 )
|
||||
|
||||
/* DATA_61_64_W registers */
|
||||
#define REG_DATA_61_64_W_DATA_61 GENMASK( 7, 0 )
|
||||
#define REG_DATA_61_64_W_DATA_62 GENMASK( 15, 8 )
|
||||
#define REG_DATA_61_64_W_DATA_63 GENMASK( 23, 16 )
|
||||
#define REG_DATA_61_64_W_DATA_64 GENMASK( 31, 24 )
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,349 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0 OR GPL-2.0-or-later */
|
||||
/*******************************************************************************
|
||||
*
|
||||
* CTU CAN FD IP Core
|
||||
*
|
||||
* Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
|
||||
* Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded
|
||||
* Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
|
||||
* Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
|
||||
*
|
||||
* Project advisors:
|
||||
* Jiri Novak <jnovak@fel.cvut.cz>
|
||||
* Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
||||
*
|
||||
* Department of Measurement (http://meas.fel.cvut.cz/)
|
||||
* Faculty of Electrical Engineering (http://www.fel.cvut.cz)
|
||||
* Czech Technical University (http://www.cvut.cz/)
|
||||
******************************************************************************/
|
||||
|
||||
/* This file is autogenerated, DO NOT EDIT! */
|
||||
|
||||
#ifndef __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
|
||||
#define __CTU_CAN_FD_CAN_FD_REGISTER_MAP__
|
||||
|
||||
#include <dev/can/can-helpers.h>
|
||||
|
||||
/* CAN_Registers memory map */
|
||||
enum ctu_can_fd_can_registers {
|
||||
CTUCANFD_DEVICE_ID = 0x0,
|
||||
CTUCANFD_VERSION = 0x2,
|
||||
CTUCANFD_MODE = 0x4,
|
||||
CTUCANFD_SETTINGS = 0x6,
|
||||
CTUCANFD_STATUS = 0x8,
|
||||
CTUCANFD_COMMAND = 0xc,
|
||||
CTUCANFD_INT_STAT = 0x10,
|
||||
CTUCANFD_INT_ENA_SET = 0x14,
|
||||
CTUCANFD_INT_ENA_CLR = 0x18,
|
||||
CTUCANFD_INT_MASK_SET = 0x1c,
|
||||
CTUCANFD_INT_MASK_CLR = 0x20,
|
||||
CTUCANFD_BTR = 0x24,
|
||||
CTUCANFD_BTR_FD = 0x28,
|
||||
CTUCANFD_EWL = 0x2c,
|
||||
CTUCANFD_ERP = 0x2d,
|
||||
CTUCANFD_FAULT_STATE = 0x2e,
|
||||
CTUCANFD_REC = 0x30,
|
||||
CTUCANFD_TEC = 0x32,
|
||||
CTUCANFD_ERR_NORM = 0x34,
|
||||
CTUCANFD_ERR_FD = 0x36,
|
||||
CTUCANFD_CTR_PRES = 0x38,
|
||||
CTUCANFD_FILTER_A_MASK = 0x3c,
|
||||
CTUCANFD_FILTER_A_VAL = 0x40,
|
||||
CTUCANFD_FILTER_B_MASK = 0x44,
|
||||
CTUCANFD_FILTER_B_VAL = 0x48,
|
||||
CTUCANFD_FILTER_C_MASK = 0x4c,
|
||||
CTUCANFD_FILTER_C_VAL = 0x50,
|
||||
CTUCANFD_FILTER_RAN_LOW = 0x54,
|
||||
CTUCANFD_FILTER_RAN_HIGH = 0x58,
|
||||
CTUCANFD_FILTER_CONTROL = 0x5c,
|
||||
CTUCANFD_FILTER_STATUS = 0x5e,
|
||||
CTUCANFD_RX_MEM_INFO = 0x60,
|
||||
CTUCANFD_RX_POINTERS = 0x64,
|
||||
CTUCANFD_RX_STATUS = 0x68,
|
||||
CTUCANFD_RX_SETTINGS = 0x6a,
|
||||
CTUCANFD_RX_DATA = 0x6c,
|
||||
CTUCANFD_TX_STATUS = 0x70,
|
||||
CTUCANFD_TX_COMMAND = 0x74,
|
||||
CTUCANFD_TXTB_INFO = 0x76,
|
||||
CTUCANFD_TX_PRIORITY = 0x78,
|
||||
CTUCANFD_ERR_CAPT = 0x7c,
|
||||
CTUCANFD_RETR_CTR = 0x7d,
|
||||
CTUCANFD_ALC = 0x7e,
|
||||
CTUCANFD_TS_INFO = 0x7f,
|
||||
CTUCANFD_TRV_DELAY = 0x80,
|
||||
CTUCANFD_SSP_CFG = 0x82,
|
||||
CTUCANFD_RX_FR_CTR = 0x84,
|
||||
CTUCANFD_TX_FR_CTR = 0x88,
|
||||
CTUCANFD_DEBUG_REGISTER = 0x8c,
|
||||
CTUCANFD_YOLO_REG = 0x90,
|
||||
CTUCANFD_TIMESTAMP_LOW = 0x94,
|
||||
CTUCANFD_TIMESTAMP_HIGH = 0x98,
|
||||
CTUCANFD_TXTB1_DATA_1 = 0x100,
|
||||
CTUCANFD_TXTB1_DATA_2 = 0x104,
|
||||
CTUCANFD_TXTB1_DATA_20 = 0x14c,
|
||||
CTUCANFD_TXTB2_DATA_1 = 0x200,
|
||||
CTUCANFD_TXTB2_DATA_2 = 0x204,
|
||||
CTUCANFD_TXTB2_DATA_20 = 0x24c,
|
||||
CTUCANFD_TXTB3_DATA_1 = 0x300,
|
||||
CTUCANFD_TXTB3_DATA_2 = 0x304,
|
||||
CTUCANFD_TXTB3_DATA_20 = 0x34c,
|
||||
CTUCANFD_TXTB4_DATA_1 = 0x400,
|
||||
CTUCANFD_TXTB4_DATA_2 = 0x404,
|
||||
CTUCANFD_TXTB4_DATA_20 = 0x44c,
|
||||
};
|
||||
|
||||
/* Control_registers memory region */
|
||||
|
||||
/* DEVICE_ID VERSION registers */
|
||||
#define REG_DEVICE_ID_DEVICE_ID GENMASK( 15, 0 )
|
||||
#define REG_DEVICE_ID_VER_MINOR GENMASK( 23, 16 )
|
||||
#define REG_DEVICE_ID_VER_MAJOR GENMASK( 31, 24 )
|
||||
|
||||
/* MODE SETTINGS registers */
|
||||
#define REG_MODE_RST BIT( 0 )
|
||||
#define REG_MODE_BMM BIT( 1 )
|
||||
#define REG_MODE_STM BIT( 2 )
|
||||
#define REG_MODE_AFM BIT( 3 )
|
||||
#define REG_MODE_FDE BIT( 4 )
|
||||
#define REG_MODE_TTTM BIT( 5 )
|
||||
#define REG_MODE_ROM BIT( 6 )
|
||||
#define REG_MODE_ACF BIT( 7 )
|
||||
#define REG_MODE_TSTM BIT( 8 )
|
||||
#define REG_MODE_RXBAM BIT( 9 )
|
||||
#define REG_MODE_SAM BIT( 11 )
|
||||
#define REG_MODE_RTRLE BIT( 16 )
|
||||
#define REG_MODE_RTRTH GENMASK( 20, 17 )
|
||||
#define REG_MODE_ILBP BIT( 21 )
|
||||
#define REG_MODE_ENA BIT( 22 )
|
||||
#define REG_MODE_NISOFD BIT( 23 )
|
||||
#define REG_MODE_PEX BIT( 24 )
|
||||
#define REG_MODE_TBFBO BIT( 25 )
|
||||
#define REG_MODE_FDRF BIT( 26 )
|
||||
|
||||
/* STATUS registers */
|
||||
#define REG_STATUS_RXNE BIT( 0 )
|
||||
#define REG_STATUS_DOR BIT( 1 )
|
||||
#define REG_STATUS_TXNF BIT( 2 )
|
||||
#define REG_STATUS_EFT BIT( 3 )
|
||||
#define REG_STATUS_RXS BIT( 4 )
|
||||
#define REG_STATUS_TXS BIT( 5 )
|
||||
#define REG_STATUS_EWL BIT( 6 )
|
||||
#define REG_STATUS_IDLE BIT( 7 )
|
||||
#define REG_STATUS_PEXS BIT( 8 )
|
||||
#define REG_STATUS_STCNT BIT( 16 )
|
||||
|
||||
/* COMMAND registers */
|
||||
#define REG_COMMAND_RXRPMV BIT( 1 )
|
||||
#define REG_COMMAND_RRB BIT( 2 )
|
||||
#define REG_COMMAND_CDO BIT( 3 )
|
||||
#define REG_COMMAND_ERCRST BIT( 4 )
|
||||
#define REG_COMMAND_RXFCRST BIT( 5 )
|
||||
#define REG_COMMAND_TXFCRST BIT( 6 )
|
||||
#define REG_COMMAND_CPEXS BIT( 7 )
|
||||
|
||||
/* INT_STAT registers */
|
||||
#define REG_INT_STAT_RXI BIT( 0 )
|
||||
#define REG_INT_STAT_TXI BIT( 1 )
|
||||
#define REG_INT_STAT_EWLI BIT( 2 )
|
||||
#define REG_INT_STAT_DOI BIT( 3 )
|
||||
#define REG_INT_STAT_FCSI BIT( 4 )
|
||||
#define REG_INT_STAT_ALI BIT( 5 )
|
||||
#define REG_INT_STAT_BEI BIT( 6 )
|
||||
#define REG_INT_STAT_OFI BIT( 7 )
|
||||
#define REG_INT_STAT_RXFI BIT( 8 )
|
||||
#define REG_INT_STAT_BSI BIT( 9 )
|
||||
#define REG_INT_STAT_RBNEI BIT( 10 )
|
||||
#define REG_INT_STAT_TXBHCI BIT( 11 )
|
||||
|
||||
/* INT_ENA_SET registers */
|
||||
#define REG_INT_ENA_SET_INT_ENA_SET GENMASK( 11, 0 )
|
||||
|
||||
/* INT_ENA_CLR registers */
|
||||
#define REG_INT_ENA_CLR_INT_ENA_CLR GENMASK( 11, 0 )
|
||||
|
||||
/* INT_MASK_SET registers */
|
||||
#define REG_INT_MASK_SET_INT_MASK_SET GENMASK( 11, 0 )
|
||||
|
||||
/* INT_MASK_CLR registers */
|
||||
#define REG_INT_MASK_CLR_INT_MASK_CLR GENMASK( 11, 0 )
|
||||
|
||||
/* BTR registers */
|
||||
#define REG_BTR_PROP GENMASK( 6, 0 )
|
||||
#define REG_BTR_PH1 GENMASK( 12, 7 )
|
||||
#define REG_BTR_PH2 GENMASK( 18, 13 )
|
||||
#define REG_BTR_BRP GENMASK( 26, 19 )
|
||||
#define REG_BTR_SJW GENMASK( 31, 27 )
|
||||
|
||||
/* BTR_FD registers */
|
||||
#define REG_BTR_FD_PROP_FD GENMASK( 5, 0 )
|
||||
#define REG_BTR_FD_PH1_FD GENMASK( 11, 7 )
|
||||
#define REG_BTR_FD_PH2_FD GENMASK( 17, 13 )
|
||||
#define REG_BTR_FD_BRP_FD GENMASK( 26, 19 )
|
||||
#define REG_BTR_FD_SJW_FD GENMASK( 31, 27 )
|
||||
|
||||
/* EWL ERP FAULT_STATE registers */
|
||||
#define REG_EWL_EW_LIMIT GENMASK( 7, 0 )
|
||||
#define REG_EWL_ERP_LIMIT GENMASK( 15, 8 )
|
||||
#define REG_EWL_ERA BIT( 16 )
|
||||
#define REG_EWL_ERP BIT( 17 )
|
||||
#define REG_EWL_BOF BIT( 18 )
|
||||
|
||||
/* REC TEC registers */
|
||||
#define REG_REC_REC_VAL GENMASK( 8, 0 )
|
||||
#define REG_REC_TEC_VAL GENMASK( 24, 16 )
|
||||
|
||||
/* ERR_NORM ERR_FD registers */
|
||||
#define REG_ERR_NORM_ERR_NORM_VAL GENMASK( 15, 0 )
|
||||
#define REG_ERR_NORM_ERR_FD_VAL GENMASK( 31, 16 )
|
||||
|
||||
/* CTR_PRES registers */
|
||||
#define REG_CTR_PRES_CTPV GENMASK( 8, 0 )
|
||||
#define REG_CTR_PRES_PTX BIT( 9 )
|
||||
#define REG_CTR_PRES_PRX BIT( 10 )
|
||||
#define REG_CTR_PRES_ENORM BIT( 11 )
|
||||
#define REG_CTR_PRES_EFD BIT( 12 )
|
||||
|
||||
/* FILTER_A_MASK registers */
|
||||
#define REG_FILTER_A_MASK_BIT_MASK_A_VAL GENMASK( 28, 0 )
|
||||
|
||||
/* FILTER_A_VAL registers */
|
||||
#define REG_FILTER_A_VAL_BIT_VAL_A_VAL GENMASK( 28, 0 )
|
||||
|
||||
/* FILTER_B_MASK registers */
|
||||
#define REG_FILTER_B_MASK_BIT_MASK_B_VAL GENMASK( 28, 0 )
|
||||
|
||||
/* FILTER_B_VAL registers */
|
||||
#define REG_FILTER_B_VAL_BIT_VAL_B_VAL GENMASK( 28, 0 )
|
||||
|
||||
/* FILTER_C_MASK registers */
|
||||
#define REG_FILTER_C_MASK_BIT_MASK_C_VAL GENMASK( 28, 0 )
|
||||
|
||||
/* FILTER_C_VAL registers */
|
||||
#define REG_FILTER_C_VAL_BIT_VAL_C_VAL GENMASK( 28, 0 )
|
||||
|
||||
/* FILTER_RAN_LOW registers */
|
||||
#define REG_FILTER_RAN_LOW_BIT_RAN_LOW_VAL GENMASK( 28, 0 )
|
||||
|
||||
/* FILTER_RAN_HIGH registers */
|
||||
#define REG_FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL GENMASK( 28, 0 )
|
||||
|
||||
/* FILTER_CONTROL FILTER_STATUS registers */
|
||||
#define REG_FILTER_CONTROL_FANB BIT( 0 )
|
||||
#define REG_FILTER_CONTROL_FANE BIT( 1 )
|
||||
#define REG_FILTER_CONTROL_FAFB BIT( 2 )
|
||||
#define REG_FILTER_CONTROL_FAFE BIT( 3 )
|
||||
#define REG_FILTER_CONTROL_FBNB BIT( 4 )
|
||||
#define REG_FILTER_CONTROL_FBNE BIT( 5 )
|
||||
#define REG_FILTER_CONTROL_FBFB BIT( 6 )
|
||||
#define REG_FILTER_CONTROL_FBFE BIT( 7 )
|
||||
#define REG_FILTER_CONTROL_FCNB BIT( 8 )
|
||||
#define REG_FILTER_CONTROL_FCNE BIT( 9 )
|
||||
#define REG_FILTER_CONTROL_FCFB BIT( 10 )
|
||||
#define REG_FILTER_CONTROL_FCFE BIT( 11 )
|
||||
#define REG_FILTER_CONTROL_FRNB BIT( 12 )
|
||||
#define REG_FILTER_CONTROL_FRNE BIT( 13 )
|
||||
#define REG_FILTER_CONTROL_FRFB BIT( 14 )
|
||||
#define REG_FILTER_CONTROL_FRFE BIT( 15 )
|
||||
#define REG_FILTER_CONTROL_SFA BIT( 16 )
|
||||
#define REG_FILTER_CONTROL_SFB BIT( 17 )
|
||||
#define REG_FILTER_CONTROL_SFC BIT( 18 )
|
||||
#define REG_FILTER_CONTROL_SFR BIT( 19 )
|
||||
|
||||
/* RX_MEM_INFO registers */
|
||||
#define REG_RX_MEM_INFO_RX_BUFF_SIZE GENMASK( 12, 0 )
|
||||
#define REG_RX_MEM_INFO_RX_MEM_FREE GENMASK( 28, 16 )
|
||||
|
||||
/* RX_POINTERS registers */
|
||||
#define REG_RX_POINTERS_RX_WPP GENMASK( 11, 0 )
|
||||
#define REG_RX_POINTERS_RX_RPP GENMASK( 27, 16 )
|
||||
|
||||
/* RX_STATUS RX_SETTINGS registers */
|
||||
#define REG_RX_STATUS_RXE BIT( 0 )
|
||||
#define REG_RX_STATUS_RXF BIT( 1 )
|
||||
#define REG_RX_STATUS_RXMOF BIT( 2 )
|
||||
#define REG_RX_STATUS_RXFRC GENMASK( 14, 4 )
|
||||
#define REG_RX_STATUS_RTSOP BIT( 16 )
|
||||
|
||||
/* RX_DATA registers */
|
||||
#define REG_RX_DATA_RX_DATA GENMASK( 31, 0 )
|
||||
|
||||
/* TX_STATUS registers */
|
||||
#define REG_TX_STATUS_TX1S GENMASK( 3, 0 )
|
||||
#define REG_TX_STATUS_TX2S GENMASK( 7, 4 )
|
||||
#define REG_TX_STATUS_TX3S GENMASK( 11, 8 )
|
||||
#define REG_TX_STATUS_TX4S GENMASK( 15, 12 )
|
||||
#define REG_TX_STATUS_TX5S GENMASK( 19, 16 )
|
||||
#define REG_TX_STATUS_TX6S GENMASK( 23, 20 )
|
||||
#define REG_TX_STATUS_TX7S GENMASK( 27, 24 )
|
||||
#define REG_TX_STATUS_TX8S GENMASK( 31, 28 )
|
||||
|
||||
/* TX_COMMAND TXTB_INFO registers */
|
||||
#define REG_TX_COMMAND_TXCE BIT( 0 )
|
||||
#define REG_TX_COMMAND_TXCR BIT( 1 )
|
||||
#define REG_TX_COMMAND_TXCA BIT( 2 )
|
||||
#define REG_TX_COMMAND_TXB1 BIT( 8 )
|
||||
#define REG_TX_COMMAND_TXB2 BIT( 9 )
|
||||
#define REG_TX_COMMAND_TXB3 BIT( 10 )
|
||||
#define REG_TX_COMMAND_TXB4 BIT( 11 )
|
||||
#define REG_TX_COMMAND_TXB5 BIT( 12 )
|
||||
#define REG_TX_COMMAND_TXB6 BIT( 13 )
|
||||
#define REG_TX_COMMAND_TXB7 BIT( 14 )
|
||||
#define REG_TX_COMMAND_TXB8 BIT( 15 )
|
||||
#define REG_TX_COMMAND_TXT_BUFFER_COUNT GENMASK( 19, 16 )
|
||||
|
||||
/* TX_PRIORITY registers */
|
||||
#define REG_TX_PRIORITY_TXT1P GENMASK( 2, 0 )
|
||||
#define REG_TX_PRIORITY_TXT2P GENMASK( 6, 4 )
|
||||
#define REG_TX_PRIORITY_TXT3P GENMASK( 10, 8 )
|
||||
#define REG_TX_PRIORITY_TXT4P GENMASK( 14, 12 )
|
||||
#define REG_TX_PRIORITY_TXT5P GENMASK( 18, 16 )
|
||||
#define REG_TX_PRIORITY_TXT6P GENMASK( 22, 20 )
|
||||
#define REG_TX_PRIORITY_TXT7P GENMASK( 26, 24 )
|
||||
#define REG_TX_PRIORITY_TXT8P GENMASK( 30, 28 )
|
||||
|
||||
/* ERR_CAPT RETR_CTR ALC TS_INFO registers */
|
||||
#define REG_ERR_CAPT_ERR_POS GENMASK( 4, 0 )
|
||||
#define REG_ERR_CAPT_ERR_TYPE GENMASK( 7, 5 )
|
||||
#define REG_ERR_CAPT_RETR_CTR_VAL GENMASK( 11, 8 )
|
||||
#define REG_ERR_CAPT_ALC_BIT GENMASK( 20, 16 )
|
||||
#define REG_ERR_CAPT_ALC_ID_FIELD GENMASK( 23, 21 )
|
||||
#define REG_ERR_CAPT_TS_BITS GENMASK( 29, 24 )
|
||||
|
||||
/* TRV_DELAY SSP_CFG registers */
|
||||
#define REG_TRV_DELAY_TRV_DELAY_VALUE GENMASK( 6, 0 )
|
||||
#define REG_TRV_DELAY_SSP_OFFSET GENMASK( 23, 16 )
|
||||
#define REG_TRV_DELAY_SSP_SRC GENMASK( 25, 24 )
|
||||
|
||||
/* RX_FR_CTR registers */
|
||||
#define REG_RX_FR_CTR_RX_FR_CTR_VAL GENMASK( 31, 0 )
|
||||
|
||||
/* TX_FR_CTR registers */
|
||||
#define REG_TX_FR_CTR_TX_FR_CTR_VAL GENMASK( 31, 0 )
|
||||
|
||||
/* DEBUG_REGISTER registers */
|
||||
#define REG_DEBUG_REGISTER_STUFF_COUNT GENMASK( 2, 0 )
|
||||
#define REG_DEBUG_REGISTER_DESTUFF_COUNT GENMASK( 5, 3 )
|
||||
#define REG_DEBUG_REGISTER_PC_ARB BIT( 6 )
|
||||
#define REG_DEBUG_REGISTER_PC_CON BIT( 7 )
|
||||
#define REG_DEBUG_REGISTER_PC_DAT BIT( 8 )
|
||||
#define REG_DEBUG_REGISTER_PC_STC BIT( 9 )
|
||||
#define REG_DEBUG_REGISTER_PC_CRC BIT( 10 )
|
||||
#define REG_DEBUG_REGISTER_PC_CRCD BIT( 11 )
|
||||
#define REG_DEBUG_REGISTER_PC_ACK BIT( 12 )
|
||||
#define REG_DEBUG_REGISTER_PC_ACKD BIT( 13 )
|
||||
#define REG_DEBUG_REGISTER_PC_EOF BIT( 14 )
|
||||
#define REG_DEBUG_REGISTER_PC_INT BIT( 15 )
|
||||
#define REG_DEBUG_REGISTER_PC_SUSP BIT( 16 )
|
||||
#define REG_DEBUG_REGISTER_PC_OVR BIT( 17 )
|
||||
#define REG_DEBUG_REGISTER_PC_SOF BIT( 18 )
|
||||
|
||||
/* YOLO_REG registers */
|
||||
#define REG_YOLO_REG_YOLO_VAL GENMASK( 31, 0 )
|
||||
|
||||
/* TIMESTAMP_LOW registers */
|
||||
#define REG_TIMESTAMP_LOW_TIMESTAMP_LOW GENMASK( 31, 0 )
|
||||
|
||||
/* TIMESTAMP_HIGH registers */
|
||||
#define REG_TIMESTAMP_HIGH_TIMESTAMP_HIGH GENMASK( 31, 0 )
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,119 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0 OR GPL-2.0-or-later */
|
||||
|
||||
/**
|
||||
* @file ctucanfd_txb.h
|
||||
*
|
||||
* @ingroup CTUCANFD
|
||||
*
|
||||
* @brief This file is part of CTU CAN FD core driver implementation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2024 Michal Lenc <michallenc@seznam.cz> FEE CTU
|
||||
* Copyright (C) 2024 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _DEV_CTUCANFD_CTUCANFD_TXB_H
|
||||
#define _DEV_CTUCANFD_CTUCANFD_TXB_H
|
||||
|
||||
#include "ctucanfd_internal.h"
|
||||
|
||||
#undef TXT_DONE
|
||||
#undef TXT_BF
|
||||
#undef TXT_MASK
|
||||
#undef TXT_ANY_DONE
|
||||
#undef TXB_BF
|
||||
#undef TXB_M
|
||||
#undef TXB_ALL
|
||||
#undef TXB_SH
|
||||
|
||||
#define TXT_DONE 0x4
|
||||
#define TXT_BF 4
|
||||
#define TXT_MASK 0xf
|
||||
#define TXT_ANY_DONE \
|
||||
( ( TXT_DONE << ( 0 * TXT_BF ) ) | ( TXT_DONE << ( 1 * TXT_BF ) ) | \
|
||||
( TXT_DONE << ( 2 * TXT_BF ) ) | ( TXT_DONE << ( 3 * TXT_BF ) ) | \
|
||||
( TXT_DONE << ( 4 * TXT_BF ) ) | ( TXT_DONE << ( 5 * TXT_BF ) ) | \
|
||||
( TXT_DONE << ( 6 * TXT_BF ) ) | ( TXT_DONE << ( 7 * TXT_BF ) ) )
|
||||
#define TXTB_GET_STATUS( status, id ) \
|
||||
( ( status >> ( id * TXT_BF ) ) & TXT_MASK )
|
||||
|
||||
#define TXB_BF 4
|
||||
#define TXB_MASK 0xf
|
||||
#define TXB_ALL 0xffffffff
|
||||
#define TXB_SH( idx ) ( idx * TXB_BF )
|
||||
|
||||
static inline uint32_t ctucanfd_txb_slot_demote(
|
||||
uint32_t txb_order,
|
||||
int from,
|
||||
int to
|
||||
)
|
||||
{
|
||||
uint32_t txb_order_new;
|
||||
uint32_t txb_move = ( txb_order >> TXB_SH( from ) ) & TXB_MASK;
|
||||
uint32_t mask_from = TXB_ALL << TXB_SH( from );
|
||||
uint32_t mask_to = TXB_ALL << TXB_SH( to );
|
||||
txb_order_new = txb_move << TXB_SH( to );
|
||||
txb_order_new |= txb_order & ( ~mask_from | ( mask_to << TXB_BF ) );
|
||||
txb_order_new |= ( ( txb_order >> TXB_BF ) & ~mask_to ) & mask_from;
|
||||
return txb_order_new;
|
||||
}
|
||||
|
||||
static inline uint32_t ctucanfd_txb_slot_promote(
|
||||
uint32_t txb_order,
|
||||
int from,
|
||||
int to
|
||||
)
|
||||
{
|
||||
uint32_t txb_order_new;
|
||||
uint32_t txb_move = ( txb_order >> TXB_SH( from ) ) & TXB_MASK;
|
||||
uint32_t mask_from = TXB_ALL << TXB_SH( from );
|
||||
uint32_t mask_to = TXB_ALL << TXB_SH( to );
|
||||
txb_order_new = txb_move << TXB_SH( to );
|
||||
txb_order_new |= ( txb_order ) & ( ~mask_to | ( mask_from << TXB_BF ) );
|
||||
txb_order_new |= ( ( ( txb_order & mask_to ) & ~mask_from ) << TXB_BF );
|
||||
return txb_order_new;
|
||||
}
|
||||
|
||||
static inline uint32_t ctucanfd_txb_order2prio( uint32_t txb_order )
|
||||
{
|
||||
uint32_t prio = 0;
|
||||
int i = RTEMS_CTUCANFD_NTXBUFS_MAX - 1;
|
||||
do {
|
||||
prio |= i << ( 4 * ( txb_order & TXB_MASK ) );
|
||||
txb_order >>= TXB_BF;
|
||||
} while ( i-- );
|
||||
|
||||
return prio;
|
||||
}
|
||||
|
||||
static inline unsigned int ctucanfd_txb_from_order(
|
||||
uint32_t txb_order,
|
||||
unsigned int at
|
||||
)
|
||||
{
|
||||
return ( txb_order >> TXB_SH( at ) ) & TXB_MASK;
|
||||
}
|
||||
|
||||
#endif /* _DEV_CTUCANFD_CTUCANFD_TXB_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,172 @@
|
||||
/* SPDX-License-Identifier: BSD-2-Clause OR Apache-2.0 OR GPL-2.0-or-later */
|
||||
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* @ingroup SJA1000
|
||||
*
|
||||
* @brief This source file contains the register's definition of SJA1000
|
||||
* controller.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (C) 2025-2026 Michal Lenc <michallenc@seznam.cz> self-funded
|
||||
* Copyright (C) 2025-2026 Pavel Pisa <pisa@cmp.felk.cvut.cz> self-funded
|
||||
* Implementation is based on original LinCAN SJA1000 driver
|
||||
* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz>
|
||||
* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz>
|
||||
* Copyright (C) 2004-2005 Tomasz Motylewski (BFAD GmbH)
|
||||
* Funded by OCERA and FRESCOR IST projects
|
||||
* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _DEV_CAN_SJA1000_SJA1000_REGS_H
|
||||
#define _DEV_CAN_SJA1000_SJA1000_REGS_H
|
||||
|
||||
#include <dev/can/can-helpers.h>
|
||||
|
||||
/* PeliCAN mode */
|
||||
enum sja1000_regs {
|
||||
SJA1000_MODE = 0x00,
|
||||
SJA1000_CMR = 0x01,
|
||||
SJA1000_SR = 0x02,
|
||||
SJA1000_IR = 0x03,
|
||||
SJA1000_IER = 0x04,
|
||||
SJA1000_BTR0 = 0x06,
|
||||
SJA1000_BTR1 = 0x07,
|
||||
SJA1000_OCR = 0x08,
|
||||
SJA1000_ALC = 0x0b,
|
||||
SJA1000_ECC = 0x0c,
|
||||
SJA1000_EWLR = 0x0d,
|
||||
SJA1000_RXERR = 0x0e,
|
||||
SJA1000_TXERR0 = 0x0e,
|
||||
SJA1000_TXERR1 = 0x0f,
|
||||
SJA1000_RMC = 0x1d,
|
||||
SJA1000_RBSA = 0x1e,
|
||||
SJA1000_FRM = 0x10,
|
||||
SJA1000_ID0 = 0x11,
|
||||
SJA1000_ID1 = 0x12,
|
||||
SJA1000_ID2 = 0x13,
|
||||
SJA1000_ID3 = 0x14,
|
||||
SJA1000_DATS = 0x13,
|
||||
SJA1000_DATE = 0x15,
|
||||
SJA1000_ACR0 = 0x10,
|
||||
SJA1000_ACR1 = 0x11,
|
||||
SJA1000_ACR2 = 0x12,
|
||||
SJA1000_ACR3 = 0x13,
|
||||
SJA1000_AMR0 = 0x14,
|
||||
SJA1000_AMR1 = 0x15,
|
||||
SJA1000_AMR2 = 0x16,
|
||||
SJA1000_AMR3 = 0x17,
|
||||
SJA1000_CDR = 0x1f
|
||||
};
|
||||
|
||||
/* Mode registers */
|
||||
#define REG_MODE_RM BIT(0)
|
||||
#define REG_MODE_LOM BIT(1)
|
||||
#define REG_MODE_STM BIT(2)
|
||||
#define REG_MODE_AFM BIT(3)
|
||||
#define REG_MODE_SM BIT(4)
|
||||
|
||||
/* Command registers */
|
||||
#define REG_CMR_TR BIT(0)
|
||||
#define REG_CMR_AT BIT(1)
|
||||
#define REG_CMR_RRB BIT(2)
|
||||
#define REG_CMR_CDO BIT(3)
|
||||
#define REG_CMR_SRR BIT(4)
|
||||
|
||||
/* Status registers */
|
||||
#define REG_SR_RBS BIT(0)
|
||||
#define REG_SR_DOS BIT(1)
|
||||
#define REG_SR_TBS BIT(2)
|
||||
#define REG_SR_TCS BIT(3)
|
||||
#define REG_SR_RS BIT(4)
|
||||
#define REG_SR_TS BIT(5)
|
||||
#define REG_SR_ES BIT(6)
|
||||
#define REG_SR_BS BIT(7)
|
||||
#define REG_SR_WORKER_MASK (0x5)
|
||||
|
||||
/* Interrupt registers */
|
||||
#define REG_INT_RI BIT(0)
|
||||
#define REG_INT_TI BIT(1)
|
||||
#define REG_INT_EI BIT(2)
|
||||
#define REG_INT_DOI BIT(3)
|
||||
#define REG_INT_WUI BIT(4)
|
||||
#define REG_INT_EPI BIT(5)
|
||||
#define REG_INT_ALI BIT(6)
|
||||
#define REG_INT_BEI BIT(7)
|
||||
#define REG_INT_MASK (0xff)
|
||||
#define REG_INT_WORKER_MASK (0xfc)
|
||||
|
||||
/* Arbitration lost capture register */
|
||||
#define REG_ALC_RTR (0x1f)
|
||||
#define REG_ALC_IDE (0x1c)
|
||||
#define REG_ALC_SRTR (0x0b)
|
||||
|
||||
/* Error Code Capture Register */
|
||||
#define REG_ECC_DIR BIT(5)
|
||||
#define REG_ECC_ERCC GENMASK(7, 6)
|
||||
#define REG_ECC_FUNC GENMASK(4, 0)
|
||||
#define REG_ECC_ERCC_BIT (0)
|
||||
#define REG_ECC_ERCC_FORM (1)
|
||||
#define REG_ECC_ERCC_STUFF (2)
|
||||
#define REG_ECC_ERCC_OTHER (3)
|
||||
|
||||
#define REG_ECC_ERROR_ACTIVE (0x11)
|
||||
#define REG_ECC_ERROR_PASSIVE (0x16)
|
||||
|
||||
/* Frame format information */
|
||||
#define REG_FRM_DLC GENMASK(3, 0)
|
||||
#define REG_FRM_RTR BIT(6)
|
||||
#define REG_FRM_FF BIT(7)
|
||||
#define REG_FRM_DLC_MASK (BIT(4) - 1)
|
||||
|
||||
/* Bus Timing 1 Register */
|
||||
#define REG_BTR1_TSEG1_MAX (15)
|
||||
#define REG_BTR1_TSEG2_MAX (7)
|
||||
|
||||
/* Output Control Register */
|
||||
#define REG_OCR_MODE_BIPHASE (0)
|
||||
#define REG_OCR_MODE_TEST (1)
|
||||
#define REG_OCR_MODE_NORMAL (2)
|
||||
#define REG_OCR_MODE_CLOCK (3)
|
||||
#define REG_OCR_TX0_LH (0x18)
|
||||
#define REG_OCR_TX1_ZZ (0)
|
||||
|
||||
/* Clock Divider register */
|
||||
#define REG_CDR_OFF BIT(3)
|
||||
#define REG_CDR_RXINPEN BIT(5)
|
||||
#define REG_CDR_CBP BIT(6)
|
||||
#define REG_CDR_PELICAN BIT(7)
|
||||
#define REG_CDR_CLKOUT_DIV1 (7)
|
||||
#define REG_CDR_CLKOUT_DIV2 (0)
|
||||
#define REG_CDR_CLKOUT_DIV4 (1)
|
||||
#define REG_CDR_CLKOUT_DIV6 (2)
|
||||
#define REG_CDR_CLKOUT_DIV8 (3)
|
||||
#define REG_CDR_CLKOUT_DIV10 (4)
|
||||
#define REG_CDR_CLKOUT_DIV12 (5)
|
||||
#define REG_CDR_CLKOUT_DIV14 (6)
|
||||
#define REG_CDR_CLKOUT_MASK (7)
|
||||
|
||||
#endif /* _DEV_CAN_SJA1000_SJA1000_REGS_H */
|
||||
Reference in New Issue
Block a user