From 485efbd418d5346c15feeaa4c058a5ac94fb0243 Mon Sep 17 00:00:00 2001 From: Mohamed Ayman Date: Sun, 15 Mar 2026 00:27:49 +0200 Subject: [PATCH] docs: correct spelling and grammar in stm32f4 headers Fixed various typos and grammatical errors throughout the documentation in the stm32f4 include folder to improve readability. --- bsps/arm/stm32f4/include/bsp/i2c.h | 12 ++++++------ bsps/arm/stm32f4/include/bsp/rcc.h | 2 +- bsps/arm/stm32f4/include/bsp/stm32f4.h | 18 +++++++++--------- bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h | 8 ++++---- bsps/arm/stm32f4/include/tm27.h | 7 +++++++ 5 files changed, 27 insertions(+), 20 deletions(-) diff --git a/bsps/arm/stm32f4/include/bsp/i2c.h b/bsps/arm/stm32f4/include/bsp/i2c.h index 80a03ac286..8bdd4c6e2e 100644 --- a/bsps/arm/stm32f4/include/bsp/i2c.h +++ b/bsps/arm/stm32f4/include/bsp/i2c.h @@ -14,9 +14,9 @@ * http://www.rtems.org/license/LICENSE. */ -/* The I2C-module can not run with libi2c. The reason for this is, that libi2c +/* The I2C-module can not run with libi2c. The reason for this is that libi2c * needs a possibility to generate a stop condition separately. This controller - * wants to generate the condition automatically when sending or receiving data. + * generates the condition automatically when sending or receiving data. */ #ifndef LIBBSP_ARM_STM32F4_I2C_H @@ -40,8 +40,8 @@ extern "C" { typedef struct { /** - * @brief The address of the slave without the read write bit. - * A 7-Bit address should be placed in the bits [6..0] + * @brief The address of the slave without the read/write bit. + * A 7-bit address should be placed in bits [6..0] */ uint16_t addr; /** @brief Read (true) or write (false) data */ @@ -68,13 +68,13 @@ typedef struct { /** @brief Initialise the i2c module. */ rtems_status_code stm32f4_i2c_init(stm32f4_i2c_bus_entry *e); -/** @brief Process a i2c message */ +/** @brief Process an i2c message */ rtems_status_code stm32f4_i2c_process_message( stm32f4_i2c_bus_entry *e, stm32f4_i2c_message *msg ); -/** @brief Set another baud rate than the default one */ +/** @brief Set a baud rate other than the default */ rtems_status_code stm32f4_i2c_set_bitrate( stm32f4_i2c_bus_entry *e, uint32_t br diff --git a/bsps/arm/stm32f4/include/bsp/rcc.h b/bsps/arm/stm32f4/include/bsp/rcc.h index de640de128..66e52f3578 100644 --- a/bsps/arm/stm32f4/include/bsp/rcc.h +++ b/bsps/arm/stm32f4/include/bsp/rcc.h @@ -125,7 +125,7 @@ typedef enum { #ifdef STM32F4_FAMILY_F10XXX /** - * @name Family F10 + * @name Family F10XXX * @{ */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4.h b/bsps/arm/stm32f4/include/bsp/stm32f4.h index d7116c49ad..c2c2f22096 100644 --- a/bsps/arm/stm32f4/include/bsp/stm32f4.h +++ b/bsps/arm/stm32f4/include/bsp/stm32f4.h @@ -42,7 +42,7 @@ #ifdef STM32F4_FAMILY_F4XXXX /** - * @defgroup stm32f4_reg Register Defintions + * @defgroup stm32f4_reg Register Definitions * @ingroup RTEMSBSPsARMSTM32F4 * @brief Register Definitions * @{ @@ -54,7 +54,7 @@ #define STM32F4_AHB2_BASE (STM32F4_BASE + 0x50000000) /** - * @name STM32f4XXXX GPIO + * @name STM32F4XXXX GPIO * @{ */ @@ -102,7 +102,7 @@ /** @} */ /** - * @name STM32f4XXXX PWR + * @name STM32F4XXXX PWR * @{ */ @@ -112,7 +112,7 @@ /** @} */ /** - * @name STM32f4XXXX EXTI + * @name STM32F4XXXX EXTI * @{ */ @@ -122,7 +122,7 @@ /** @} */ /** - * @name STM32f4XXXX SYSCFG + * @name STM32F4XXXX SYSCFG * @{ */ @@ -132,7 +132,7 @@ /** @} */ /** - * @name STM32f4XXXX FLASH + * @name STM32F4XXXX FLASH * @{ */ @@ -142,7 +142,7 @@ /** @} */ /** - * @name STM32f4XXXX TIM + * @name STM32F4XXXX TIM * @{ */ @@ -165,7 +165,7 @@ /** @} */ /** - * @name STM32f4XXXX ADC + * @name STM32F4XXXX ADC * @{ */ @@ -178,7 +178,7 @@ /** @} */ /** - * @name STM32f4XXXX OTGFS + * @name STM32F4XXXX OTGFS * @{ */ diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h index b1366b6978..245fa8b4c8 100644 --- a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_adc.h @@ -42,7 +42,7 @@ struct stm32f4_adc_chan_s { #define STM32F4_ADC_CR1_DISCNUM(val) BSP_FLD32(val, 13, 15) // Discontinuous mode channel count #define STM32F4_ADC_CR1_DISCNUM_GET(reg) BSP_FLD32GET(reg, 13, 15) #define STM32F4_ADC_CR1_DISCNUM_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) -#define STM32F4_ADC_CR1_JDISCEN BSP_BIT32(12) // Discontinous mode on injected channels +#define STM32F4_ADC_CR1_JDISCEN BSP_BIT32(12) // Discontinuous mode on injected channels #define STM32F4_ADC_CR1_DISCEN BSP_BIT32(11) // Discontinous mode on regular channels #define STM32F4_ADC_CR1_JAUTO BSP_BIT32(10) // Automated injected group conversion #define STM32F4_ADC_CR1_AWDSGL BSP_BIT32(9) // Enable watchdog on single channel in scan mode @@ -254,10 +254,10 @@ struct stm32f4_adc_com_s { #define STM32F4_ADC_CSR_EOC1 BSP_BIT32(1) // Channel end of conversion flag ADC1 #define STM32F4_ADC_CSR_AWD1 BSP_BIT32(0) // Analog watchdog flag ADC1 - uint32_t ccr; // 0x00: Common control register + uint32_t ccr; // 0x04: Common control register #define STM32F4_ADC_CCR_TSVREFE BSP_BIT32(23) // Temp sensor and Vrefint enable #define STM32F4_ADC_CCR_VBATE BSP_BIT32(22) // Vbat enable -#define STM32F4_ADC_CCR_ADCPRE(val) BSP_FLD32(val, 16, 17) // ADC prescalar +#define STM32F4_ADC_CCR_ADCPRE(val) BSP_FLD32(val, 16, 17) // ADC prescaler #define STM32F4_ADC_CCR_ADCPRE_GET(reg) BSP_FLD32GET(reg, 16, 17) #define STM32F4_ADC_CCR_ADCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) #define ADC_ADCPRE_PCLK2_2 0 @@ -308,7 +308,7 @@ struct stm32f4_adc_com_s { #define ADC_MULTI_TRIPLE_INTRL 0x17 #define ADC_MULTI_TRIPLE_ALT_TRIG 0x19 - uint32_t cdr; // 0x00: Common regular data register + uint32_t cdr; // 0x08: Common regular data register #define STM32F4_ADC_CDR_DATA2(val) BSP_FLD32(val, 16, 31) // 2nd data item #define STM32F4_ADC_CDR_DATA2_GET(reg) BSP_FLD32GET(reg, 16, 31) #define STM32F4_ADC_CDR_DATA2_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) diff --git a/bsps/arm/stm32f4/include/tm27.h b/bsps/arm/stm32f4/include/tm27.h index 971075dbf1..78fd0f760b 100644 --- a/bsps/arm/stm32f4/include/tm27.h +++ b/bsps/arm/stm32f4/include/tm27.h @@ -33,4 +33,11 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#ifndef LIBBSP_ARM_STM32F4_TM27_H +#define LIBBSP_ARM_STM32F4_TM27_H + + #include + + +#endif /* LIBBSP_ARM_STM32F4_TM27_H */