From 3ff994ce8393d9709cdf91c4dd9fdc0fc46ec852 Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Mon, 23 Mar 2026 17:07:54 -0500 Subject: [PATCH] cpukit/riscv: Make use of MDT conditional on Zicsr The MDT bit is defined by the Smdbltrp extension which is dependent on the Zicsr extension, so if zicsr is not present then neither is Smdbltrp. Smdbltrp also introduces mstatush on rv32, so this entire block must be skipped if Zicsr is not present. --- cpukit/score/cpu/riscv/riscv-exception-handler.S | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index db286a54c4..8d184e376c 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -136,8 +136,10 @@ SYM(_RISCV_Vector_table): * Interrupt exception, clear MDT bit. * This is only necessary if the Smdbltrp extension is implemented. * In that case not clearing the MDT bit would prevent us from setting - * the MIE bit later. + * the MIE bit later. Smdbltrp implies zicsr, so if zicsr is not present + * then Smdbltrp (which introduces mstatush/MDT) can not be present. */ +#ifdef __riscv_zicsr #ifdef RISCV_USE_S_MODE li t0, SSTATUS_SDT csrrc zero, sstatus, t0 @@ -150,6 +152,7 @@ SYM(_RISCV_Vector_table): csrrc zero, mstatush, t0 #endif #endif /* RISCV_USE_S_MODE */ +#endif /* __riscv_zicsr */ /* Increment interrupt nest and thread dispatch disable level */ lw t0, PER_CPU_ISR_NEST_LEVEL(s0)