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bsps/grlib: Add generated headers

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Close #4828.
This commit is contained in:
Sebastian Huber
2023-07-14 09:11:19 +02:00
parent f46c15fd76
commit 2d71cba033
31 changed files with 17191 additions and 47 deletions
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bsps/include/grlib/ahbstat-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBAHBSTAT
*
* @brief This header file defines the AHBSTAT register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/ahbstat-header */
#ifndef _GRLIB_AHBSTAT_REGS_H
#define _GRLIB_AHBSTAT_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/ahbstat */
/**
* @defgroup RTEMSDeviceGRLIBAHBSTAT AHBSTAT
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the AHBSTAT interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBAHBSTATAHBS AHB Status register (AHBS)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBSTAT_AHBS_ME 0x2000U
#define AHBSTAT_AHBS_FW 0x1000U
#define AHBSTAT_AHBS_CF 0x800U
#define AHBSTAT_AHBS_AF 0x400U
#define AHBSTAT_AHBS_CE 0x200U
#define AHBSTAT_AHBS_NE 0x100U
#define AHBSTAT_AHBS_HWRITE 0x80U
#define AHBSTAT_AHBS_HMASTER_SHIFT 3
#define AHBSTAT_AHBS_HMASTER_MASK 0x78U
#define AHBSTAT_AHBS_HMASTER_GET( _reg ) \
( ( ( _reg ) & AHBSTAT_AHBS_HMASTER_MASK ) >> \
AHBSTAT_AHBS_HMASTER_SHIFT )
#define AHBSTAT_AHBS_HMASTER_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBSTAT_AHBS_HMASTER_MASK ) | \
( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & \
AHBSTAT_AHBS_HMASTER_MASK ) )
#define AHBSTAT_AHBS_HMASTER( _val ) \
( ( ( _val ) << AHBSTAT_AHBS_HMASTER_SHIFT ) & \
AHBSTAT_AHBS_HMASTER_MASK )
#define AHBSTAT_AHBS_HSIZE_SHIFT 0
#define AHBSTAT_AHBS_HSIZE_MASK 0x7U
#define AHBSTAT_AHBS_HSIZE_GET( _reg ) \
( ( ( _reg ) & AHBSTAT_AHBS_HSIZE_MASK ) >> \
AHBSTAT_AHBS_HSIZE_SHIFT )
#define AHBSTAT_AHBS_HSIZE_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBSTAT_AHBS_HSIZE_MASK ) | \
( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & \
AHBSTAT_AHBS_HSIZE_MASK ) )
#define AHBSTAT_AHBS_HSIZE( _val ) \
( ( ( _val ) << AHBSTAT_AHBS_HSIZE_SHIFT ) & \
AHBSTAT_AHBS_HSIZE_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBSTATAHBFAR \
* AHB Failing address register (AHBFAR)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBSTAT_AHBFAR_HADDR_SHIFT 0
#define AHBSTAT_AHBFAR_HADDR_MASK 0xffffffffU
#define AHBSTAT_AHBFAR_HADDR_GET( _reg ) \
( ( ( _reg ) & AHBSTAT_AHBFAR_HADDR_MASK ) >> \
AHBSTAT_AHBFAR_HADDR_SHIFT )
#define AHBSTAT_AHBFAR_HADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBSTAT_AHBFAR_HADDR_MASK ) | \
( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & \
AHBSTAT_AHBFAR_HADDR_MASK ) )
#define AHBSTAT_AHBFAR_HADDR( _val ) \
( ( ( _val ) << AHBSTAT_AHBFAR_HADDR_SHIFT ) & \
AHBSTAT_AHBFAR_HADDR_MASK )
/** @} */
/**
* @brief This structure defines the AHBSTAT register block memory map.
*/
typedef struct ahbstat {
/**
* @brief See @ref RTEMSDeviceGRLIBAHBSTATAHBS.
*/
uint32_t ahbs;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBSTATAHBFAR.
*/
uint32_t ahbfar;
} ahbstat;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_AHBSTAT_REGS_H */
bsps/include/grlib/ahbtrace-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBAHBTRACE
*
* @brief This header file defines the AHBTRACE register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/ahbtrace-header */
#ifndef _GRLIB_AHBTRACE_REGS_H
#define _GRLIB_AHBTRACE_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/ahbtrace */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACE AHBTRACE
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the AHBTRACE interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACECTRL Trace buffer control register (CTRL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_CTRL_DCNT_SHIFT 16
#define AHBTRACE_CTRL_DCNT_MASK 0x7f0000U
#define AHBTRACE_CTRL_DCNT_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_CTRL_DCNT_MASK ) >> \
AHBTRACE_CTRL_DCNT_SHIFT )
#define AHBTRACE_CTRL_DCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_CTRL_DCNT_MASK ) | \
( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \
AHBTRACE_CTRL_DCNT_MASK ) )
#define AHBTRACE_CTRL_DCNT( _val ) \
( ( ( _val ) << AHBTRACE_CTRL_DCNT_SHIFT ) & \
AHBTRACE_CTRL_DCNT_MASK )
#define AHBTRACE_CTRL_PF 0x100U
#define AHBTRACE_CTRL_BW_SHIFT 6
#define AHBTRACE_CTRL_BW_MASK 0xc0U
#define AHBTRACE_CTRL_BW_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_CTRL_BW_MASK ) >> \
AHBTRACE_CTRL_BW_SHIFT )
#define AHBTRACE_CTRL_BW_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_CTRL_BW_MASK ) | \
( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \
AHBTRACE_CTRL_BW_MASK ) )
#define AHBTRACE_CTRL_BW( _val ) \
( ( ( _val ) << AHBTRACE_CTRL_BW_SHIFT ) & \
AHBTRACE_CTRL_BW_MASK )
#define AHBTRACE_CTRL_RF 0x20U
#define AHBTRACE_CTRL_AF 0x10U
#define AHBTRACE_CTRL_FR 0x8U
#define AHBTRACE_CTRL_FW 0x4U
#define AHBTRACE_CTRL_DM 0x2U
#define AHBTRACE_CTRL_EN 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACEINDEX Trace buffer index register (INDEX)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_INDEX_INDEX_SHIFT 4
#define AHBTRACE_INDEX_INDEX_MASK 0x7f0U
#define AHBTRACE_INDEX_INDEX_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_INDEX_INDEX_MASK ) >> \
AHBTRACE_INDEX_INDEX_SHIFT )
#define AHBTRACE_INDEX_INDEX_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_INDEX_INDEX_MASK ) | \
( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \
AHBTRACE_INDEX_INDEX_MASK ) )
#define AHBTRACE_INDEX_INDEX( _val ) \
( ( ( _val ) << AHBTRACE_INDEX_INDEX_SHIFT ) & \
AHBTRACE_INDEX_INDEX_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACETIMETAG \
* Trace buffer time tag register (TIMETAG)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_TIMETAG_TIMETAG_SHIFT 0
#define AHBTRACE_TIMETAG_TIMETAG_MASK 0xffffffffU
#define AHBTRACE_TIMETAG_TIMETAG_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TIMETAG_TIMETAG_MASK ) >> \
AHBTRACE_TIMETAG_TIMETAG_SHIFT )
#define AHBTRACE_TIMETAG_TIMETAG_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TIMETAG_TIMETAG_MASK ) | \
( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \
AHBTRACE_TIMETAG_TIMETAG_MASK ) )
#define AHBTRACE_TIMETAG_TIMETAG( _val ) \
( ( ( _val ) << AHBTRACE_TIMETAG_TIMETAG_SHIFT ) & \
AHBTRACE_TIMETAG_TIMETAG_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACEMSFILT \
* Trace buffer master/slave filter register (MSFILT)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_MSFILT_SMASK_15_0_SHIFT 16
#define AHBTRACE_MSFILT_SMASK_15_0_MASK 0xffff0000U
#define AHBTRACE_MSFILT_SMASK_15_0_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_MSFILT_SMASK_15_0_MASK ) >> \
AHBTRACE_MSFILT_SMASK_15_0_SHIFT )
#define AHBTRACE_MSFILT_SMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_MSFILT_SMASK_15_0_MASK ) | \
( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_SMASK_15_0_MASK ) )
#define AHBTRACE_MSFILT_SMASK_15_0( _val ) \
( ( ( _val ) << AHBTRACE_MSFILT_SMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_SMASK_15_0_MASK )
#define AHBTRACE_MSFILT_MMASK_15_0_SHIFT 0
#define AHBTRACE_MSFILT_MMASK_15_0_MASK 0xffffU
#define AHBTRACE_MSFILT_MMASK_15_0_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_MSFILT_MMASK_15_0_MASK ) >> \
AHBTRACE_MSFILT_MMASK_15_0_SHIFT )
#define AHBTRACE_MSFILT_MMASK_15_0_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_MSFILT_MMASK_15_0_MASK ) | \
( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_MMASK_15_0_MASK ) )
#define AHBTRACE_MSFILT_MMASK_15_0( _val ) \
( ( ( _val ) << AHBTRACE_MSFILT_MMASK_15_0_SHIFT ) & \
AHBTRACE_MSFILT_MMASK_15_0_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACETBBA \
* Trace buffer break address registers (TBBA)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_TBBA_BADDR_31_2_SHIFT 2
#define AHBTRACE_TBBA_BADDR_31_2_MASK 0xfffffffcU
#define AHBTRACE_TBBA_BADDR_31_2_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TBBA_BADDR_31_2_MASK ) >> \
AHBTRACE_TBBA_BADDR_31_2_SHIFT )
#define AHBTRACE_TBBA_BADDR_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TBBA_BADDR_31_2_MASK ) | \
( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \
AHBTRACE_TBBA_BADDR_31_2_MASK ) )
#define AHBTRACE_TBBA_BADDR_31_2( _val ) \
( ( ( _val ) << AHBTRACE_TBBA_BADDR_31_2_SHIFT ) & \
AHBTRACE_TBBA_BADDR_31_2_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAHBTRACETBBM \
* Trace buffer break mask registers (TBBM)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define AHBTRACE_TBBM_BMASK_31_2_SHIFT 2
#define AHBTRACE_TBBM_BMASK_31_2_MASK 0xfffffffcU
#define AHBTRACE_TBBM_BMASK_31_2_GET( _reg ) \
( ( ( _reg ) & AHBTRACE_TBBM_BMASK_31_2_MASK ) >> \
AHBTRACE_TBBM_BMASK_31_2_SHIFT )
#define AHBTRACE_TBBM_BMASK_31_2_SET( _reg, _val ) \
( ( ( _reg ) & ~AHBTRACE_TBBM_BMASK_31_2_MASK ) | \
( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \
AHBTRACE_TBBM_BMASK_31_2_MASK ) )
#define AHBTRACE_TBBM_BMASK_31_2( _val ) \
( ( ( _val ) << AHBTRACE_TBBM_BMASK_31_2_SHIFT ) & \
AHBTRACE_TBBM_BMASK_31_2_MASK )
#define AHBTRACE_TBBM_LD 0x2U
#define AHBTRACE_TBBM_ST 0x1U
/** @} */
/**
* @brief This structure defines the AHBTRACE register block memory map.
*/
typedef struct ahbtrace {
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACECTRL.
*/
uint32_t ctrl;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACEINDEX.
*/
uint32_t index;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETIMETAG.
*/
uint32_t timetag;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACEMSFILT.
*/
uint32_t msfilt;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA.
*/
uint32_t tbba_0;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM.
*/
uint32_t tbbm_0;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBA.
*/
uint32_t tbba_1;
/**
* @brief See @ref RTEMSDeviceGRLIBAHBTRACETBBM.
*/
uint32_t tbbm_1;
} ahbtrace;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_AHBTRACE_REGS_H */
bsps/include/grlib/apbuart-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBAPBUART
*
* @brief This header file defines the APBUART register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/apbuart-header */
#ifndef _GRLIB_APBUART_REGS_H
#define _GRLIB_APBUART_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/apbuart */
/**
* @defgroup RTEMSDeviceGRLIBAPBUART APBUART
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the APBUART interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBAPBUARTDATA UART data register (DATA)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define APBUART_DATA_DATA_SHIFT 0
#define APBUART_DATA_DATA_MASK 0xffU
#define APBUART_DATA_DATA_GET( _reg ) \
( ( ( _reg ) & APBUART_DATA_DATA_MASK ) >> \
APBUART_DATA_DATA_SHIFT )
#define APBUART_DATA_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_DATA_DATA_MASK ) | \
( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & \
APBUART_DATA_DATA_MASK ) )
#define APBUART_DATA_DATA( _val ) \
( ( ( _val ) << APBUART_DATA_DATA_SHIFT ) & \
APBUART_DATA_DATA_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAPBUARTSTATUS UART status register (STATUS)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define APBUART_STATUS_RCNT_SHIFT 26
#define APBUART_STATUS_RCNT_MASK 0xfc000000U
#define APBUART_STATUS_RCNT_GET( _reg ) \
( ( ( _reg ) & APBUART_STATUS_RCNT_MASK ) >> \
APBUART_STATUS_RCNT_SHIFT )
#define APBUART_STATUS_RCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_STATUS_RCNT_MASK ) | \
( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & \
APBUART_STATUS_RCNT_MASK ) )
#define APBUART_STATUS_RCNT( _val ) \
( ( ( _val ) << APBUART_STATUS_RCNT_SHIFT ) & \
APBUART_STATUS_RCNT_MASK )
#define APBUART_STATUS_TCNT_SHIFT 20
#define APBUART_STATUS_TCNT_MASK 0x3f00000U
#define APBUART_STATUS_TCNT_GET( _reg ) \
( ( ( _reg ) & APBUART_STATUS_TCNT_MASK ) >> \
APBUART_STATUS_TCNT_SHIFT )
#define APBUART_STATUS_TCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_STATUS_TCNT_MASK ) | \
( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & \
APBUART_STATUS_TCNT_MASK ) )
#define APBUART_STATUS_TCNT( _val ) \
( ( ( _val ) << APBUART_STATUS_TCNT_SHIFT ) & \
APBUART_STATUS_TCNT_MASK )
#define APBUART_STATUS_RF 0x400U
#define APBUART_STATUS_TF 0x200U
#define APBUART_STATUS_RH 0x100U
#define APBUART_STATUS_TH 0x80U
#define APBUART_STATUS_FE 0x40U
#define APBUART_STATUS_PE 0x20U
#define APBUART_STATUS_OV 0x10U
#define APBUART_STATUS_BR 0x8U
#define APBUART_STATUS_TE 0x4U
#define APBUART_STATUS_TS 0x2U
#define APBUART_STATUS_DR 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAPBUARTCTRL UART control register (CTRL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define APBUART_CTRL_FA 0x80000000U
#define APBUART_CTRL_SI 0x4000U
#define APBUART_CTRL_DI 0x2000U
#define APBUART_CTRL_BI 0x1000U
#define APBUART_CTRL_DB 0x800U
#define APBUART_CTRL_RF 0x400U
#define APBUART_CTRL_TF 0x200U
#define APBUART_CTRL_EC 0x100U
#define APBUART_CTRL_LB 0x80U
#define APBUART_CTRL_FL 0x40U
#define APBUART_CTRL_PE 0x20U
#define APBUART_CTRL_PS 0x10U
#define APBUART_CTRL_TI 0x8U
#define APBUART_CTRL_RI 0x4U
#define APBUART_CTRL_TE 0x2U
#define APBUART_CTRL_RE 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAPBUARTSCALER UART scaler reload register (SCALER)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT 0
#define APBUART_SCALER_SCALER_RELOAD_VALUE_MASK 0xfffffU
#define APBUART_SCALER_SCALER_RELOAD_VALUE_GET( _reg ) \
( ( ( _reg ) & APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) >> \
APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT )
#define APBUART_SCALER_SCALER_RELOAD_VALUE_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) | \
( ( ( _val ) << APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) & \
APBUART_SCALER_SCALER_RELOAD_VALUE_MASK ) )
#define APBUART_SCALER_SCALER_RELOAD_VALUE( _val ) \
( ( ( _val ) << APBUART_SCALER_SCALER_RELOAD_VALUE_SHIFT ) & \
APBUART_SCALER_SCALER_RELOAD_VALUE_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBAPBUARTFIFO UART FIFO debug register (FIFO)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define APBUART_FIFO_DATA_SHIFT 0
#define APBUART_FIFO_DATA_MASK 0xffU
#define APBUART_FIFO_DATA_GET( _reg ) \
( ( ( _reg ) & APBUART_FIFO_DATA_MASK ) >> \
APBUART_FIFO_DATA_SHIFT )
#define APBUART_FIFO_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~APBUART_FIFO_DATA_MASK ) | \
( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & \
APBUART_FIFO_DATA_MASK ) )
#define APBUART_FIFO_DATA( _val ) \
( ( ( _val ) << APBUART_FIFO_DATA_SHIFT ) & \
APBUART_FIFO_DATA_MASK )
/** @} */
/**
* @brief This structure defines the APBUART register block memory map.
*/
typedef struct apbuart {
/**
* @brief See @ref RTEMSDeviceGRLIBAPBUARTDATA.
*/
uint32_t data;
/**
* @brief See @ref RTEMSDeviceGRLIBAPBUARTSTATUS.
*/
uint32_t status;
/**
* @brief See @ref RTEMSDeviceGRLIBAPBUARTCTRL.
*/
uint32_t ctrl;
/**
* @brief See @ref RTEMSDeviceGRLIBAPBUARTSCALER.
*/
uint32_t scaler;
/**
* @brief See @ref RTEMSDeviceGRLIBAPBUARTFIFO.
*/
uint32_t fifo;
} apbuart;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_APBUART_REGS_H */
bsps/include/grlib/apbuart.h
+61 -47
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@@ -2,12 +2,14 @@
/**
* @file
* @ingroup uart
*
* @ingroup RTEMSDeviceGRLIBAPBUART
*
* @brief This header file defines the APBUART interface.
*/
/*
* COPYRIGHT (c) 2007.
* Gaisler Research
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -29,68 +31,80 @@
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __APBUART_H__
#define __APBUART_H__
/**
* @defgroup uart UART
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* @ingroup RTEMSBSPsSharedGRLIB
* https://www.rtems.org/bugs.html
*
* @brief Driver interface for APBUART
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* @{
* https://docs.rtems.org
*/
#include "ambapp.h"
#include "grlib.h"
/* Generated from spec:/dev/grlib/if/apbuart-header-2 */
#ifndef _GRLIB_APBUART_H
#define _GRLIB_APBUART_H
#include <grlib/apbuart-regs.h>
#ifdef __cplusplus
extern "C" {
#endif
#define APBUART_CTRL_RE 0x1
#define APBUART_CTRL_TE 0x2
#define APBUART_CTRL_RI 0x4
#define APBUART_CTRL_TI 0x8
#define APBUART_CTRL_PS 0x10
#define APBUART_CTRL_PE 0x20
#define APBUART_CTRL_FL 0x40
#define APBUART_CTRL_LB 0x80
#define APBUART_CTRL_EC 0x100
#define APBUART_CTRL_TF 0x200
#define APBUART_CTRL_RF 0x400
#define APBUART_CTRL_DB 0x800
#define APBUART_CTRL_BI 0x1000
#define APBUART_CTRL_DI 0x2000
#define APBUART_CTRL_FA 0x80000000
/* Generated from spec:/dev/grlib/if/apbuart-inbyte-nonblocking */
#define APBUART_STATUS_DR 0x1
#define APBUART_STATUS_TS 0x2
#define APBUART_STATUS_TE 0x4
#define APBUART_STATUS_BR 0x8
#define APBUART_STATUS_OV 0x10
#define APBUART_STATUS_PE 0x20
#define APBUART_STATUS_FE 0x40
#define APBUART_STATUS_ERR 0x78
#define APBUART_STATUS_TH 0x80
#define APBUART_STATUS_RH 0x100
#define APBUART_STATUS_TF 0x200
#define APBUART_STATUS_RF 0x400
/**
* @ingroup RTEMSDeviceGRLIBAPBUART
*
* @brief Clears all errors and tries to get one character from the receiver
* FIFO.
*
* @param regs is the pointer to the APBUART register block.
*
* @retval -1 The receiver FIFO was empty.
*
* @return Returns the first character of the receiver FIFO if it was
* non-empty.
*/
int apbuart_inbyte_nonblocking( apbuart *regs );
void apbuart_outbyte_wait(const struct apbuart_regs *regs);
/* Generated from spec:/dev/grlib/if/apbuart-outbyte-polled */
void apbuart_outbyte_polled(struct apbuart_regs *regs, char ch);
/**
* @ingroup RTEMSDeviceGRLIBAPBUART
*
* @brief Waits until an empty transmitter FIFO was observed and then stores
* the character to the data register.
*
* @param regs is the pointer to the APBUART register block.
*
* @param ch is the character to output.
*/
void apbuart_outbyte_polled( apbuart *regs, char ch );
int apbuart_inbyte_nonblocking(struct apbuart_regs *regs);
/* Generated from spec:/dev/grlib/if/apbuart-outbyte-wait */
/**
* @ingroup RTEMSDeviceGRLIBAPBUART
*
* @brief Ensures that at least once an empty transmitter FIFO was observed.
*
* @param regs is the pointer to the APBUART register block.
*/
void apbuart_outbyte_wait( const apbuart *regs );
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* __APBUART_H__ */
#endif /* _GRLIB_APBUART_H */
bsps/include/grlib/dsu4-regs.h
+788
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bsps/include/grlib/ftmctrl-regs.h
+309
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@@ -0,0 +1,309 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBFTMCTRL
*
* @brief This header file defines the FTMCTRL register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/ftmctrl-header */
#ifndef _GRLIB_FTMCTRL_REGS_H
#define _GRLIB_FTMCTRL_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/ftmctrl */
/**
* @defgroup RTEMSDeviceGRLIBFTMCTRL FTMCTRL
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the FTMCTRL interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG1 \
* Memory configuration register 1 (MCFG1)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define FTMCTRL_MCFG1_PBRDY 0x80000000U
#define FTMCTRL_MCFG1_ABRDY 0x40000000U
#define FTMCTRL_MCFG1_IOBUSW 0x20000000U
#define FTMCTRL_MCFG1_IBRDY_SHIFT 27
#define FTMCTRL_MCFG1_IBRDY_MASK 0x18000000U
#define FTMCTRL_MCFG1_IBRDY_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_IBRDY_MASK ) >> \
FTMCTRL_MCFG1_IBRDY_SHIFT )
#define FTMCTRL_MCFG1_IBRDY_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IBRDY_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_IBRDY_SHIFT ) & \
FTMCTRL_MCFG1_IBRDY_MASK ) )
#define FTMCTRL_MCFG1_IBRDY( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_IBRDY_SHIFT ) & \
FTMCTRL_MCFG1_IBRDY_MASK )
#define FTMCTRL_MCFG1_BEXCN 0x4000000U
#define FTMCTRL_MCFG1_IO_WAITSTATES 0x1000000U
#define FTMCTRL_MCFG1_IOEN_SHIFT 20
#define FTMCTRL_MCFG1_IOEN_MASK 0xf00000U
#define FTMCTRL_MCFG1_IOEN_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_IOEN_MASK ) >> \
FTMCTRL_MCFG1_IOEN_SHIFT )
#define FTMCTRL_MCFG1_IOEN_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_IOEN_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_IOEN_SHIFT ) & \
FTMCTRL_MCFG1_IOEN_MASK ) )
#define FTMCTRL_MCFG1_IOEN( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_IOEN_SHIFT ) & \
FTMCTRL_MCFG1_IOEN_MASK )
#define FTMCTRL_MCFG1_ROMBANKSZ 0x80000U
#define FTMCTRL_MCFG1_PWEN_SHIFT 14
#define FTMCTRL_MCFG1_PWEN_MASK 0x3c000U
#define FTMCTRL_MCFG1_PWEN_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PWEN_MASK ) >> \
FTMCTRL_MCFG1_PWEN_SHIFT )
#define FTMCTRL_MCFG1_PWEN_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PWEN_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_PWEN_SHIFT ) & \
FTMCTRL_MCFG1_PWEN_MASK ) )
#define FTMCTRL_MCFG1_PWEN( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_PWEN_SHIFT ) & \
FTMCTRL_MCFG1_PWEN_MASK )
#define FTMCTRL_MCFG1_PROM_WIDTH_SHIFT 12
#define FTMCTRL_MCFG1_PROM_WIDTH_MASK 0x3000U
#define FTMCTRL_MCFG1_PROM_WIDTH_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PROM_WIDTH_MASK ) >> \
FTMCTRL_MCFG1_PROM_WIDTH_SHIFT )
#define FTMCTRL_MCFG1_PROM_WIDTH_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_WIDTH_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WIDTH_MASK ) )
#define FTMCTRL_MCFG1_PROM_WIDTH( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_WIDTH_SHIFT ) & \
FTMCTRL_MCFG1_PROM_WIDTH_MASK )
#define FTMCTRL_MCFG1_PROM_WRITE_WS 0x800U
#define FTMCTRL_MCFG1_PROM_READ_WS_SHIFT 8
#define FTMCTRL_MCFG1_PROM_READ_WS_MASK 0x300U
#define FTMCTRL_MCFG1_PROM_READ_WS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG1_PROM_READ_WS_MASK ) >> \
FTMCTRL_MCFG1_PROM_READ_WS_SHIFT )
#define FTMCTRL_MCFG1_PROM_READ_WS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG1_PROM_READ_WS_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \
FTMCTRL_MCFG1_PROM_READ_WS_MASK ) )
#define FTMCTRL_MCFG1_PROM_READ_WS( _val ) \
( ( ( _val ) << FTMCTRL_MCFG1_PROM_READ_WS_SHIFT ) & \
FTMCTRL_MCFG1_PROM_READ_WS_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG3 \
* Memory configuration register 3 (MCFG3)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define FTMCTRL_MCFG3_ME 0x8000000U
#define FTMCTRL_MCFG3_WB 0x800U
#define FTMCTRL_MCFG3_RB 0x400U
#define FTMCTRL_MCFG3_PE 0x100U
#define FTMCTRL_MCFG3_TCB_SHIFT 0
#define FTMCTRL_MCFG3_TCB_MASK 0xffU
#define FTMCTRL_MCFG3_TCB_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG3_TCB_MASK ) >> \
FTMCTRL_MCFG3_TCB_SHIFT )
#define FTMCTRL_MCFG3_TCB_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG3_TCB_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \
FTMCTRL_MCFG3_TCB_MASK ) )
#define FTMCTRL_MCFG3_TCB( _val ) \
( ( ( _val ) << FTMCTRL_MCFG3_TCB_SHIFT ) & \
FTMCTRL_MCFG3_TCB_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG5 \
* Memory configuration register 5 (MCFG5)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define FTMCTRL_MCFG5_IOHWS_SHIFT 23
#define FTMCTRL_MCFG5_IOHWS_MASK 0x3f800000U
#define FTMCTRL_MCFG5_IOHWS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG5_IOHWS_MASK ) >> \
FTMCTRL_MCFG5_IOHWS_SHIFT )
#define FTMCTRL_MCFG5_IOHWS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG5_IOHWS_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \
FTMCTRL_MCFG5_IOHWS_MASK ) )
#define FTMCTRL_MCFG5_IOHWS( _val ) \
( ( ( _val ) << FTMCTRL_MCFG5_IOHWS_SHIFT ) & \
FTMCTRL_MCFG5_IOHWS_MASK )
#define FTMCTRL_MCFG5_ROMHWS_SHIFT 7
#define FTMCTRL_MCFG5_ROMHWS_MASK 0x3f80U
#define FTMCTRL_MCFG5_ROMHWS_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG5_ROMHWS_MASK ) >> \
FTMCTRL_MCFG5_ROMHWS_SHIFT )
#define FTMCTRL_MCFG5_ROMHWS_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG5_ROMHWS_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \
FTMCTRL_MCFG5_ROMHWS_MASK ) )
#define FTMCTRL_MCFG5_ROMHWS( _val ) \
( ( ( _val ) << FTMCTRL_MCFG5_ROMHWS_SHIFT ) & \
FTMCTRL_MCFG5_ROMHWS_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBFTMCTRLMCFG7 \
* Memory configuration register 7 (MCFG7)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define FTMCTRL_MCFG7_BRDYNCNT_SHIFT 16
#define FTMCTRL_MCFG7_BRDYNCNT_MASK 0xffff0000U
#define FTMCTRL_MCFG7_BRDYNCNT_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNCNT_MASK ) >> \
FTMCTRL_MCFG7_BRDYNCNT_SHIFT )
#define FTMCTRL_MCFG7_BRDYNCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNCNT_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \
FTMCTRL_MCFG7_BRDYNCNT_MASK ) )
#define FTMCTRL_MCFG7_BRDYNCNT( _val ) \
( ( ( _val ) << FTMCTRL_MCFG7_BRDYNCNT_SHIFT ) & \
FTMCTRL_MCFG7_BRDYNCNT_MASK )
#define FTMCTRL_MCFG7_BRDYNRLD_SHIFT 0
#define FTMCTRL_MCFG7_BRDYNRLD_MASK 0xffffU
#define FTMCTRL_MCFG7_BRDYNRLD_GET( _reg ) \
( ( ( _reg ) & FTMCTRL_MCFG7_BRDYNRLD_MASK ) >> \
FTMCTRL_MCFG7_BRDYNRLD_SHIFT )
#define FTMCTRL_MCFG7_BRDYNRLD_SET( _reg, _val ) \
( ( ( _reg ) & ~FTMCTRL_MCFG7_BRDYNRLD_MASK ) | \
( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \
FTMCTRL_MCFG7_BRDYNRLD_MASK ) )
#define FTMCTRL_MCFG7_BRDYNRLD( _val ) \
( ( ( _val ) << FTMCTRL_MCFG7_BRDYNRLD_SHIFT ) & \
FTMCTRL_MCFG7_BRDYNRLD_MASK )
/** @} */
/**
* @brief This structure defines the FTMCTRL register block memory map.
*/
typedef struct ftmctrl {
/**
* @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG1.
*/
uint32_t mcfg1;
uint32_t reserved_4_8;
/**
* @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG3.
*/
uint32_t mcfg3;
uint32_t reserved_c_10;
/**
* @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG5.
*/
uint32_t mcfg5;
uint32_t reserved_14_18;
/**
* @brief See @ref RTEMSDeviceGRLIBFTMCTRLMCFG7.
*/
uint32_t mcfg7;
} ftmctrl;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_FTMCTRL_REGS_H */
bsps/include/grlib/gptimer-regs.h
+379
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@@ -0,0 +1,379 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBGPTIMER
*
* @brief This header file defines the GPTIMER register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/gptimer-header */
#ifndef _GRLIB_GPTIMER_REGS_H
#define _GRLIB_GPTIMER_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/group */
/**
* @defgroup RTEMSDeviceGRLIB GRLIB
*
* @ingroup RTEMSDeviceDrivers
*
* @brief This group contains the GRLIB interfaces.
*/
/* Generated from spec:/dev/grlib/if/gptimer-timer */
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERTimer GPTIMER TIMER
*
* @ingroup RTEMSDeviceGRLIBGPTIMER
*
* @brief This group contains the GPTIMER TIMER interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERTimerTCNTVAL \
* Timer n counter value register (TCNTVAL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GPTIMER_TCNTVAL_TCVAL_SHIFT 0
#define GPTIMER_TCNTVAL_TCVAL_MASK 0xffffffffU
#define GPTIMER_TCNTVAL_TCVAL_GET( _reg ) \
( ( ( _reg ) & GPTIMER_TCNTVAL_TCVAL_MASK ) >> \
GPTIMER_TCNTVAL_TCVAL_SHIFT )
#define GPTIMER_TCNTVAL_TCVAL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TCNTVAL_TCVAL_MASK ) | \
( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \
GPTIMER_TCNTVAL_TCVAL_MASK ) )
#define GPTIMER_TCNTVAL_TCVAL( _val ) \
( ( ( _val ) << GPTIMER_TCNTVAL_TCVAL_SHIFT ) & \
GPTIMER_TCNTVAL_TCVAL_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERTimerTRLDVAL \
* Timer n counter reload value register (TRLDVAL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GPTIMER_TRLDVAL_TRLDVAL_SHIFT 0
#define GPTIMER_TRLDVAL_TRLDVAL_MASK 0xffffffffU
#define GPTIMER_TRLDVAL_TRLDVAL_GET( _reg ) \
( ( ( _reg ) & GPTIMER_TRLDVAL_TRLDVAL_MASK ) >> \
GPTIMER_TRLDVAL_TRLDVAL_SHIFT )
#define GPTIMER_TRLDVAL_TRLDVAL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TRLDVAL_TRLDVAL_MASK ) | \
( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \
GPTIMER_TRLDVAL_TRLDVAL_MASK ) )
#define GPTIMER_TRLDVAL_TRLDVAL( _val ) \
( ( ( _val ) << GPTIMER_TRLDVAL_TRLDVAL_SHIFT ) & \
GPTIMER_TRLDVAL_TRLDVAL_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERTimerTCTRL Timer n control register (TCTRL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GPTIMER_TCTRL_WS 0x100U
#define GPTIMER_TCTRL_WN 0x80U
#define GPTIMER_TCTRL_DH 0x40U
#define GPTIMER_TCTRL_CH 0x20U
#define GPTIMER_TCTRL_IP 0x10U
#define GPTIMER_TCTRL_IE 0x8U
#define GPTIMER_TCTRL_LD 0x4U
#define GPTIMER_TCTRL_RS 0x2U
#define GPTIMER_TCTRL_EN 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERTimerTLATCH Timer n latch register (TLATCH)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GPTIMER_TLATCH_LTCV_SHIFT 0
#define GPTIMER_TLATCH_LTCV_MASK 0xffffffffU
#define GPTIMER_TLATCH_LTCV_GET( _reg ) \
( ( ( _reg ) & GPTIMER_TLATCH_LTCV_MASK ) >> \
GPTIMER_TLATCH_LTCV_SHIFT )
#define GPTIMER_TLATCH_LTCV_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_TLATCH_LTCV_MASK ) | \
( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \
GPTIMER_TLATCH_LTCV_MASK ) )
#define GPTIMER_TLATCH_LTCV( _val ) \
( ( ( _val ) << GPTIMER_TLATCH_LTCV_SHIFT ) & \
GPTIMER_TLATCH_LTCV_MASK )
/** @} */
/**
* @brief This structure defines the GPTIMER TIMER register block memory map.
*/
typedef struct gptimer_timer {
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTCNTVAL.
*/
uint32_t tcntval;
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTRLDVAL.
*/
uint32_t trldval;
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTCTRL.
*/
uint32_t tctrl;
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERTimerTLATCH.
*/
uint32_t tlatch;
} gptimer_timer;
/** @} */
/* Generated from spec:/dev/grlib/if/gptimer */
/**
* @defgroup RTEMSDeviceGRLIBGPTIMER GPTIMER
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the GPTIMER interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERSCALER Scaler value register (SCALER)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GPTIMER_SCALER_SCALER_SHIFT 0
#define GPTIMER_SCALER_SCALER_MASK 0xffffU
#define GPTIMER_SCALER_SCALER_GET( _reg ) \
( ( ( _reg ) & GPTIMER_SCALER_SCALER_MASK ) >> \
GPTIMER_SCALER_SCALER_SHIFT )
#define GPTIMER_SCALER_SCALER_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_SCALER_SCALER_MASK ) | \
( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \
GPTIMER_SCALER_SCALER_MASK ) )
#define GPTIMER_SCALER_SCALER( _val ) \
( ( ( _val ) << GPTIMER_SCALER_SCALER_SHIFT ) & \
GPTIMER_SCALER_SCALER_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERSRELOAD \
* Scaler reload value register (SRELOAD)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GPTIMER_SRELOAD_SRELOAD_SHIFT 0
#define GPTIMER_SRELOAD_SRELOAD_MASK 0xffffU
#define GPTIMER_SRELOAD_SRELOAD_GET( _reg ) \
( ( ( _reg ) & GPTIMER_SRELOAD_SRELOAD_MASK ) >> \
GPTIMER_SRELOAD_SRELOAD_SHIFT )
#define GPTIMER_SRELOAD_SRELOAD_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_SRELOAD_SRELOAD_MASK ) | \
( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \
GPTIMER_SRELOAD_SRELOAD_MASK ) )
#define GPTIMER_SRELOAD_SRELOAD( _val ) \
( ( ( _val ) << GPTIMER_SRELOAD_SRELOAD_SHIFT ) & \
GPTIMER_SRELOAD_SRELOAD_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERCONFIG Configuration register (CONFIG)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GPTIMER_CONFIG_EV 0x2000U
#define GPTIMER_CONFIG_ES 0x1000U
#define GPTIMER_CONFIG_EL 0x800U
#define GPTIMER_CONFIG_EE 0x400U
#define GPTIMER_CONFIG_DF 0x200U
#define GPTIMER_CONFIG_SI 0x100U
#define GPTIMER_CONFIG_IRQ_SHIFT 3
#define GPTIMER_CONFIG_IRQ_MASK 0xf8U
#define GPTIMER_CONFIG_IRQ_GET( _reg ) \
( ( ( _reg ) & GPTIMER_CONFIG_IRQ_MASK ) >> \
GPTIMER_CONFIG_IRQ_SHIFT )
#define GPTIMER_CONFIG_IRQ_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_CONFIG_IRQ_MASK ) | \
( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \
GPTIMER_CONFIG_IRQ_MASK ) )
#define GPTIMER_CONFIG_IRQ( _val ) \
( ( ( _val ) << GPTIMER_CONFIG_IRQ_SHIFT ) & \
GPTIMER_CONFIG_IRQ_MASK )
#define GPTIMER_CONFIG_TIMERS_SHIFT 0
#define GPTIMER_CONFIG_TIMERS_MASK 0x7U
#define GPTIMER_CONFIG_TIMERS_GET( _reg ) \
( ( ( _reg ) & GPTIMER_CONFIG_TIMERS_MASK ) >> \
GPTIMER_CONFIG_TIMERS_SHIFT )
#define GPTIMER_CONFIG_TIMERS_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_CONFIG_TIMERS_MASK ) | \
( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \
GPTIMER_CONFIG_TIMERS_MASK ) )
#define GPTIMER_CONFIG_TIMERS( _val ) \
( ( ( _val ) << GPTIMER_CONFIG_TIMERS_SHIFT ) & \
GPTIMER_CONFIG_TIMERS_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBGPTIMERLATCHCFG \
* Timer latch configuration register (LATCHCFG)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GPTIMER_LATCHCFG_LATCHSEL_SHIFT 0
#define GPTIMER_LATCHCFG_LATCHSEL_MASK 0xffffffffU
#define GPTIMER_LATCHCFG_LATCHSEL_GET( _reg ) \
( ( ( _reg ) & GPTIMER_LATCHCFG_LATCHSEL_MASK ) >> \
GPTIMER_LATCHCFG_LATCHSEL_SHIFT )
#define GPTIMER_LATCHCFG_LATCHSEL_SET( _reg, _val ) \
( ( ( _reg ) & ~GPTIMER_LATCHCFG_LATCHSEL_MASK ) | \
( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \
GPTIMER_LATCHCFG_LATCHSEL_MASK ) )
#define GPTIMER_LATCHCFG_LATCHSEL( _val ) \
( ( ( _val ) << GPTIMER_LATCHCFG_LATCHSEL_SHIFT ) & \
GPTIMER_LATCHCFG_LATCHSEL_MASK )
/** @} */
/**
* @brief This structure defines the GPTIMER register block memory map.
*/
typedef struct gptimer {
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERSCALER.
*/
uint32_t scaler;
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERSRELOAD.
*/
uint32_t sreload;
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERCONFIG.
*/
uint32_t config;
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERLATCHCFG.
*/
uint32_t latchcfg;
/**
* @brief See @ref RTEMSDeviceGRLIBGPTIMERTimer.
*/
gptimer_timer timer[ 15 ];
} gptimer;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_GPTIMER_REGS_H */
bsps/include/grlib/gr1553b-regs.h
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bsps/include/grlib/gr740thsens-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGR740THSENS
*
* @brief This header file defines the GR740THSENS register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/gr740thsens-header */
#ifndef _GRLIB_GR740THSENS_REGS_H
#define _GRLIB_GR740THSENS_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/gr740thsens */
/**
* @defgroup RTEMSDeviceGR740THSENS GR740THSENS
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the GR740THSENS interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGR740THSENSCTRL Control register (CTRL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GR740THSENS_CTRL_DIV_SHIFT 16
#define GR740THSENS_CTRL_DIV_MASK 0x3ff0000U
#define GR740THSENS_CTRL_DIV_GET( _reg ) \
( ( ( _reg ) & GR740THSENS_CTRL_DIV_MASK ) >> \
GR740THSENS_CTRL_DIV_SHIFT )
#define GR740THSENS_CTRL_DIV_SET( _reg, _val ) \
( ( ( _reg ) & ~GR740THSENS_CTRL_DIV_MASK ) | \
( ( ( _val ) << GR740THSENS_CTRL_DIV_SHIFT ) & \
GR740THSENS_CTRL_DIV_MASK ) )
#define GR740THSENS_CTRL_DIV( _val ) \
( ( ( _val ) << GR740THSENS_CTRL_DIV_SHIFT ) & \
GR740THSENS_CTRL_DIV_MASK )
#define GR740THSENS_CTRL_ALEN 0x100U
#define GR740THSENS_CTRL_PDN 0x80U
#define GR740THSENS_CTRL_DCORRECT_SHIFT 2
#define GR740THSENS_CTRL_DCORRECT_MASK 0x7cU
#define GR740THSENS_CTRL_DCORRECT_GET( _reg ) \
( ( ( _reg ) & GR740THSENS_CTRL_DCORRECT_MASK ) >> \
GR740THSENS_CTRL_DCORRECT_SHIFT )
#define GR740THSENS_CTRL_DCORRECT_SET( _reg, _val ) \
( ( ( _reg ) & ~GR740THSENS_CTRL_DCORRECT_MASK ) | \
( ( ( _val ) << GR740THSENS_CTRL_DCORRECT_SHIFT ) & \
GR740THSENS_CTRL_DCORRECT_MASK ) )
#define GR740THSENS_CTRL_DCORRECT( _val ) \
( ( ( _val ) << GR740THSENS_CTRL_DCORRECT_SHIFT ) & \
GR740THSENS_CTRL_DCORRECT_MASK )
#define GR740THSENS_CTRL_SRSTN 0x2U
#define GR740THSENS_CTRL_CLKEN 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGR740THSENSSTATUS Status register (STATUS)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GR740THSENS_STATUS_MAX_SHIFT 24
#define GR740THSENS_STATUS_MAX_MASK 0x7f000000U
#define GR740THSENS_STATUS_MAX_GET( _reg ) \
( ( ( _reg ) & GR740THSENS_STATUS_MAX_MASK ) >> \
GR740THSENS_STATUS_MAX_SHIFT )
#define GR740THSENS_STATUS_MAX_SET( _reg, _val ) \
( ( ( _reg ) & ~GR740THSENS_STATUS_MAX_MASK ) | \
( ( ( _val ) << GR740THSENS_STATUS_MAX_SHIFT ) & \
GR740THSENS_STATUS_MAX_MASK ) )
#define GR740THSENS_STATUS_MAX( _val ) \
( ( ( _val ) << GR740THSENS_STATUS_MAX_SHIFT ) & \
GR740THSENS_STATUS_MAX_MASK )
#define GR740THSENS_STATUS_MIN_SHIFT 16
#define GR740THSENS_STATUS_MIN_MASK 0x7f0000U
#define GR740THSENS_STATUS_MIN_GET( _reg ) \
( ( ( _reg ) & GR740THSENS_STATUS_MIN_MASK ) >> \
GR740THSENS_STATUS_MIN_SHIFT )
#define GR740THSENS_STATUS_MIN_SET( _reg, _val ) \
( ( ( _reg ) & ~GR740THSENS_STATUS_MIN_MASK ) | \
( ( ( _val ) << GR740THSENS_STATUS_MIN_SHIFT ) & \
GR740THSENS_STATUS_MIN_MASK ) )
#define GR740THSENS_STATUS_MIN( _val ) \
( ( ( _val ) << GR740THSENS_STATUS_MIN_SHIFT ) & \
GR740THSENS_STATUS_MIN_MASK )
#define GR740THSENS_STATUS_SCLK 0x8000U
#define GR740THSENS_STATUS_WE 0x400U
#define GR740THSENS_STATUS_UPD 0x200U
#define GR740THSENS_STATUS_ALACT 0x100U
#define GR740THSENS_STATUS_DATA_SHIFT 0
#define GR740THSENS_STATUS_DATA_MASK 0x7fU
#define GR740THSENS_STATUS_DATA_GET( _reg ) \
( ( ( _reg ) & GR740THSENS_STATUS_DATA_MASK ) >> \
GR740THSENS_STATUS_DATA_SHIFT )
#define GR740THSENS_STATUS_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GR740THSENS_STATUS_DATA_MASK ) | \
( ( ( _val ) << GR740THSENS_STATUS_DATA_SHIFT ) & \
GR740THSENS_STATUS_DATA_MASK ) )
#define GR740THSENS_STATUS_DATA( _val ) \
( ( ( _val ) << GR740THSENS_STATUS_DATA_SHIFT ) & \
GR740THSENS_STATUS_DATA_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGR740THSENSTHRES Threshold register (THRES)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GR740THSENS_THRES_THRES_SHIFT 0
#define GR740THSENS_THRES_THRES_MASK 0x7fU
#define GR740THSENS_THRES_THRES_GET( _reg ) \
( ( ( _reg ) & GR740THSENS_THRES_THRES_MASK ) >> \
GR740THSENS_THRES_THRES_SHIFT )
#define GR740THSENS_THRES_THRES_SET( _reg, _val ) \
( ( ( _reg ) & ~GR740THSENS_THRES_THRES_MASK ) | \
( ( ( _val ) << GR740THSENS_THRES_THRES_SHIFT ) & \
GR740THSENS_THRES_THRES_MASK ) )
#define GR740THSENS_THRES_THRES( _val ) \
( ( ( _val ) << GR740THSENS_THRES_THRES_SHIFT ) & \
GR740THSENS_THRES_THRES_MASK )
/** @} */
/**
* @brief This structure defines the GR740THSENS register block memory map.
*/
typedef struct gr740thsens {
/**
* @brief See @ref RTEMSDeviceGR740THSENSCTRL.
*/
uint32_t ctrl;
/**
* @brief See @ref RTEMSDeviceGR740THSENSSTATUS.
*/
uint32_t status;
/**
* @brief See @ref RTEMSDeviceGR740THSENSTHRES.
*/
uint32_t thres;
} gr740thsens;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_GR740THSENS_REGS_H */
bsps/include/grlib/grcan-regs.h
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bsps/include/grlib/grclkgate-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRCLKGATE
*
* @brief This header file defines the GRCLKGATE register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/grclkgate-header */
#ifndef _GRLIB_GRCLKGATE_REGS_H
#define _GRLIB_GRCLKGATE_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/grclkgate */
/**
* @defgroup RTEMSDeviceGRCLKGATE GRCLKGATE
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the GRCLKGATE interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRCLKGATEUNLOCK Unlock register (UNLOCK)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRCLKGATE_UNLOCK_UNLOCK_SHIFT 0
#define GRCLKGATE_UNLOCK_UNLOCK_MASK 0x7ffU
#define GRCLKGATE_UNLOCK_UNLOCK_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_UNLOCK_UNLOCK_MASK ) >> \
GRCLKGATE_UNLOCK_UNLOCK_SHIFT )
#define GRCLKGATE_UNLOCK_UNLOCK_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_UNLOCK_UNLOCK_MASK ) | \
( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \
GRCLKGATE_UNLOCK_UNLOCK_MASK ) )
#define GRCLKGATE_UNLOCK_UNLOCK( _val ) \
( ( ( _val ) << GRCLKGATE_UNLOCK_UNLOCK_SHIFT ) & \
GRCLKGATE_UNLOCK_UNLOCK_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRCLKGATECLKEN Clock enable register (CLKEN)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRCLKGATE_CLKEN_ENABLE_SHIFT 0
#define GRCLKGATE_CLKEN_ENABLE_MASK 0x7ffU
#define GRCLKGATE_CLKEN_ENABLE_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_CLKEN_ENABLE_MASK ) >> \
GRCLKGATE_CLKEN_ENABLE_SHIFT )
#define GRCLKGATE_CLKEN_ENABLE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_CLKEN_ENABLE_MASK ) | \
( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \
GRCLKGATE_CLKEN_ENABLE_MASK ) )
#define GRCLKGATE_CLKEN_ENABLE( _val ) \
( ( ( _val ) << GRCLKGATE_CLKEN_ENABLE_SHIFT ) & \
GRCLKGATE_CLKEN_ENABLE_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRCLKGATERESET Reset register (RESET)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRCLKGATE_RESET_RESET_SHIFT 0
#define GRCLKGATE_RESET_RESET_MASK 0x7ffU
#define GRCLKGATE_RESET_RESET_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_RESET_RESET_MASK ) >> \
GRCLKGATE_RESET_RESET_SHIFT )
#define GRCLKGATE_RESET_RESET_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_RESET_RESET_MASK ) | \
( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \
GRCLKGATE_RESET_RESET_MASK ) )
#define GRCLKGATE_RESET_RESET( _val ) \
( ( ( _val ) << GRCLKGATE_RESET_RESET_SHIFT ) & \
GRCLKGATE_RESET_RESET_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRCLKGATEOVERRIDE CPU/FPU override register (OVERRIDE)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT 16
#define GRCLKGATE_OVERRIDE_FOVERRIDE_MASK 0xf0000U
#define GRCLKGATE_OVERRIDE_FOVERRIDE_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) >> \
GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT )
#define GRCLKGATE_OVERRIDE_FOVERRIDE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) | \
( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \
GRCLKGATE_OVERRIDE_FOVERRIDE_MASK ) )
#define GRCLKGATE_OVERRIDE_FOVERRIDE( _val ) \
( ( ( _val ) << GRCLKGATE_OVERRIDE_FOVERRIDE_SHIFT ) & \
GRCLKGATE_OVERRIDE_FOVERRIDE_MASK )
#define GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT 0
#define GRCLKGATE_OVERRIDE_OVERRIDE_MASK 0xfU
#define GRCLKGATE_OVERRIDE_OVERRIDE_GET( _reg ) \
( ( ( _reg ) & GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) >> \
GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT )
#define GRCLKGATE_OVERRIDE_OVERRIDE_SET( _reg, _val ) \
( ( ( _reg ) & ~GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) | \
( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \
GRCLKGATE_OVERRIDE_OVERRIDE_MASK ) )
#define GRCLKGATE_OVERRIDE_OVERRIDE( _val ) \
( ( ( _val ) << GRCLKGATE_OVERRIDE_OVERRIDE_SHIFT ) & \
GRCLKGATE_OVERRIDE_OVERRIDE_MASK )
/** @} */
/**
* @brief This structure defines the GRCLKGATE register block memory map.
*/
typedef struct grclkgate {
/**
* @brief See @ref RTEMSDeviceGRCLKGATEUNLOCK.
*/
uint32_t unlock;
/**
* @brief See @ref RTEMSDeviceGRCLKGATECLKEN.
*/
uint32_t clken;
/**
* @brief See @ref RTEMSDeviceGRCLKGATERESET.
*/
uint32_t reset;
/**
* @brief See @ref RTEMSDeviceGRCLKGATEOVERRIDE.
*/
uint32_t override;
} grclkgate;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_GRCLKGATE_REGS_H */
bsps/include/grlib/grethgbit-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRETHGBIT
*
* @brief This header file defines the GRETH_GBIT register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/grethgbit-header */
#ifndef _GRLIB_GRETHGBIT_REGS_H
#define _GRLIB_GRETHGBIT_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/grethgbit */
/**
* @defgroup RTEMSDeviceGRETHGBIT GRETH_GBIT
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the GRETH_GBIT interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRETHGBITCR control register (CR)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_CR_EA 0x80000000U
#define GRETHGBIT_CR_BS_SHIFT 28
#define GRETHGBIT_CR_BS_MASK 0x70000000U
#define GRETHGBIT_CR_BS_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_CR_BS_MASK ) >> \
GRETHGBIT_CR_BS_SHIFT )
#define GRETHGBIT_CR_BS_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_CR_BS_MASK ) | \
( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
GRETHGBIT_CR_BS_MASK ) )
#define GRETHGBIT_CR_BS( _val ) \
( ( ( _val ) << GRETHGBIT_CR_BS_SHIFT ) & \
GRETHGBIT_CR_BS_MASK )
#define GRETHGBIT_CR_GA 0x8000000U
#define GRETHGBIT_CR_MA 0x4000000U
#define GRETHGBIT_CR_MC 0x2000000U
#define GRETHGBIT_CR_ED 0x4000U
#define GRETHGBIT_CR_RD 0x2000U
#define GRETHGBIT_CR_DD 0x1000U
#define GRETHGBIT_CR_ME 0x800U
#define GRETHGBIT_CR_PI 0x400U
#define GRETHGBIT_CR_BM 0x200U
#define GRETHGBIT_CR_GB 0x100U
#define GRETHGBIT_CR_SP 0x80U
#define GRETHGBIT_CR_RS 0x40U
#define GRETHGBIT_CR_PM 0x20U
#define GRETHGBIT_CR_FD 0x10U
#define GRETHGBIT_CR_RI 0x8U
#define GRETHGBIT_CR_TI 0x4U
#define GRETHGBIT_CR_RE 0x2U
#define GRETHGBIT_CR_TE 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRETHGBITSR status register. (SR)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_SR_PS 0x100U
#define GRETHGBIT_SR_IA 0x80U
#define GRETHGBIT_SR_TS 0x40U
#define GRETHGBIT_SR_TA 0x20U
#define GRETHGBIT_SR_RA 0x10U
#define GRETHGBIT_SR_TI 0x8U
#define GRETHGBIT_SR_RI 0x4U
#define GRETHGBIT_SR_TE 0x2U
#define GRETHGBIT_SR_RE 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRETHGBITMACMSB MAC address MSB. (MACMSB)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_MACMSB_MSB_SHIFT 0
#define GRETHGBIT_MACMSB_MSB_MASK 0xffffU
#define GRETHGBIT_MACMSB_MSB_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MACMSB_MSB_MASK ) >> \
GRETHGBIT_MACMSB_MSB_SHIFT )
#define GRETHGBIT_MACMSB_MSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MACMSB_MSB_MASK ) | \
( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
GRETHGBIT_MACMSB_MSB_MASK ) )
#define GRETHGBIT_MACMSB_MSB( _val ) \
( ( ( _val ) << GRETHGBIT_MACMSB_MSB_SHIFT ) & \
GRETHGBIT_MACMSB_MSB_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRETHGBITMACLSB MAC address LSB. (MACLSB)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_MACLSB_LSB_SHIFT 0
#define GRETHGBIT_MACLSB_LSB_MASK 0xffffffffU
#define GRETHGBIT_MACLSB_LSB_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MACLSB_LSB_MASK ) >> \
GRETHGBIT_MACLSB_LSB_SHIFT )
#define GRETHGBIT_MACLSB_LSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MACLSB_LSB_MASK ) | \
( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
GRETHGBIT_MACLSB_LSB_MASK ) )
#define GRETHGBIT_MACLSB_LSB( _val ) \
( ( ( _val ) << GRETHGBIT_MACLSB_LSB_SHIFT ) & \
GRETHGBIT_MACLSB_LSB_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRETHGBITMDIO MDIO control/status register. (MDIO)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_MDIO_DATA_SHIFT 16
#define GRETHGBIT_MDIO_DATA_MASK 0xffff0000U
#define GRETHGBIT_MDIO_DATA_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MDIO_DATA_MASK ) >> \
GRETHGBIT_MDIO_DATA_SHIFT )
#define GRETHGBIT_MDIO_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_DATA_MASK ) | \
( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
GRETHGBIT_MDIO_DATA_MASK ) )
#define GRETHGBIT_MDIO_DATA( _val ) \
( ( ( _val ) << GRETHGBIT_MDIO_DATA_SHIFT ) & \
GRETHGBIT_MDIO_DATA_MASK )
#define GRETHGBIT_MDIO_PHYADDR_SHIFT 11
#define GRETHGBIT_MDIO_PHYADDR_MASK 0xf800U
#define GRETHGBIT_MDIO_PHYADDR_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MDIO_PHYADDR_MASK ) >> \
GRETHGBIT_MDIO_PHYADDR_SHIFT )
#define GRETHGBIT_MDIO_PHYADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_PHYADDR_MASK ) | \
( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
GRETHGBIT_MDIO_PHYADDR_MASK ) )
#define GRETHGBIT_MDIO_PHYADDR( _val ) \
( ( ( _val ) << GRETHGBIT_MDIO_PHYADDR_SHIFT ) & \
GRETHGBIT_MDIO_PHYADDR_MASK )
#define GRETHGBIT_MDIO_REGADDR_SHIFT 6
#define GRETHGBIT_MDIO_REGADDR_MASK 0x7c0U
#define GRETHGBIT_MDIO_REGADDR_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_MDIO_REGADDR_MASK ) >> \
GRETHGBIT_MDIO_REGADDR_SHIFT )
#define GRETHGBIT_MDIO_REGADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_MDIO_REGADDR_MASK ) | \
( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
GRETHGBIT_MDIO_REGADDR_MASK ) )
#define GRETHGBIT_MDIO_REGADDR( _val ) \
( ( ( _val ) << GRETHGBIT_MDIO_REGADDR_SHIFT ) & \
GRETHGBIT_MDIO_REGADDR_MASK )
#define GRETHGBIT_MDIO_BU 0x8U
#define GRETHGBIT_MDIO_LF 0x4U
#define GRETHGBIT_MDIO_RD 0x2U
#define GRETHGBIT_MDIO_WR 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRETHGBITTDTBA \
* transmitter descriptor table base address register. (TDTBA)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_TDTBA_BASEADDR_SHIFT 10
#define GRETHGBIT_TDTBA_BASEADDR_MASK 0xfffffc00U
#define GRETHGBIT_TDTBA_BASEADDR_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_TDTBA_BASEADDR_MASK ) >> \
GRETHGBIT_TDTBA_BASEADDR_SHIFT )
#define GRETHGBIT_TDTBA_BASEADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_TDTBA_BASEADDR_MASK ) | \
( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
GRETHGBIT_TDTBA_BASEADDR_MASK ) )
#define GRETHGBIT_TDTBA_BASEADDR( _val ) \
( ( ( _val ) << GRETHGBIT_TDTBA_BASEADDR_SHIFT ) & \
GRETHGBIT_TDTBA_BASEADDR_MASK )
#define GRETHGBIT_TDTBA_DESCPNT_SHIFT 3
#define GRETHGBIT_TDTBA_DESCPNT_MASK 0x3f8U
#define GRETHGBIT_TDTBA_DESCPNT_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_TDTBA_DESCPNT_MASK ) >> \
GRETHGBIT_TDTBA_DESCPNT_SHIFT )
#define GRETHGBIT_TDTBA_DESCPNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_TDTBA_DESCPNT_MASK ) | \
( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
GRETHGBIT_TDTBA_DESCPNT_MASK ) )
#define GRETHGBIT_TDTBA_DESCPNT( _val ) \
( ( ( _val ) << GRETHGBIT_TDTBA_DESCPNT_SHIFT ) & \
GRETHGBIT_TDTBA_DESCPNT_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRETHGBITRDTBA \
* receiver descriptor table base address register. (RDTBA)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_RDTBA_BASEADDR_SHIFT 10
#define GRETHGBIT_RDTBA_BASEADDR_MASK 0xfffffc00U
#define GRETHGBIT_RDTBA_BASEADDR_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_RDTBA_BASEADDR_MASK ) >> \
GRETHGBIT_RDTBA_BASEADDR_SHIFT )
#define GRETHGBIT_RDTBA_BASEADDR_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_RDTBA_BASEADDR_MASK ) | \
( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
GRETHGBIT_RDTBA_BASEADDR_MASK ) )
#define GRETHGBIT_RDTBA_BASEADDR( _val ) \
( ( ( _val ) << GRETHGBIT_RDTBA_BASEADDR_SHIFT ) & \
GRETHGBIT_RDTBA_BASEADDR_MASK )
#define GRETHGBIT_RDTBA_DESCPNT_SHIFT 3
#define GRETHGBIT_RDTBA_DESCPNT_MASK 0x3f8U
#define GRETHGBIT_RDTBA_DESCPNT_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_RDTBA_DESCPNT_MASK ) >> \
GRETHGBIT_RDTBA_DESCPNT_SHIFT )
#define GRETHGBIT_RDTBA_DESCPNT_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_RDTBA_DESCPNT_MASK ) | \
( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
GRETHGBIT_RDTBA_DESCPNT_MASK ) )
#define GRETHGBIT_RDTBA_DESCPNT( _val ) \
( ( ( _val ) << GRETHGBIT_RDTBA_DESCPNT_SHIFT ) & \
GRETHGBIT_RDTBA_DESCPNT_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRETHGBITEDCLMACMSB EDCL MAC address MSB. (EDCLMACMSB)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_EDCLMACMSB_MSB_SHIFT 0
#define GRETHGBIT_EDCLMACMSB_MSB_MASK 0xffffU
#define GRETHGBIT_EDCLMACMSB_MSB_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_EDCLMACMSB_MSB_MASK ) >> \
GRETHGBIT_EDCLMACMSB_MSB_SHIFT )
#define GRETHGBIT_EDCLMACMSB_MSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_EDCLMACMSB_MSB_MASK ) | \
( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
GRETHGBIT_EDCLMACMSB_MSB_MASK ) )
#define GRETHGBIT_EDCLMACMSB_MSB( _val ) \
( ( ( _val ) << GRETHGBIT_EDCLMACMSB_MSB_SHIFT ) & \
GRETHGBIT_EDCLMACMSB_MSB_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRETHGBITEDCLMACLSB EDCL MAC address LSB. (EDCLMACLSB)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRETHGBIT_EDCLMACLSB_LSB_SHIFT 0
#define GRETHGBIT_EDCLMACLSB_LSB_MASK 0xffffffffU
#define GRETHGBIT_EDCLMACLSB_LSB_GET( _reg ) \
( ( ( _reg ) & GRETHGBIT_EDCLMACLSB_LSB_MASK ) >> \
GRETHGBIT_EDCLMACLSB_LSB_SHIFT )
#define GRETHGBIT_EDCLMACLSB_LSB_SET( _reg, _val ) \
( ( ( _reg ) & ~GRETHGBIT_EDCLMACLSB_LSB_MASK ) | \
( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
GRETHGBIT_EDCLMACLSB_LSB_MASK ) )
#define GRETHGBIT_EDCLMACLSB_LSB( _val ) \
( ( ( _val ) << GRETHGBIT_EDCLMACLSB_LSB_SHIFT ) & \
GRETHGBIT_EDCLMACLSB_LSB_MASK )
/** @} */
/**
* @brief This structure defines the GRETH_GBIT register block memory map.
*/
typedef struct grethgbit {
/**
* @brief See @ref RTEMSDeviceGRETHGBITCR.
*/
uint32_t cr;
/**
* @brief See @ref RTEMSDeviceGRETHGBITSR.
*/
uint32_t sr;
/**
* @brief See @ref RTEMSDeviceGRETHGBITMACMSB.
*/
uint32_t macmsb;
/**
* @brief See @ref RTEMSDeviceGRETHGBITMACLSB.
*/
uint32_t maclsb;
/**
* @brief See @ref RTEMSDeviceGRETHGBITMDIO.
*/
uint32_t mdio;
/**
* @brief See @ref RTEMSDeviceGRETHGBITTDTBA.
*/
uint32_t tdtba;
/**
* @brief See @ref RTEMSDeviceGRETHGBITRDTBA.
*/
uint32_t rdtba;
uint32_t reserved_1c_28[ 3 ];
/**
* @brief See @ref RTEMSDeviceGRETHGBITEDCLMACMSB.
*/
uint32_t edclmacmsb;
/**
* @brief See @ref RTEMSDeviceGRETHGBITEDCLMACLSB.
*/
uint32_t edclmaclsb;
} grethgbit;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_GRETHGBIT_REGS_H */
bsps/include/grlib/grgpio-regs.h
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bsps/include/grlib/grgprbank-regs.h
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bsps/include/grlib/grgpreg-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRGPREG
*
* @brief This header file defines the GRGPREG register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/grgpreg-header */
#ifndef _GRLIB_GRGPREG_REGS_H
#define _GRLIB_GRGPREG_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/grgpreg */
/**
* @defgroup RTEMSDeviceGRGPREG GRGPREG
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the GRGPREG interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRGPREGBOOTSTRAP Bootstrap register (BOOTSTRAP)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define GRGPREG_BOOTSTRAP_B10 0x2000000U
#define GRGPREG_BOOTSTRAP_B9 0x1000000U
#define GRGPREG_BOOTSTRAP_B8 0x800000U
#define GRGPREG_BOOTSTRAP_B7 0x400000U
#define GRGPREG_BOOTSTRAP_B6 0x200000U
#define GRGPREG_BOOTSTRAP_B5 0x100000U
#define GRGPREG_BOOTSTRAP_B4 0x80000U
#define GRGPREG_BOOTSTRAP_B3 0x40000U
#define GRGPREG_BOOTSTRAP_B2 0x20000U
#define GRGPREG_BOOTSTRAP_B1 0x10000U
#define GRGPREG_BOOTSTRAP_GPIO_SHIFT 0
#define GRGPREG_BOOTSTRAP_GPIO_MASK 0xffffU
#define GRGPREG_BOOTSTRAP_GPIO_GET( _reg ) \
( ( ( _reg ) & GRGPREG_BOOTSTRAP_GPIO_MASK ) >> \
GRGPREG_BOOTSTRAP_GPIO_SHIFT )
#define GRGPREG_BOOTSTRAP_GPIO_SET( _reg, _val ) \
( ( ( _reg ) & ~GRGPREG_BOOTSTRAP_GPIO_MASK ) | \
( ( ( _val ) << GRGPREG_BOOTSTRAP_GPIO_SHIFT ) & \
GRGPREG_BOOTSTRAP_GPIO_MASK ) )
#define GRGPREG_BOOTSTRAP_GPIO( _val ) \
( ( ( _val ) << GRGPREG_BOOTSTRAP_GPIO_SHIFT ) & \
GRGPREG_BOOTSTRAP_GPIO_MASK )
/** @} */
/**
* @brief This structure defines the GRGPREG register block memory map.
*/
typedef struct grgpreg {
/**
* @brief See @ref RTEMSDeviceGRGPREGBOOTSTRAP.
*/
uint32_t bootstrap;
} grgpreg;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_GRGPREG_REGS_H */
bsps/include/grlib/griommu-regs.h
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bsps/include/grlib/grpci2-regs.h
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bsps/include/grlib/grspw2-regs.h
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bsps/include/grlib/grspwrouter-regs.h
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bsps/include/grlib/irqamp-regs.h
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bsps/include/grlib/irqamp.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBIRQAMP
*
* @brief This header file defines the IRQ(A)MP interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/irqamp-header-2 */
#ifndef _GRLIB_IRQAMP_H
#define _GRLIB_IRQAMP_H
#include <stddef.h>
#include <grlib/io.h>
#include <grlib/irqamp-regs.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/irqamp-get-timestamp */
/**
* @ingroup RTEMSDeviceGRLIBIRQAMP
*
* @brief Gets the interrupt timestamping register bock.
*
* @param irqamp_regs is the IRQ(A)MP register block.
*
* @retval NULL The IRQ(A)MP does not support the interrupt timestamping
* feature.
*
* @return Returns the interrupt timestamping register block.
*/
static inline irqamp_timestamp *irqamp_get_timestamp_registers(
irqamp *irqamp_regs
)
{
irqamp_timestamp *timestamp_regs;
uint32_t itstmpc;
timestamp_regs = &irqamp_regs->itstmp[ 0 ];
itstmpc = grlib_load_32( &timestamp_regs->itstmpc );
if ( IRQAMP_ITSTMPC_TSTAMP_GET( itstmpc ) == 0 ) {
return NULL;
}
return timestamp_regs;
}
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_IRQAMP_H */
bsps/include/grlib/l2cache-regs.h
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bsps/include/grlib/l4stat-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBL4STAT
*
* @brief This header file defines the L4STAT register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/l4stat-header */
#ifndef _GRLIB_L4STAT_REGS_H
#define _GRLIB_L4STAT_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/l4stat */
/**
* @defgroup RTEMSDeviceGRLIBL4STAT L4STAT
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the L4STAT interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBL4STATCVAL Counter 0-15 value register (CVAL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define L4STAT_CVAL_CVAL_SHIFT 0
#define L4STAT_CVAL_CVAL_MASK 0xffffffffU
#define L4STAT_CVAL_CVAL_GET( _reg ) \
( ( ( _reg ) & L4STAT_CVAL_CVAL_MASK ) >> \
L4STAT_CVAL_CVAL_SHIFT )
#define L4STAT_CVAL_CVAL_SET( _reg, _val ) \
( ( ( _reg ) & ~L4STAT_CVAL_CVAL_MASK ) | \
( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \
L4STAT_CVAL_CVAL_MASK ) )
#define L4STAT_CVAL_CVAL( _val ) \
( ( ( _val ) << L4STAT_CVAL_CVAL_SHIFT ) & \
L4STAT_CVAL_CVAL_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBL4STATCCTRL Counter 0-15 control register (CCTRL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define L4STAT_CCTRL_NCPU_SHIFT 28
#define L4STAT_CCTRL_NCPU_MASK 0xf0000000U
#define L4STAT_CCTRL_NCPU_GET( _reg ) \
( ( ( _reg ) & L4STAT_CCTRL_NCPU_MASK ) >> \
L4STAT_CCTRL_NCPU_SHIFT )
#define L4STAT_CCTRL_NCPU_SET( _reg, _val ) \
( ( ( _reg ) & ~L4STAT_CCTRL_NCPU_MASK ) | \
( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
L4STAT_CCTRL_NCPU_MASK ) )
#define L4STAT_CCTRL_NCPU( _val ) \
( ( ( _val ) << L4STAT_CCTRL_NCPU_SHIFT ) & \
L4STAT_CCTRL_NCPU_MASK )
#define L4STAT_CCTRL_NCNT_SHIFT 23
#define L4STAT_CCTRL_NCNT_MASK 0xf800000U
#define L4STAT_CCTRL_NCNT_GET( _reg ) \
( ( ( _reg ) & L4STAT_CCTRL_NCNT_MASK ) >> \
L4STAT_CCTRL_NCNT_SHIFT )
#define L4STAT_CCTRL_NCNT_SET( _reg, _val ) \
( ( ( _reg ) & ~L4STAT_CCTRL_NCNT_MASK ) | \
( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
L4STAT_CCTRL_NCNT_MASK ) )
#define L4STAT_CCTRL_NCNT( _val ) \
( ( ( _val ) << L4STAT_CCTRL_NCNT_SHIFT ) & \
L4STAT_CCTRL_NCNT_MASK )
#define L4STAT_CCTRL_MC 0x400000U
#define L4STAT_CCTRL_IA 0x200000U
#define L4STAT_CCTRL_DS 0x100000U
#define L4STAT_CCTRL_EE 0x80000U
#define L4STAT_CCTRL_AE 0x40000U
#define L4STAT_CCTRL_EL 0x20000U
#define L4STAT_CCTRL_CD 0x10000U
#define L4STAT_CCTRL_SU_SHIFT 14
#define L4STAT_CCTRL_SU_MASK 0xc000U
#define L4STAT_CCTRL_SU_GET( _reg ) \
( ( ( _reg ) & L4STAT_CCTRL_SU_MASK ) >> \
L4STAT_CCTRL_SU_SHIFT )
#define L4STAT_CCTRL_SU_SET( _reg, _val ) \
( ( ( _reg ) & ~L4STAT_CCTRL_SU_MASK ) | \
( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
L4STAT_CCTRL_SU_MASK ) )
#define L4STAT_CCTRL_SU( _val ) \
( ( ( _val ) << L4STAT_CCTRL_SU_SHIFT ) & \
L4STAT_CCTRL_SU_MASK )
#define L4STAT_CCTRL_CL 0x2000U
#define L4STAT_CCTRL_EN 0x1000U
#define L4STAT_CCTRL_EVENT_ID_SHIFT 4
#define L4STAT_CCTRL_EVENT_ID_MASK 0xff0U
#define L4STAT_CCTRL_EVENT_ID_GET( _reg ) \
( ( ( _reg ) & L4STAT_CCTRL_EVENT_ID_MASK ) >> \
L4STAT_CCTRL_EVENT_ID_SHIFT )
#define L4STAT_CCTRL_EVENT_ID_SET( _reg, _val ) \
( ( ( _reg ) & ~L4STAT_CCTRL_EVENT_ID_MASK ) | \
( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
L4STAT_CCTRL_EVENT_ID_MASK ) )
#define L4STAT_CCTRL_EVENT_ID( _val ) \
( ( ( _val ) << L4STAT_CCTRL_EVENT_ID_SHIFT ) & \
L4STAT_CCTRL_EVENT_ID_MASK )
#define L4STAT_CCTRL_CPU_AHBM_SHIFT 0
#define L4STAT_CCTRL_CPU_AHBM_MASK 0xfU
#define L4STAT_CCTRL_CPU_AHBM_GET( _reg ) \
( ( ( _reg ) & L4STAT_CCTRL_CPU_AHBM_MASK ) >> \
L4STAT_CCTRL_CPU_AHBM_SHIFT )
#define L4STAT_CCTRL_CPU_AHBM_SET( _reg, _val ) \
( ( ( _reg ) & ~L4STAT_CCTRL_CPU_AHBM_MASK ) | \
( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
L4STAT_CCTRL_CPU_AHBM_MASK ) )
#define L4STAT_CCTRL_CPU_AHBM( _val ) \
( ( ( _val ) << L4STAT_CCTRL_CPU_AHBM_SHIFT ) & \
L4STAT_CCTRL_CPU_AHBM_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBL4STATCSVAL \
* Counter 0-15 max/latch register (CSVAL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define L4STAT_CSVAL_CSVAL_SHIFT 0
#define L4STAT_CSVAL_CSVAL_MASK 0xffffffffU
#define L4STAT_CSVAL_CSVAL_GET( _reg ) \
( ( ( _reg ) & L4STAT_CSVAL_CSVAL_MASK ) >> \
L4STAT_CSVAL_CSVAL_SHIFT )
#define L4STAT_CSVAL_CSVAL_SET( _reg, _val ) \
( ( ( _reg ) & ~L4STAT_CSVAL_CSVAL_MASK ) | \
( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \
L4STAT_CSVAL_CSVAL_MASK ) )
#define L4STAT_CSVAL_CSVAL( _val ) \
( ( ( _val ) << L4STAT_CSVAL_CSVAL_SHIFT ) & \
L4STAT_CSVAL_CSVAL_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBL4STATTSTAMP Timestamp register (TSTAMP)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define L4STAT_TSTAMP_TSTAMP_SHIFT 0
#define L4STAT_TSTAMP_TSTAMP_MASK 0xffffffffU
#define L4STAT_TSTAMP_TSTAMP_GET( _reg ) \
( ( ( _reg ) & L4STAT_TSTAMP_TSTAMP_MASK ) >> \
L4STAT_TSTAMP_TSTAMP_SHIFT )
#define L4STAT_TSTAMP_TSTAMP_SET( _reg, _val ) \
( ( ( _reg ) & ~L4STAT_TSTAMP_TSTAMP_MASK ) | \
( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \
L4STAT_TSTAMP_TSTAMP_MASK ) )
#define L4STAT_TSTAMP_TSTAMP( _val ) \
( ( ( _val ) << L4STAT_TSTAMP_TSTAMP_SHIFT ) & \
L4STAT_TSTAMP_TSTAMP_MASK )
/** @} */
/**
* @brief This structure defines the L4STAT register block memory map.
*/
typedef struct l4stat {
/**
* @brief See @ref RTEMSDeviceGRLIBL4STATCVAL.
*/
uint32_t cval_0;
uint32_t reserved_4_3c[ 14 ];
/**
* @brief See @ref RTEMSDeviceGRLIBL4STATCVAL.
*/
uint32_t cval_1;
uint32_t reserved_40_80[ 16 ];
/**
* @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL.
*/
uint32_t cctrl_0;
uint32_t reserved_84_cc[ 18 ];
/**
* @brief See @ref RTEMSDeviceGRLIBL4STATCCTRL.
*/
uint32_t cctrl_1;
uint32_t reserved_d0_100[ 12 ];
/**
* @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL.
*/
uint32_t csval_0;
uint32_t reserved_104_13c[ 14 ];
/**
* @brief See @ref RTEMSDeviceGRLIBL4STATCSVAL.
*/
uint32_t csval_1;
uint32_t reserved_140_180[ 16 ];
/**
* @brief See @ref RTEMSDeviceGRLIBL4STATTSTAMP.
*/
uint32_t tstamp;
} l4stat;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_L4STAT_REGS_H */
bsps/include/grlib/memscrub-regs.h
+568
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bsps/include/grlib/mmctrl-regs.h
+434
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@@ -0,0 +1,434 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBMMCTRL
*
* @brief This header file defines the MMCTRL register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/mmctrl-header */
#ifndef _GRLIB_MMCTRL_REGS_H
#define _GRLIB_MMCTRL_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/mmctrl */
/**
* @defgroup RTEMSDeviceGRLIBMMCTRL MMCTRL
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the MMCTRL interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBMMCTRLSDCFG1 \
* SDRAM configuration register 1 (SDCFG1)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define MMCTRL_SDCFG1_RF 0x80000000U
#define MMCTRL_SDCFG1_TRP 0x40000000U
#define MMCTRL_SDCFG1_TRFC_SHIFT 27
#define MMCTRL_SDCFG1_TRFC_MASK 0x38000000U
#define MMCTRL_SDCFG1_TRFC_GET( _reg ) \
( ( ( _reg ) & MMCTRL_SDCFG1_TRFC_MASK ) >> \
MMCTRL_SDCFG1_TRFC_SHIFT )
#define MMCTRL_SDCFG1_TRFC_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_SDCFG1_TRFC_MASK ) | \
( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \
MMCTRL_SDCFG1_TRFC_MASK ) )
#define MMCTRL_SDCFG1_TRFC( _val ) \
( ( ( _val ) << MMCTRL_SDCFG1_TRFC_SHIFT ) & \
MMCTRL_SDCFG1_TRFC_MASK )
#define MMCTRL_SDCFG1_TC 0x4000000U
#define MMCTRL_SDCFG1_BANKSZ_SHIFT 23
#define MMCTRL_SDCFG1_BANKSZ_MASK 0x3800000U
#define MMCTRL_SDCFG1_BANKSZ_GET( _reg ) \
( ( ( _reg ) & MMCTRL_SDCFG1_BANKSZ_MASK ) >> \
MMCTRL_SDCFG1_BANKSZ_SHIFT )
#define MMCTRL_SDCFG1_BANKSZ_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_SDCFG1_BANKSZ_MASK ) | \
( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \
MMCTRL_SDCFG1_BANKSZ_MASK ) )
#define MMCTRL_SDCFG1_BANKSZ( _val ) \
( ( ( _val ) << MMCTRL_SDCFG1_BANKSZ_SHIFT ) & \
MMCTRL_SDCFG1_BANKSZ_MASK )
#define MMCTRL_SDCFG1_COLSZ_SHIFT 21
#define MMCTRL_SDCFG1_COLSZ_MASK 0x600000U
#define MMCTRL_SDCFG1_COLSZ_GET( _reg ) \
( ( ( _reg ) & MMCTRL_SDCFG1_COLSZ_MASK ) >> \
MMCTRL_SDCFG1_COLSZ_SHIFT )
#define MMCTRL_SDCFG1_COLSZ_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_SDCFG1_COLSZ_MASK ) | \
( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \
MMCTRL_SDCFG1_COLSZ_MASK ) )
#define MMCTRL_SDCFG1_COLSZ( _val ) \
( ( ( _val ) << MMCTRL_SDCFG1_COLSZ_SHIFT ) & \
MMCTRL_SDCFG1_COLSZ_MASK )
#define MMCTRL_SDCFG1_COMMAND_SHIFT 18
#define MMCTRL_SDCFG1_COMMAND_MASK 0x1c0000U
#define MMCTRL_SDCFG1_COMMAND_GET( _reg ) \
( ( ( _reg ) & MMCTRL_SDCFG1_COMMAND_MASK ) >> \
MMCTRL_SDCFG1_COMMAND_SHIFT )
#define MMCTRL_SDCFG1_COMMAND_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_SDCFG1_COMMAND_MASK ) | \
( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \
MMCTRL_SDCFG1_COMMAND_MASK ) )
#define MMCTRL_SDCFG1_COMMAND( _val ) \
( ( ( _val ) << MMCTRL_SDCFG1_COMMAND_SHIFT ) & \
MMCTRL_SDCFG1_COMMAND_MASK )
#define MMCTRL_SDCFG1_MS 0x10000U
#define MMCTRL_SDCFG1_64 0x8000U
#define MMCTRL_SDCFG1_RFLOAD_SHIFT 0
#define MMCTRL_SDCFG1_RFLOAD_MASK 0x7fffU
#define MMCTRL_SDCFG1_RFLOAD_GET( _reg ) \
( ( ( _reg ) & MMCTRL_SDCFG1_RFLOAD_MASK ) >> \
MMCTRL_SDCFG1_RFLOAD_SHIFT )
#define MMCTRL_SDCFG1_RFLOAD_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_SDCFG1_RFLOAD_MASK ) | \
( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \
MMCTRL_SDCFG1_RFLOAD_MASK ) )
#define MMCTRL_SDCFG1_RFLOAD( _val ) \
( ( ( _val ) << MMCTRL_SDCFG1_RFLOAD_SHIFT ) & \
MMCTRL_SDCFG1_RFLOAD_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBMMCTRLSDCFG2 \
* SDRAM configuration register 2 (SDCFG2)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define MMCTRL_SDCFG2_CE 0x40000000U
#define MMCTRL_SDCFG2_EN2T 0x8000U
#define MMCTRL_SDCFG2_DCS 0x4000U
#define MMCTRL_SDCFG2_BPARK 0x2000U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBMMCTRLMUXCFG Mux configuration register (MUXCFG)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define MMCTRL_MUXCFG_ERRLOC_SHIFT 20
#define MMCTRL_MUXCFG_ERRLOC_MASK 0xfff00000U
#define MMCTRL_MUXCFG_ERRLOC_GET( _reg ) \
( ( ( _reg ) & MMCTRL_MUXCFG_ERRLOC_MASK ) >> \
MMCTRL_MUXCFG_ERRLOC_SHIFT )
#define MMCTRL_MUXCFG_ERRLOC_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_MUXCFG_ERRLOC_MASK ) | \
( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \
MMCTRL_MUXCFG_ERRLOC_MASK ) )
#define MMCTRL_MUXCFG_ERRLOC( _val ) \
( ( ( _val ) << MMCTRL_MUXCFG_ERRLOC_SHIFT ) & \
MMCTRL_MUXCFG_ERRLOC_MASK )
#define MMCTRL_MUXCFG_DDERR 0x80000U
#define MMCTRL_MUXCFG_DWIDTH_SHIFT 16
#define MMCTRL_MUXCFG_DWIDTH_MASK 0x70000U
#define MMCTRL_MUXCFG_DWIDTH_GET( _reg ) \
( ( ( _reg ) & MMCTRL_MUXCFG_DWIDTH_MASK ) >> \
MMCTRL_MUXCFG_DWIDTH_SHIFT )
#define MMCTRL_MUXCFG_DWIDTH_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_MUXCFG_DWIDTH_MASK ) | \
( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \
MMCTRL_MUXCFG_DWIDTH_MASK ) )
#define MMCTRL_MUXCFG_DWIDTH( _val ) \
( ( ( _val ) << MMCTRL_MUXCFG_DWIDTH_SHIFT ) & \
MMCTRL_MUXCFG_DWIDTH_MASK )
#define MMCTRL_MUXCFG_BEID_SHIFT 12
#define MMCTRL_MUXCFG_BEID_MASK 0xf000U
#define MMCTRL_MUXCFG_BEID_GET( _reg ) \
( ( ( _reg ) & MMCTRL_MUXCFG_BEID_MASK ) >> \
MMCTRL_MUXCFG_BEID_SHIFT )
#define MMCTRL_MUXCFG_BEID_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_MUXCFG_BEID_MASK ) | \
( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \
MMCTRL_MUXCFG_BEID_MASK ) )
#define MMCTRL_MUXCFG_BEID( _val ) \
( ( ( _val ) << MMCTRL_MUXCFG_BEID_SHIFT ) & \
MMCTRL_MUXCFG_BEID_MASK )
#define MMCTRL_MUXCFG_DATAMUX_SHIFT 5
#define MMCTRL_MUXCFG_DATAMUX_MASK 0xe0U
#define MMCTRL_MUXCFG_DATAMUX_GET( _reg ) \
( ( ( _reg ) & MMCTRL_MUXCFG_DATAMUX_MASK ) >> \
MMCTRL_MUXCFG_DATAMUX_SHIFT )
#define MMCTRL_MUXCFG_DATAMUX_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_MUXCFG_DATAMUX_MASK ) | \
( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \
MMCTRL_MUXCFG_DATAMUX_MASK ) )
#define MMCTRL_MUXCFG_DATAMUX( _val ) \
( ( ( _val ) << MMCTRL_MUXCFG_DATAMUX_SHIFT ) & \
MMCTRL_MUXCFG_DATAMUX_MASK )
#define MMCTRL_MUXCFG_CEN 0x10U
#define MMCTRL_MUXCFG_BAUPD 0x8U
#define MMCTRL_MUXCFG_BAEN 0x4U
#define MMCTRL_MUXCFG_CODE 0x2U
#define MMCTRL_MUXCFG_EDEN 0x1U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBMMCTRLFTDA FT diagnostic address register (FTDA)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define MMCTRL_FTDA_FTDA_SHIFT 2
#define MMCTRL_FTDA_FTDA_MASK 0xfffffffcU
#define MMCTRL_FTDA_FTDA_GET( _reg ) \
( ( ( _reg ) & MMCTRL_FTDA_FTDA_MASK ) >> \
MMCTRL_FTDA_FTDA_SHIFT )
#define MMCTRL_FTDA_FTDA_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_FTDA_FTDA_MASK ) | \
( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \
MMCTRL_FTDA_FTDA_MASK ) )
#define MMCTRL_FTDA_FTDA( _val ) \
( ( ( _val ) << MMCTRL_FTDA_FTDA_SHIFT ) & \
MMCTRL_FTDA_FTDA_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBMMCTRLFTDC FT diagnostic checkbits register (FTDC)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define MMCTRL_FTDC_CBD_SHIFT 24
#define MMCTRL_FTDC_CBD_MASK 0xff000000U
#define MMCTRL_FTDC_CBD_GET( _reg ) \
( ( ( _reg ) & MMCTRL_FTDC_CBD_MASK ) >> \
MMCTRL_FTDC_CBD_SHIFT )
#define MMCTRL_FTDC_CBD_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_FTDC_CBD_MASK ) | \
( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \
MMCTRL_FTDC_CBD_MASK ) )
#define MMCTRL_FTDC_CBD( _val ) \
( ( ( _val ) << MMCTRL_FTDC_CBD_SHIFT ) & \
MMCTRL_FTDC_CBD_MASK )
#define MMCTRL_FTDC_CBC_SHIFT 16
#define MMCTRL_FTDC_CBC_MASK 0xff0000U
#define MMCTRL_FTDC_CBC_GET( _reg ) \
( ( ( _reg ) & MMCTRL_FTDC_CBC_MASK ) >> \
MMCTRL_FTDC_CBC_SHIFT )
#define MMCTRL_FTDC_CBC_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_FTDC_CBC_MASK ) | \
( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \
MMCTRL_FTDC_CBC_MASK ) )
#define MMCTRL_FTDC_CBC( _val ) \
( ( ( _val ) << MMCTRL_FTDC_CBC_SHIFT ) & \
MMCTRL_FTDC_CBC_MASK )
#define MMCTRL_FTDC_CBB_SHIFT 8
#define MMCTRL_FTDC_CBB_MASK 0xff00U
#define MMCTRL_FTDC_CBB_GET( _reg ) \
( ( ( _reg ) & MMCTRL_FTDC_CBB_MASK ) >> \
MMCTRL_FTDC_CBB_SHIFT )
#define MMCTRL_FTDC_CBB_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_FTDC_CBB_MASK ) | \
( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \
MMCTRL_FTDC_CBB_MASK ) )
#define MMCTRL_FTDC_CBB( _val ) \
( ( ( _val ) << MMCTRL_FTDC_CBB_SHIFT ) & \
MMCTRL_FTDC_CBB_MASK )
#define MMCTRL_FTDC_CBA_SHIFT 0
#define MMCTRL_FTDC_CBA_MASK 0xffU
#define MMCTRL_FTDC_CBA_GET( _reg ) \
( ( ( _reg ) & MMCTRL_FTDC_CBA_MASK ) >> \
MMCTRL_FTDC_CBA_SHIFT )
#define MMCTRL_FTDC_CBA_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_FTDC_CBA_MASK ) | \
( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \
MMCTRL_FTDC_CBA_MASK ) )
#define MMCTRL_FTDC_CBA( _val ) \
( ( ( _val ) << MMCTRL_FTDC_CBA_SHIFT ) & \
MMCTRL_FTDC_CBA_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBMMCTRLFTDD FT diagnostic data register (FTDD)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define MMCTRL_FTDD_DATA_SHIFT 0
#define MMCTRL_FTDD_DATA_MASK 0xffffffffU
#define MMCTRL_FTDD_DATA_GET( _reg ) \
( ( ( _reg ) & MMCTRL_FTDD_DATA_MASK ) >> \
MMCTRL_FTDD_DATA_SHIFT )
#define MMCTRL_FTDD_DATA_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_FTDD_DATA_MASK ) | \
( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \
MMCTRL_FTDD_DATA_MASK ) )
#define MMCTRL_FTDD_DATA( _val ) \
( ( ( _val ) << MMCTRL_FTDD_DATA_SHIFT ) & \
MMCTRL_FTDD_DATA_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBMMCTRLFTBND FT boundary address register (FTBND)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define MMCTRL_FTBND_FTBND_31_3_SHIFT 3
#define MMCTRL_FTBND_FTBND_31_3_MASK 0xfffffff8U
#define MMCTRL_FTBND_FTBND_31_3_GET( _reg ) \
( ( ( _reg ) & MMCTRL_FTBND_FTBND_31_3_MASK ) >> \
MMCTRL_FTBND_FTBND_31_3_SHIFT )
#define MMCTRL_FTBND_FTBND_31_3_SET( _reg, _val ) \
( ( ( _reg ) & ~MMCTRL_FTBND_FTBND_31_3_MASK ) | \
( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \
MMCTRL_FTBND_FTBND_31_3_MASK ) )
#define MMCTRL_FTBND_FTBND_31_3( _val ) \
( ( ( _val ) << MMCTRL_FTBND_FTBND_31_3_SHIFT ) & \
MMCTRL_FTBND_FTBND_31_3_MASK )
/** @} */
/**
* @brief This structure defines the MMCTRL register block memory map.
*/
typedef struct mmctrl {
/**
* @brief See @ref RTEMSDeviceGRLIBMMCTRLSDCFG1.
*/
uint32_t sdcfg1;
/**
* @brief See @ref RTEMSDeviceGRLIBMMCTRLSDCFG2.
*/
uint32_t sdcfg2;
uint32_t reserved_8_20[ 6 ];
/**
* @brief See @ref RTEMSDeviceGRLIBMMCTRLMUXCFG.
*/
uint32_t muxcfg;
/**
* @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDA.
*/
uint32_t ftda;
/**
* @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDC.
*/
uint32_t ftdc;
/**
* @brief See @ref RTEMSDeviceGRLIBMMCTRLFTDD.
*/
uint32_t ftdd;
/**
* @brief See @ref RTEMSDeviceGRLIBMMCTRLFTBND.
*/
uint32_t ftbnd;
} mmctrl;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_MMCTRL_REGS_H */
bsps/include/grlib/spictrl-regs.h
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/* SPDX-License-Identifier: BSD-2-Clause */
/**
* @file
*
* @ingroup RTEMSDeviceGRLIBSPICTRL
*
* @brief This header file defines the SPICTRL register block interface.
*/
/*
* Copyright (C) 2021 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* This file is part of the RTEMS quality process and was automatically
* generated. If you find something that needs to be fixed or
* worded better please post a report or patch to an RTEMS mailing list
* or raise a bug report:
*
* https://www.rtems.org/bugs.html
*
* For information on updating and regenerating please refer to the How-To
* section in the Software Requirements Engineering chapter of the
* RTEMS Software Engineering manual. The manual is provided as a part of
* a release. For development sources please refer to the online
* documentation at:
*
* https://docs.rtems.org
*/
/* Generated from spec:/dev/grlib/if/spictrl-header */
#ifndef _GRLIB_SPICTRL_REGS_H
#define _GRLIB_SPICTRL_REGS_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Generated from spec:/dev/grlib/if/spictrl */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRL SPICTRL
*
* @ingroup RTEMSDeviceGRLIB
*
* @brief This group contains the SPICTRL interfaces.
*
* @{
*/
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLCAP Capability register (CAP)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_CAP_SSSZ_SHIFT 24
#define SPICTRL_CAP_SSSZ_MASK 0xff000000U
#define SPICTRL_CAP_SSSZ_GET( _reg ) \
( ( ( _reg ) & SPICTRL_CAP_SSSZ_MASK ) >> \
SPICTRL_CAP_SSSZ_SHIFT )
#define SPICTRL_CAP_SSSZ_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_CAP_SSSZ_MASK ) | \
( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \
SPICTRL_CAP_SSSZ_MASK ) )
#define SPICTRL_CAP_SSSZ( _val ) \
( ( ( _val ) << SPICTRL_CAP_SSSZ_SHIFT ) & \
SPICTRL_CAP_SSSZ_MASK )
#define SPICTRL_CAP_MAXWLEN_SHIFT 20
#define SPICTRL_CAP_MAXWLEN_MASK 0xf00000U
#define SPICTRL_CAP_MAXWLEN_GET( _reg ) \
( ( ( _reg ) & SPICTRL_CAP_MAXWLEN_MASK ) >> \
SPICTRL_CAP_MAXWLEN_SHIFT )
#define SPICTRL_CAP_MAXWLEN_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_CAP_MAXWLEN_MASK ) | \
( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \
SPICTRL_CAP_MAXWLEN_MASK ) )
#define SPICTRL_CAP_MAXWLEN( _val ) \
( ( ( _val ) << SPICTRL_CAP_MAXWLEN_SHIFT ) & \
SPICTRL_CAP_MAXWLEN_MASK )
#define SPICTRL_CAP_TWEN 0x80000U
#define SPICTRL_CAP_AMODE 0x40000U
#define SPICTRL_CAP_ASELA 0x20000U
#define SPICTRL_CAP_SSEN 0x10000U
#define SPICTRL_CAP_FDEPTH_SHIFT 8
#define SPICTRL_CAP_FDEPTH_MASK 0xff00U
#define SPICTRL_CAP_FDEPTH_GET( _reg ) \
( ( ( _reg ) & SPICTRL_CAP_FDEPTH_MASK ) >> \
SPICTRL_CAP_FDEPTH_SHIFT )
#define SPICTRL_CAP_FDEPTH_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_CAP_FDEPTH_MASK ) | \
( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \
SPICTRL_CAP_FDEPTH_MASK ) )
#define SPICTRL_CAP_FDEPTH( _val ) \
( ( ( _val ) << SPICTRL_CAP_FDEPTH_SHIFT ) & \
SPICTRL_CAP_FDEPTH_MASK )
#define SPICTRL_CAP_SR 0x80U
#define SPICTRL_CAP_FT_SHIFT 5
#define SPICTRL_CAP_FT_MASK 0x60U
#define SPICTRL_CAP_FT_GET( _reg ) \
( ( ( _reg ) & SPICTRL_CAP_FT_MASK ) >> \
SPICTRL_CAP_FT_SHIFT )
#define SPICTRL_CAP_FT_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_CAP_FT_MASK ) | \
( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \
SPICTRL_CAP_FT_MASK ) )
#define SPICTRL_CAP_FT( _val ) \
( ( ( _val ) << SPICTRL_CAP_FT_SHIFT ) & \
SPICTRL_CAP_FT_MASK )
#define SPICTRL_CAP_REV_SHIFT 0
#define SPICTRL_CAP_REV_MASK 0x1fU
#define SPICTRL_CAP_REV_GET( _reg ) \
( ( ( _reg ) & SPICTRL_CAP_REV_MASK ) >> \
SPICTRL_CAP_REV_SHIFT )
#define SPICTRL_CAP_REV_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_CAP_REV_MASK ) | \
( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \
SPICTRL_CAP_REV_MASK ) )
#define SPICTRL_CAP_REV( _val ) \
( ( ( _val ) << SPICTRL_CAP_REV_SHIFT ) & \
SPICTRL_CAP_REV_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLMODE Mode register (MODE)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_MODE_LOOP 0x40000000U
#define SPICTRL_MODE_CPOL 0x20000000U
#define SPICTRL_MODE_CPHA 0x10000000U
#define SPICTRL_MODE_DIV_16 0x8000000U
#define SPICTRL_MODE_REV 0x4000000U
#define SPICTRL_MODE_MX 0x2000000U
#define SPICTRL_MODE_EN 0x1000000U
#define SPICTRL_MODE_LEN_SHIFT 20
#define SPICTRL_MODE_LEN_MASK 0xf00000U
#define SPICTRL_MODE_LEN_GET( _reg ) \
( ( ( _reg ) & SPICTRL_MODE_LEN_MASK ) >> \
SPICTRL_MODE_LEN_SHIFT )
#define SPICTRL_MODE_LEN_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_MODE_LEN_MASK ) | \
( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \
SPICTRL_MODE_LEN_MASK ) )
#define SPICTRL_MODE_LEN( _val ) \
( ( ( _val ) << SPICTRL_MODE_LEN_SHIFT ) & \
SPICTRL_MODE_LEN_MASK )
#define SPICTRL_MODE_PM_SHIFT 16
#define SPICTRL_MODE_PM_MASK 0xf0000U
#define SPICTRL_MODE_PM_GET( _reg ) \
( ( ( _reg ) & SPICTRL_MODE_PM_MASK ) >> \
SPICTRL_MODE_PM_SHIFT )
#define SPICTRL_MODE_PM_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_MODE_PM_MASK ) | \
( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \
SPICTRL_MODE_PM_MASK ) )
#define SPICTRL_MODE_PM( _val ) \
( ( ( _val ) << SPICTRL_MODE_PM_SHIFT ) & \
SPICTRL_MODE_PM_MASK )
#define SPICTRL_MODE_TWEN 0x8000U
#define SPICTRL_MODE_ASEL 0x4000U
#define SPICTRL_MODE_FACT 0x2000U
#define SPICTRL_MODE_OD 0x1000U
#define SPICTRL_MODE_CG_SHIFT 7
#define SPICTRL_MODE_CG_MASK 0xf80U
#define SPICTRL_MODE_CG_GET( _reg ) \
( ( ( _reg ) & SPICTRL_MODE_CG_MASK ) >> \
SPICTRL_MODE_CG_SHIFT )
#define SPICTRL_MODE_CG_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_MODE_CG_MASK ) | \
( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \
SPICTRL_MODE_CG_MASK ) )
#define SPICTRL_MODE_CG( _val ) \
( ( ( _val ) << SPICTRL_MODE_CG_SHIFT ) & \
SPICTRL_MODE_CG_MASK )
#define SPICTRL_MODE_ASELDEL_SHIFT 5
#define SPICTRL_MODE_ASELDEL_MASK 0x60U
#define SPICTRL_MODE_ASELDEL_GET( _reg ) \
( ( ( _reg ) & SPICTRL_MODE_ASELDEL_MASK ) >> \
SPICTRL_MODE_ASELDEL_SHIFT )
#define SPICTRL_MODE_ASELDEL_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_MODE_ASELDEL_MASK ) | \
( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \
SPICTRL_MODE_ASELDEL_MASK ) )
#define SPICTRL_MODE_ASELDEL( _val ) \
( ( ( _val ) << SPICTRL_MODE_ASELDEL_SHIFT ) & \
SPICTRL_MODE_ASELDEL_MASK )
#define SPICTRL_MODE_TAC 0x10U
#define SPICTRL_MODE_TTO 0x8U
#define SPICTRL_MODE_IGSEL 0x4U
#define SPICTRL_MODE_CITE 0x2U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLEVENT Event register (EVENT)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_EVENT_TIP 0x80000000U
#define SPICTRL_EVENT_LT 0x4000U
#define SPICTRL_EVENT_OV 0x1000U
#define SPICTRL_EVENT_UN 0x800U
#define SPICTRL_EVENT_MME 0x400U
#define SPICTRL_EVENT_NE 0x200U
#define SPICTRL_EVENT_NF 0x100U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLMASK Mask register (MASK)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_MASK_TIPE 0x80000000U
#define SPICTRL_MASK_LTE 0x4000U
#define SPICTRL_MASK_OVE 0x1000U
#define SPICTRL_MASK_UNE 0x800U
#define SPICTRL_MASK_MMEE 0x400U
#define SPICTRL_MASK_NEEE 0x200U
#define SPICTRL_MASK_NFE 0x100U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLCMD Command register (CMD)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_CMD_LST 0x400000U
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLTX Transmit register (TX)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_TX_TDATA_SHIFT 0
#define SPICTRL_TX_TDATA_MASK 0xffffffffU
#define SPICTRL_TX_TDATA_GET( _reg ) \
( ( ( _reg ) & SPICTRL_TX_TDATA_MASK ) >> \
SPICTRL_TX_TDATA_SHIFT )
#define SPICTRL_TX_TDATA_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_TX_TDATA_MASK ) | \
( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \
SPICTRL_TX_TDATA_MASK ) )
#define SPICTRL_TX_TDATA( _val ) \
( ( ( _val ) << SPICTRL_TX_TDATA_SHIFT ) & \
SPICTRL_TX_TDATA_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLRX Receive register (RX)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_RX_RDATA_SHIFT 0
#define SPICTRL_RX_RDATA_MASK 0xffffffffU
#define SPICTRL_RX_RDATA_GET( _reg ) \
( ( ( _reg ) & SPICTRL_RX_RDATA_MASK ) >> \
SPICTRL_RX_RDATA_SHIFT )
#define SPICTRL_RX_RDATA_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_RX_RDATA_MASK ) | \
( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \
SPICTRL_RX_RDATA_MASK ) )
#define SPICTRL_RX_RDATA( _val ) \
( ( ( _val ) << SPICTRL_RX_RDATA_SHIFT ) & \
SPICTRL_RX_RDATA_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLSLVSEL Slave select register (SLVSEL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_SLVSEL_SLVSEL_SHIFT 0
#define SPICTRL_SLVSEL_SLVSEL_MASK 0x3U
#define SPICTRL_SLVSEL_SLVSEL_GET( _reg ) \
( ( ( _reg ) & SPICTRL_SLVSEL_SLVSEL_MASK ) >> \
SPICTRL_SLVSEL_SLVSEL_SHIFT )
#define SPICTRL_SLVSEL_SLVSEL_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_SLVSEL_SLVSEL_MASK ) | \
( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \
SPICTRL_SLVSEL_SLVSEL_MASK ) )
#define SPICTRL_SLVSEL_SLVSEL( _val ) \
( ( ( _val ) << SPICTRL_SLVSEL_SLVSEL_SHIFT ) & \
SPICTRL_SLVSEL_SLVSEL_MASK )
/** @} */
/**
* @defgroup RTEMSDeviceGRLIBSPICTRLASLVSEL \
* Automatic slave select register (ASLVSEL)
*
* @brief This group contains register bit definitions.
*
* @{
*/
#define SPICTRL_ASLVSEL_ASLVSEL_SHIFT 0
#define SPICTRL_ASLVSEL_ASLVSEL_MASK 0x3U
#define SPICTRL_ASLVSEL_ASLVSEL_GET( _reg ) \
( ( ( _reg ) & SPICTRL_ASLVSEL_ASLVSEL_MASK ) >> \
SPICTRL_ASLVSEL_ASLVSEL_SHIFT )
#define SPICTRL_ASLVSEL_ASLVSEL_SET( _reg, _val ) \
( ( ( _reg ) & ~SPICTRL_ASLVSEL_ASLVSEL_MASK ) | \
( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \
SPICTRL_ASLVSEL_ASLVSEL_MASK ) )
#define SPICTRL_ASLVSEL_ASLVSEL( _val ) \
( ( ( _val ) << SPICTRL_ASLVSEL_ASLVSEL_SHIFT ) & \
SPICTRL_ASLVSEL_ASLVSEL_MASK )
/** @} */
/**
* @brief This structure defines the SPICTRL register block memory map.
*/
typedef struct spictrl {
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLCAP.
*/
uint32_t cap;
uint32_t reserved_4_20[ 7 ];
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLMODE.
*/
uint32_t mode;
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLEVENT.
*/
uint32_t event;
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLMASK.
*/
uint32_t mask;
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLCMD.
*/
uint32_t cmd;
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLTX.
*/
uint32_t tx;
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLRX.
*/
uint32_t rx;
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLSLVSEL.
*/
uint32_t slvsel;
/**
* @brief See @ref RTEMSDeviceGRLIBSPICTRLASLVSEL.
*/
uint32_t aslvsel;
} spictrl;
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _GRLIB_SPICTRL_REGS_H */
bsps/include/grlib/spwpnp-regs.h
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bsps/include/grlib/spwrmap-regs.h
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bsps/include/grlib/spwtdp-regs.h
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