mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
synced 2026-09-28 01:29:34 +08:00
Move contents of libcsupport/include/zilog into libbsp/shared
Only a few BSPs use this and it should not have been in libcsupport.
This commit is contained in:
Joel Sherrill
@@ -26,13 +26,6 @@ include_rtems_HEADERS += include/rtems/malloc.h
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include_rtems_HEADERS += include/rtems/termiostypes.h
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include_rtems_HEADERS += include/rtems/gxx_wrappers.h
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## zilog
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include_rtems_zilogdir = $(includedir)/rtems/zilog
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include_rtems_zilog_HEADERS = include/zilog/z8036.h
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include_rtems_zilog_HEADERS += include/zilog/z8530.h
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## General stuff
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ERROR_C_FILES = src/error.c src/__assert.c
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@@ -1,106 +0,0 @@
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/**
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* @file
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*
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* @brief Zilog Z8036 Counter/Timer/IO Chip
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*
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* This include file defines information related to a Zilog Z8036
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* Counter/Timer/IO Chip. It is a memory mapped part.
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*
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* @note This file shares as much as possible with the include file
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* for the Z8536 via z8x36.h.
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*/
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/*
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* COPYRIGHT (c) 1989-2011.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef _RTEMS_ZILOG_Z8036_H
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#define _RTEMS_ZILOG_Z8036_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* macros */
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#define Z8036( ptr ) ((volatile struct z8036_map *)(ptr))
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#define Z8x36_STATE0 ( z8036 ) \
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{ /*char *garbage = *(Z8036(z8036))->???; */ }
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#define Z8x36_WRITE( z8036, reg, data ) \
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(Z8036(z8036))->reg = (data)
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#define Z8x36_READ( z8036, reg, data ) \
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(Z8036(z8036))->reg = (data)
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/* structures */
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struct z8036_map {
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/* MAIN CONTROL REGISTERS (0x00-0x07) */
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uint8_t MASTER_INTR; /* Master Interrupt Ctl Reg */
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uint8_t MASTER_CFG; /* Master Configuration Ctl Reg */
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uint8_t PORTA_VECTOR; /* Port A - Interrupt Vector */
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uint8_t PORTB_VECTOR; /* Port B - Interrupt Vector */
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uint8_t CNT_TMR_VECTOR; /* Counter/Timer Interrupt Vector */
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uint8_t PORTC_DATA_POLARITY; /* Port C - Data Path Polarity */
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uint8_t PORTC_DIRECTION; /* Port C - Data Direction */
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uint8_t PORTC_SPECIAL_IO_CTL; /* Port C - Special IO Control */
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/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */
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uint8_t PORTA_CMD_STATUS; /* Port A - Command Status Reg */
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uint8_t PORTB_CMD_STATUS; /* Port B - Command Status Reg */
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uint8_t CT1_CMD_STATUS; /* Ctr/Timer 1 - Command Status Reg */
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uint8_t CT2_CMD_STATUS; /* Ctr/Timer 2 - Command Status Reg */
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uint8_t CT3_CMD_STATUS; /* Ctr/Timer 3 - Command Status Reg */
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uint8_t PORTA_DATA; /* Port A - Data */
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uint8_t PORTB_DATA; /* Port B - Data */
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uint8_t PORTC_DATA; /* Port C - Data */
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/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */
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uint8_t CT1_CUR_CNT_MSB; /* Ctr/Timer 1 - Current Count (MSB) */
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uint8_t CT1_CUR_CNT_LSB; /* Ctr/Timer 1 - Current Count (LSB) */
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uint8_t CT2_CUR_CNT_MSB; /* Ctr/Timer 2 - Current Count (MSB) */
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uint8_t CT2_CUR_CNT_LSB; /* Ctr/Timer 2 - Current Count (LSB) */
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uint8_t CT3_CUR_CNT_MSB; /* Ctr/Timer 3 - Current Count (MSB) */
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uint8_t CT3_CUR_CNT_LSB; /* Ctr/Timer 3 - Current Count (LSB) */
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uint8_t CT1_TIME_CONST_MSB; /* Ctr/Timer 1 - Time Constant (MSB) */
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uint8_t CT1_TIME_CONST_LSB; /* Ctr/Timer 1 - Time Constant (LSB) */
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uint8_t CT2_TIME_CONST_MSB; /* Ctr/Timer 2 - Time Constant (MSB) */
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uint8_t CT2_TIME_CONST_LSB; /* Ctr/Timer 2 - Time Constant (LSB) */
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uint8_t CT3_TIME_CONST_MSB; /* Ctr/Timer 3 - Time Constant (MSB) */
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uint8_t CT3_TIME_CONST_LSB; /* Ctr/Timer 3 - Time Constant (LSB) */
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uint8_t CT1_MODE_SPEC; /* Ctr/Timer 1 - Mode Specification */
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uint8_t CT2_MODE_SPEC; /* Ctr/Timer 2 - Mode Specification */
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uint8_t CT3_MODE_SPEC; /* Ctr/Timer 3 - Mode Specification */
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uint8_t CURRENT_VECTOR; /* Current Vector */
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/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */
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uint8_t PORTA_MODE; /* Port A - Mode Specification */
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uint8_t PORTA_HANDSHAKE; /* Port A - Handshake Specification */
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uint8_t PORTA_DATA_POLARITY; /* Port A - Data Path Polarity */
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uint8_t PORTA_DIRECTION; /* Port A - Data Direction */
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uint8_t PORTA_SPECIAL_IO_CTL; /* Port A - Special IO Control */
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uint8_t PORTA_PATT_POLARITY; /* Port A - Pattern Polarity */
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uint8_t PORTA_PATT_TRANS; /* Port A - Pattern Transition */
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uint8_t PORTA_PATT_MASK; /* Port A - Pattern Mask */
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/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */
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uint8_t PORTB_MODE; /* Port B - Mode Specification */
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uint8_t PORTB_HANDSHAKE; /* Port B - Handshake Specification */
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uint8_t PORTB_DATA_POLARITY; /* Port B - Data Path Polarity */
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uint8_t PORTB_DIRECTION; /* Port B - Data Direction */
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uint8_t PORTB_SPECIAL_IO_CTL; /* Port B - Special IO Control */
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uint8_t PORTB_PATT_POLARITY; /* Port B - Pattern Polarity */
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uint8_t PORTB_PATT_TRANS; /* Port B - Pattern Transition */
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uint8_t PORTB_PATT_MASK; /* Port B - Pattern Mask */
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};
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -1,97 +0,0 @@
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/**
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* @file
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*
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* @brief Information Related to a Zilog Z8530 SCC Chip
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*
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* This include file defines information related to a Zilog Z8530
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* SCC Chip. It is a IO mapped part.
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*/
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/*
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* COPYRIGHT (c) 1989-2011.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef _RTEMS_ZILOG_Z8530_H
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#define _RTEMS_ZILOG_Z8530_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* macros */
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#define VOL8( ptr ) ((volatile uint8_t *)(ptr))
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#define Z8x30_STATE0 ( z8530 ) \
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{ char *garbage; \
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(garbage) = *(VOL8(z8530)) \
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}
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#define Z8x30_WRITE_CONTROL( z8530, reg, data ) \
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*(VOL8(z8530)) = (reg); \
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*(VOL8(z8530)) = (data)
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#define Z8x30_READ_CONTROL( z8530, reg, data ) \
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*(VOL8(z8530)) = (reg); \
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(data) = *(VOL8(z8530))
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#define Z8x30_WRITE_DATA( z8530, data ) \
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*(VOL8(z8530)) = (data);
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#define Z8x30_READ_DATA( z8530, data ) \
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(data) = *(VOL8(z8530));
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/* RR_0 Bit Definitions */
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#define RR_0_TX_BUFFER_EMPTY 0x04
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#define RR_0_RX_DATA_AVAILABLE 0x01
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/* read registers */
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#define RR_0 0x00
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#define RR_1 0x01
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#define RR_2 0x02
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#define RR_3 0x03
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#define RR_4 0x04
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#define RR_5 0x05
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#define RR_6 0x06
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#define RR_7 0x07
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#define RR_8 0x08
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#define RR_9 0x09
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#define RR_10 0x0A
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#define RR_11 0x0B
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#define RR_12 0x0C
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#define RR_13 0x0D
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#define RR_14 0x0E
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#define RR_15 0x0F
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/* write registers */
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#define WR_0 0x00
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#define WR_1 0x01
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#define WR_2 0x02
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#define WR_3 0x03
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#define WR_4 0x04
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#define WR_5 0x05
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#define WR_6 0x06
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#define WR_7 0x07
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#define WR_8 0x08
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#define WR_9 0x09
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#define WR_10 0x0A
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#define WR_11 0x0B
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#define WR_12 0x0C
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#define WR_13 0x0D
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#define WR_14 0x0E
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#define WR_15 0x0F
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#ifdef __cplusplus
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}
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#endif
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#endif
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@@ -90,16 +90,3 @@ $(PROJECT_INCLUDE)/rtems/gxx_wrappers.h: include/rtems/gxx_wrappers.h $(PROJECT_
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/gxx_wrappers.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/gxx_wrappers.h
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$(PROJECT_INCLUDE)/rtems/zilog/$(dirstamp):
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@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems/zilog
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@: > $(PROJECT_INCLUDE)/rtems/zilog/$(dirstamp)
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PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/zilog/$(dirstamp)
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$(PROJECT_INCLUDE)/rtems/zilog/z8036.h: include/zilog/z8036.h $(PROJECT_INCLUDE)/rtems/zilog/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/zilog/z8036.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/zilog/z8036.h
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$(PROJECT_INCLUDE)/rtems/zilog/z8530.h: include/zilog/z8530.h $(PROJECT_INCLUDE)/rtems/zilog/$(dirstamp)
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$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/zilog/z8530.h
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PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/zilog/z8530.h
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