From 14605b6d2b4381096199efb5c8b306ef258a90bd Mon Sep 17 00:00:00 2001 From: Mohamed Ayman Date: Mon, 16 Mar 2026 17:12:42 +0200 Subject: [PATCH] arm/stm32f4: fix SYSCFG register layout The SYSCFG register block misses two reserved registers between EXTICR4 and CMPCR. This causes CMPCR to be mapped at the wrong offset (0x18 instead of 0x20). Add the missing reserved fields to preserve the correct hardware register layout according to the STM32F4 reference manual. --- bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h index a2e37200e8..303d9d3e7f 100644 --- a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h +++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_syscfg.h @@ -101,6 +101,7 @@ struct stm32f4_syscfg_s { #define STM32F4_SYSCFG_EXTI15(val) BSP_FLD32(val, 12, 15) #define STM32F4_SYSCFG_EXTI15_GET(reg) BSP_FLD32GET(reg, 12, 15) #define STM32F4_SYSCFG_EXTI15_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) + uint32_t reserved[2]; uint32_t cmpcr; // Compensation cell control register #define STM32F4_SYSCFG_CMPCR_READY BSP_BIT32(8) #define STM32F4_SYSCFG_CMPCR_PD BSP_BIT32(0)