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* [DM/OFW][PCI] Fix address translation and PCI resource enumeration Rework OFW address translation to walk nested bus ranges in the correct direction and cache "ranges" and "dma-ranges" independently. Handle PCI three-cell addresses without treating the PCI flags cell as part of the address, and fix CPU-to-DMA and DMA-to-CPU translation across nested buses. Fix PCI BAR sizing and assignment by disabling address decoding during probing, preserving BAR attribute bits, and programming 64-bit BARs correctly. Add device enable and disable helpers so resources and bus mastering are enabled before driver probe. Program bridge memory and prefetch windows while scanning downstream buses, correctly link child buses into the PCI bus hierarchy, and avoid unnecessary PCIe link retraining when the link is already active. Allow host bridges without a device-tree pci-domain property by allocating unique domains dynamically, while preserving explicit domain assignments. Fix MSI and MSI-X IRQ setup, rollback, vector addressing, and affinity selection. Add the Raspberry Pi PCI vendor ID for RP1 and other downstream devices. Signed-off-by: GuEe-GUI <2991707448@qq.com> * style: format code with clang-format * style: format complete changed files with clang-format * drivers: pci: address OFW review feedback * style: format PCI and OFW changes for current master --------- Signed-off-by: GuEe-GUI <2991707448@qq.com>