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https://github.com/RT-Thread/rt-thread.git
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e5e0ad29bf
* Append WT attribute. * Change the API with pool size only. * Add address mask for DMA * Change DMA lock to mutex * Add pause callback for DMA engine driver * Add DMA Engine test * Add ARM PL330 DMA Engine driver
147 lines
3.5 KiB
C
147 lines
3.5 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2023-02-25 GuEe-GUI the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#if defined(RT_USING_DMA) && defined(RT_USING_FINSH)
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#include <stdlib.h>
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static void test_dma_callback(struct rt_dma_chan *chan, rt_size_t size)
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{
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rt_bool_t *done_ptr = chan->priv;
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*done_ptr = RT_TRUE;
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rt_hw_wmb();
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}
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static int dma_memcpy_test(int argc, char**argv)
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{
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rt_bool_t done;
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int dma_sz = 64;
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rt_ubase_t dma_addr;
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char *src_addr, *dst_addr;
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struct rt_device dev = {};
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struct rt_dma_slave_config config;
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struct rt_dma_slave_transfer transfer;
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struct rt_dma_chan *chn = rt_dma_chan_request(&dev, RT_NULL);
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if (rt_is_err_or_null(chn))
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{
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rt_kputs("Alloc DMA channel fail");
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return 0;
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}
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if (argc > 1)
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{
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dma_sz = atoi(argv[1]);
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}
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if (dma_sz % sizeof(rt_uint32_t))
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{
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dma_sz = RT_ALIGN_DOWN(dma_sz, sizeof(rt_uint32_t));
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rt_kprintf("DMA size align to %d\n", dma_sz);
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}
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if (!(src_addr = rt_dma_alloc_coherent(&dev, dma_sz, &dma_addr)))
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{
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rt_kprintf("Alloc DMA %s buffer(size = %d) fail\n", "SRC", dma_sz);
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goto _free_dma_chan;
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}
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config.src_addr = dma_addr;
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if (!(dst_addr = rt_dma_alloc_coherent(&dev, dma_sz, &dma_addr)))
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{
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rt_kprintf("Alloc DMA %s buffer(size = %d) fail\n", "DST", dma_sz);
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goto _free_src_addr;
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}
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config.dst_addr = dma_addr;
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config.direction = RT_DMA_MEM_TO_MEM;
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config.src_addr_width = sizeof(rt_uint32_t);
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config.src_maxburst = sizeof(rt_uint32_t);
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config.dst_addr_width = sizeof(rt_uint32_t);
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config.dst_maxburst = sizeof(rt_uint32_t);
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chn->callback = test_dma_callback;
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chn->priv = &done;
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if (rt_dma_chan_config(chn, &config))
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{
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rt_kprintf("DMA channel %s fail\n", "config");
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goto _free_dst_addr;
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}
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rt_memset(&transfer, 0, sizeof(transfer));
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transfer.src_addr = config.src_addr;
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transfer.dst_addr = config.dst_addr;
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transfer.buffer_len = dma_sz;
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if (rt_dma_prep_memcpy(chn, &transfer))
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{
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rt_kprintf("DMA channel %s fail\n", "prep");
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goto _free_dst_addr;
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}
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rt_memset(src_addr, 0xff, dma_sz);
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rt_memset(dst_addr, 0, dma_sz);
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rt_kprintf("%s %s:\n", "SRC", "start");
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for (int i = 0; i < dma_sz; ++i)
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{
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rt_kprintf("%02x ", src_addr[i]);
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}
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rt_kputs("\n");
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rt_kprintf("%s %s:\n", "DST", "start");
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for (int i = 0; i < dma_sz; ++i)
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{
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rt_kprintf("%02x ", dst_addr[i]);
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}
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rt_kputs("\n");
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done = RT_FALSE;
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if (rt_dma_chan_start(chn))
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{
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rt_kprintf("DMA channel %s fail\n", "start");
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goto _free_dst_addr;
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}
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while (!done)
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{
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rt_hw_cpu_relax();
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}
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rt_kprintf("%s %s:\n", "SRC", "end");
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for (int i = 0; i < dma_sz; ++i)
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{
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rt_kprintf("%02x ", src_addr[i]);
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}
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rt_kputs("\n");
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rt_kprintf("%s %s:\n", "DST", "end");
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for (int i = 0; i < dma_sz; ++i)
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{
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rt_kprintf("%02x ", dst_addr[i]);
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}
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rt_kputs("\n");
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_free_dst_addr:
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rt_dma_free_coherent(&dev, dma_sz, dst_addr, config.dst_addr);
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_free_src_addr:
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rt_dma_free_coherent(&dev, dma_sz, src_addr, config.src_addr);
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_free_dma_chan:
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rt_dma_chan_release(chn);
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return 0;
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}
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MSH_CMD_EXPORT(dma_memcpy_test, test dma memcpy e.g: dma_memcpy_test(64));
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#endif /* RT_USING_DMA && RT_USING_FINSH */
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