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1.Add the necessary function declarations for SMP enablement and implement the corresponding functionalities, including rt_hw_secondary_cpu_up, secondary_cpu_entry, rt_hw_local_irq_disable, rt_hw_local_irq_enable, rt_hw_secondary_cpu_idle_exec, rt_hw_spin_lock_init, rt_hw_spin_lock, rt_hw_spin_unlock, rt_hw_ipi_send, rt_hw_interrupt_set_priority, rt_hw_interrupt_get_priority, rt_hw_ipi_init, rt_hw_ipi_handler_install, and rt_hw_ipi_handler. 2.In the two functions (rt_hw_context_switch_to and rt_hw_context_switch) in context_gcc.S, add a call to rt_cpus_lock_status_restore to update the scheduler information. 3.If the MMU is enabled, use the .percpu section and record different hartids by configuring special page tables; if the MMU is not enabled, record them directly in the satp register. Additionally, add dynamic startup based on core configuration.The .percpu section is only used when both ARCH_MM_MMU and RT_USING_SMP are enabled. However, there is a certain amount of space waste since no macro guard is added for it in the link script currently. 4.The physical memory of QEMU started in CI is 128MB, so RT_HW_PAGE_END is modified from the original +256MB to +128MB. Modify the SConscript file under the common64 directory to include common/atomic_riscv.c in the compilation process. Signed-off-by: Mengchen Teng <teng_mengchen@163.com>
203 lines
4.6 KiB
Plaintext
203 lines
4.6 KiB
Plaintext
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/12/12 bernard The first version
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*/
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INCLUDE "link_stacksize.lds"
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INCLUDE "link_cpus.lds"
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OUTPUT_ARCH( "riscv" )
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/*
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* Memory layout:
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* 0x80000000 - 0x80200000: SBI
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* 0x80200000 - 0x81200000: Kernel
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*/
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MEMORY
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{
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SRAM : ORIGIN = 0xFFFFFFC000200000, LENGTH = 0x1000000 - 0x200000
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}
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ENTRY(_start)
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SECTIONS
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{
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/* . = 0x80200000 ; */
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. = 0xFFFFFFC000200000;
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/* __STACKSIZE__ = 4096; */
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__text_start = .;
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.start :
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{
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*(.start);
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} > SRAM
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. = ALIGN(8);
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.text :
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{
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*(.text) /* remaining code */
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*(.text.*) /* remaining code */
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*(.rodata) /* read-only data (constants) */
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*(.rodata*)
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*(.glue_7)
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*(.glue_7t)
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*(.gnu.linkonce.t*)
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/* section information for finsh shell */
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. = ALIGN(8);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(8);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(8);
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/* section information for initial. */
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. = ALIGN(8);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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. = ALIGN(8);
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__rt_utest_tc_tab_start = .;
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KEEP(*(UtestTcTab))
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__rt_utest_tc_tab_end = .;
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. = ALIGN(8);
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_etext = .;
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} > SRAM
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.eh_frame_hdr :
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{
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*(.eh_frame_hdr)
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*(.eh_frame_entry)
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} > SRAM
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.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > SRAM
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. = ALIGN(8);
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__text_end = .;
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__text_size = __text_end - __text_start;
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.data :
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{
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*(.data)
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*(.data.*)
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*(.data1)
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*(.data1.*)
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. = ALIGN(8);
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PROVIDE( __global_pointer$ = . + 0x800 );
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*(.sdata)
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*(.sdata.*)
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} > SRAM
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. = ALIGN(8);
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.ctors :
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{
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PROVIDE(__ctors_start__ = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE(__ctors_end__ = .);
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} > SRAM
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.dtors :
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{
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PROVIDE(__dtors_start__ = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE(__dtors_end__ = .);
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} > SRAM
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/* stack for dual core */
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.stack :
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{
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. = ALIGN(64);
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__stack_start__ = .;
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/* Dynamically allocate stack areas according to RT_CPUS_NR */
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. += (__STACKSIZE__ * RT_CPUS_NR);
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__stack_end__ = .;
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} > SRAM
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.sbss :
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{
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__bss_start = .;
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*(.sbss)
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*(.sbss.*)
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*(.dynsbss)
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*(.scommon)
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} > SRAM
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.percpu (NOLOAD) :
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{
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/* 2MB Align for MMU early map */
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. = ALIGN(0x200000);
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PROVIDE(__percpu_start = .);
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*(.percpu)
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/* 2MB Align for MMU early map */
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. = ALIGN(0x200000);
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PROVIDE(__percpu_end = .);
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/* Clone the area */
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. = __percpu_end + (__percpu_end - __percpu_start) * (RT_CPUS_NR - 1);
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PROVIDE(__percpu_real_end = .);
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} > SRAM
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.bss :
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{
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*(.bss)
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*(.bss.*)
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*(.dynbss)
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*(COMMON)
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__bss_end = .;
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} > SRAM
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_end = .;
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/* Stabs debugging sections. */
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections.
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* Symbols in the DWARF debugging sections are relative to the beginning
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* of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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}
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