From b9c660587680fc503ddec6717bd228630dd2d527 Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 15:04:19 +0800 Subject: [PATCH 1/5] add operating definitions of UART0 to UART5 --- bsp/beaglebone/drivers/serial.c | 231 ++++++++++++++++++++++++++++---- 1 file changed, 202 insertions(+), 29 deletions(-) diff --git a/bsp/beaglebone/drivers/serial.c b/bsp/beaglebone/drivers/serial.c index b29ffc9963..077f78ea3b 100644 --- a/bsp/beaglebone/drivers/serial.c +++ b/bsp/beaglebone/drivers/serial.c @@ -10,6 +10,7 @@ * Change Logs: * Date Author Notes * 2013-07-06 Bernard the first version + * 2014-01-11 RTsien add definitions of UART0 to UART5 */ #include @@ -162,14 +163,18 @@ static const struct rt_uart_ops am33xx_uart_ops = am33xx_getc, }; -/* UART1 device driver structure */ -struct serial_ringbuffer uart1_int_rx; -struct am33xx_uart uart1 = +/* UART device driver structure */ +struct serial_ringbuffer uart_int_rx[6]; +struct am33xx_uart uart[6] = { - UART0_BASE, - UART0_INT, + {UART0_BASE,UART0_INT}, + {UART1_BASE,UART1_INT}, + {UART2_BASE,UART2_INT}, + {UART3_BASE,UART3_INT}, + {UART4_BASE,UART4_INT}, + {UART5_BASE,UART5_INT} }; -struct rt_serial_device serial1; +struct rt_serial_device serial[6]; #define write_reg(base, value) *(int*)(base) = value #define read_reg(base) *(int*)(base) @@ -219,11 +224,46 @@ static void start_uart_clk(void) ; /* enable uart1 */ +#ifdef RT_USING_UART1 CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2; /* wait for uart1 clk */ while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; +#endif + +#ifdef RT_USING_UART2 + CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2; + + /* wait for uart2 clk */ + while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; +#endif + +#ifdef RT_USING_UART3 + CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2; + + /* wait for uart3 clk */ + while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; +#endif + +#ifdef RT_USING_UART4 + CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2; + + /* wait for uart4 clk */ + while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; +#endif + +#ifdef RT_USING_UART5 + CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2; + + /* wait for uart5 clk */ + while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) + ; +#endif + /* Waiting for the L4LS UART clock */ while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<10))) ; @@ -236,44 +276,177 @@ static void config_pinmux(void) ctlm_base = AM33XX_CTLM_REGS; /* make sure the pin mux is OK for uart */ +#ifdef RT_USING_UART1 REG32(ctlm_base + 0x800 + 0x180) = 0x20; REG32(ctlm_base + 0x800 + 0x184) = 0x00; +#endif + +#ifdef RT_USING_UART2 + REG32(ctlm_base + 0x800 + 0x150) = 0x20; + REG32(ctlm_base + 0x800 + 0x154) = 0x00; +#endif + +#ifdef RT_USING_UART3 + REG32(ctlm_base + 0x800 + 0x164) = 0x01; +#endif + +#ifdef RT_USING_UART4 + REG32(ctlm_base + 0x800 + 0x070) = 0x26; + REG32(ctlm_base + 0x800 + 0x074) = 0x06; +#endif + +#ifdef RT_USING_UART5 + REG32(ctlm_base + 0x800 + 0x0C4) = 0x24; + REG32(ctlm_base + 0x800 + 0x0C0) = 0x04; +#endif + + } int rt_hw_serial_init(void) { - struct am33xx_uart* uart; - struct serial_configure config; - - uart = &uart1; - uart->base = UART1_BASE; + struct serial_configure config[6]; poweron_per_domain(); start_uart_clk(); config_pinmux(); - config.baud_rate = BAUD_RATE_115200; - config.bit_order = BIT_ORDER_LSB; - config.data_bits = DATA_BITS_8; - config.parity = PARITY_NONE; - config.stop_bits = STOP_BITS_1; - config.invert = NRZ_NORMAL; - - serial1.ops = &am33xx_uart_ops; - serial1.int_rx = &uart1_int_rx; - serial1.config = config; +#ifdef RT_USING_UART0 + config[0].baud_rate = BAUD_RATE_115200; + config[0].bit_order = BIT_ORDER_LSB; + config[0].data_bits = DATA_BITS_8; + config[0].parity = PARITY_NONE; + config[0].stop_bits = STOP_BITS_1; + config[0].invert = NRZ_NORMAL; + serial[0].ops = &am33xx_uart_ops; + serial[0].int_rx = &uart_int_rx[0]; + serial[0].config = config[0]; /* enable RX interrupt */ - UART_IER_REG(uart->base) = 0x01; + UART_IER_REG(uart[0].base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart->irq, am33xx_uart_isr, &serial1, "uart1"); - rt_hw_interrupt_control(uart->irq, 0, 0); - rt_hw_interrupt_mask(uart->irq); - - /* register UART1 device */ - rt_hw_serial_register(&serial1, "uart1", + rt_hw_interrupt_install(uart[0].irq, am33xx_uart_isr, &serial[0], "uart0"); + rt_hw_interrupt_control(uart[0].irq, 0, 0); + rt_hw_interrupt_mask(uart[0].irq); + /* register UART0 device */ + rt_hw_serial_register(&serial[0], "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - uart); + &uart[0]); +#endif + +#ifdef RT_USING_UART1 + config[1].baud_rate = BAUD_RATE_115200; + config[1].bit_order = BIT_ORDER_LSB; + config[1].data_bits = DATA_BITS_8; + config[1].parity = PARITY_NONE; + config[1].stop_bits = STOP_BITS_1; + config[1].invert = NRZ_NORMAL; + + serial[1].ops = &am33xx_uart_ops; + serial[1].int_rx = &uart_int_rx[1]; + serial[1].config = config[1]; + /* enable RX interrupt */ + UART_IER_REG(uart[1].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[1].irq, am33xx_uart_isr, &serial[1], "uart1"); + rt_hw_interrupt_control(uart[1].irq, 0, 0); + rt_hw_interrupt_mask(uart[1].irq); + /* register UART0 device */ + rt_hw_serial_register(&serial[1], "uart1", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[1]); +#endif + +#ifdef RT_USING_UART2 + config[2].baud_rate = BAUD_RATE_115200; + config[2].bit_order = BIT_ORDER_LSB; + config[2].data_bits = DATA_BITS_8; + config[2].parity = PARITY_NONE; + config[2].stop_bits = STOP_BITS_1; + config[2].invert = NRZ_NORMAL; + + serial[2].ops = &am33xx_uart_ops; + serial[2].int_rx = &uart_int_rx[2]; + serial[2].config = config[2]; + /* enable RX interrupt */ + UART_IER_REG(uart[2].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[2].irq, am33xx_uart_isr, &serial[2], "uart2"); + rt_hw_interrupt_control(uart[2].irq, 0, 0); + rt_hw_interrupt_mask(uart[2].irq); + /* register UART2 device */ + rt_hw_serial_register(&serial[2], "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[2]); +#endif + +#ifdef RT_USING_UART3 + config[3].baud_rate = BAUD_RATE_115200; + config[3].bit_order = BIT_ORDER_LSB; + config[3].data_bits = DATA_BITS_8; + config[3].parity = PARITY_NONE; + config[3].stop_bits = STOP_BITS_1; + config[3].invert = NRZ_NORMAL; + serial[3].ops = &am33xx_uart_ops; + serial[3].int_rx = &uart_int_rx[3]; + serial[3].config = config[3]; + /* enable RX interrupt */ + UART_IER_REG(uart[3].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[3].irq, am33xx_uart_isr, &serial[3], "uart3"); + rt_hw_interrupt_control(uart[3].irq, 0, 0); + rt_hw_interrupt_mask(uart[3].irq); + /* register UART3 device */ + rt_hw_serial_register(&serial[3], "uart3", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[3]); +#endif + +#ifdef RT_USING_UART4 + config[4].baud_rate = BAUD_RATE_115200; + config[4].bit_order = BIT_ORDER_LSB; + config[4].data_bits = DATA_BITS_8; + config[4].parity = PARITY_NONE; + config[4].stop_bits = STOP_BITS_1; + config[4].invert = NRZ_NORMAL; + + serial[4].ops = &am33xx_uart_ops; + serial[4].int_rx = &uart_int_rx[4]; + serial[4].config = config[4]; + /* enable RX interrupt */ + UART_IER_REG(uart[4].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[4].irq, am33xx_uart_isr, &serial[4], "uart4"); + rt_hw_interrupt_control(uart[4].irq, 0, 0); + rt_hw_interrupt_mask(uart[4].irq); + /* register UART4 device */ + rt_hw_serial_register(&serial[4], "uart4", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[4]); +#endif + +#ifdef RT_USING_UART5 + config[5].baud_rate = BAUD_RATE_115200; + config[5].bit_order = BIT_ORDER_LSB; + config[5].data_bits = DATA_BITS_8; + config[5].parity = PARITY_NONE; + config[5].stop_bits = STOP_BITS_1; + config[5].invert = NRZ_NORMAL; + + serial[5].ops = &am33xx_uart_ops; + serial[5].int_rx = &uart_int_rx[5]; + serial[5].config = config[5]; + /* enable RX interrupt */ + UART_IER_REG(uart[5].base) = 0x01; + /* install ISR */ + rt_hw_interrupt_install(uart[5].irq, am33xx_uart_isr, &serial[5], "uart5"); + rt_hw_interrupt_control(uart[5].irq, 0, 0); + rt_hw_interrupt_mask(uart[5].irq); + /* register UART4 device */ + rt_hw_serial_register(&serial[5], "uart5", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart[5]); +#endif return 0; } From faf3515e6bcbd049ca2a0eaea339fc687de7f8e0 Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 15:05:51 +0800 Subject: [PATCH 2/5] support UART0 to UART5 straightly --- bsp/beaglebone/drivers/serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bsp/beaglebone/drivers/serial.c b/bsp/beaglebone/drivers/serial.c index 077f78ea3b..af93048ac9 100644 --- a/bsp/beaglebone/drivers/serial.c +++ b/bsp/beaglebone/drivers/serial.c @@ -10,7 +10,7 @@ * Change Logs: * Date Author Notes * 2013-07-06 Bernard the first version - * 2014-01-11 RTsien add definitions of UART0 to UART5 + * 2014-01-11 RTsien support UART0 to UART5 straightly */ #include From ef09b822b71795759a9bfbf5903e069b7b2668d6 Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 15:09:43 +0800 Subject: [PATCH 3/5] add RT_USING_UARTx and set console via uart0 --- bsp/beaglebone/rtconfig.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/bsp/beaglebone/rtconfig.h b/bsp/beaglebone/rtconfig.h index 27992c84cd..15326d74cf 100644 --- a/bsp/beaglebone/rtconfig.h +++ b/bsp/beaglebone/rtconfig.h @@ -73,6 +73,18 @@ #define RT_USING_DEVICE_IPC // #define RT_USING_SERIAL +// +#define RT_USING_UART0 +// +#define RT_USING_UART1 +// +#define RT_USING_UART2 +// +//#define RT_USING_UART3 +// +#define RT_USING_UART4 +// +#define RT_USING_UART5 // #define RT_UART_RX_BUFFER_SIZE 64 // @@ -84,7 +96,7 @@ // #define RT_CONSOLEBUF_SIZE 128 // -#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_CONSOLE_DEVICE_NAME "uart0" // // From 9382a7105f9e14bd74398983aa0c526b4e3dd0dd Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 15:14:36 +0800 Subject: [PATCH 4/5] add CM_PER_UARTx_CLKCTRL --- libcpu/arm/am335x/am33xx.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/libcpu/arm/am335x/am33xx.h b/libcpu/arm/am335x/am33xx.h index 86ed82750a..68ea4478d3 100644 --- a/libcpu/arm/am335x/am33xx.h +++ b/libcpu/arm/am335x/am33xx.h @@ -84,7 +84,11 @@ #define CM_PER(base) ((base) + 0) #define CM_PER_L4LS_CLKSTCTRL(base) (CM_PER(base) + 0) -#define CM_PER_UART1_CLKCTRL(base) (CM_PER(base) + 0x06C) +#define CM_PER_UART1_CLKCTRL(base) (CM_PER(base) + 0x6C) +#define CM_PER_UART2_CLKCTRL(base) (CM_PER(base) + 0x70) +#define CM_PER_UART3_CLKCTRL(base) (CM_PER(base) + 0x74) +#define CM_PER_UART4_CLKCTRL(base) (CM_PER(base) + 0x78) +#define CM_PER_UART5_CLKCTRL(base) (CM_PER(base) + 0x38) #define CM_WKUP(base) ((base) + 0x400) #define CM_DPLL(base) ((base) + 0x500) #define CM_MPU(base) ((base) + 0x600) @@ -171,6 +175,10 @@ /* PRCM registers */ #define CM_PER_L4LS_CLKSTCTRL_REG(base) REG32((base) + 0x0) #define CM_PER_UART1_CLKCTRL_REG(base) REG32(CM_PER_UART1_CLKCTRL(base)) +#define CM_PER_UART2_CLKCTRL_REG(base) REG32(CM_PER_UART2_CLKCTRL(base)) +#define CM_PER_UART3_CLKCTRL_REG(base) REG32(CM_PER_UART3_CLKCTRL(base)) +#define CM_PER_UART4_CLKCTRL_REG(base) REG32(CM_PER_UART4_CLKCTRL(base)) +#define CM_PER_UART5_CLKCTRL_REG(base) REG32(CM_PER_UART5_CLKCTRL(base)) #define CM_PER_TIMER7_CLKCTRL(base) REG32((base) + 0x7C) #define CM_PER_TIMER2_CLKCTRL(base) REG32((base) + 0x80) From d71b86c750d99ea2cb98b3e657f4f3baf104d3ea Mon Sep 17 00:00:00 2001 From: RTsien Date: Sat, 11 Jan 2014 22:03:51 +0800 Subject: [PATCH 5/5] friendly for uart count under 6 --- bsp/beaglebone/drivers/serial.c | 263 ++++++++++++++++++-------------- 1 file changed, 150 insertions(+), 113 deletions(-) diff --git a/bsp/beaglebone/drivers/serial.c b/bsp/beaglebone/drivers/serial.c index af93048ac9..d07621080b 100644 --- a/bsp/beaglebone/drivers/serial.c +++ b/bsp/beaglebone/drivers/serial.c @@ -39,7 +39,7 @@ static void am33xx_uart_isr(int irqno, void* param) iir = UART_IIR_REG(uart->base); - if ((iir & (0x02 << 1)) || (iir & (0x6 << 1))) + if ((iir & (0x02 << 1)) || (iir & (0x6 << 1))) { rt_hw_serial_isr(serial); } @@ -164,17 +164,65 @@ static const struct rt_uart_ops am33xx_uart_ops = }; /* UART device driver structure */ -struct serial_ringbuffer uart_int_rx[6]; -struct am33xx_uart uart[6] = +#ifdef RT_USING_UART0 +struct serial_ringbuffer uart0_int_rx; +struct am33xx_uart uart0 = { - {UART0_BASE,UART0_INT}, - {UART1_BASE,UART1_INT}, - {UART2_BASE,UART2_INT}, - {UART3_BASE,UART3_INT}, - {UART4_BASE,UART4_INT}, - {UART5_BASE,UART5_INT} + UART0_BASE, + UART0_INT, }; -struct rt_serial_device serial[6]; +struct rt_serial_device serial0; +#endif + +#ifdef RT_USING_UART1 +struct serial_ringbuffer uart1_int_rx; +struct am33xx_uart uart1 = +{ + UART1_BASE, + UART1_INT, +}; +struct rt_serial_device serial1; +#endif + +#ifdef RT_USING_UART2 +struct serial_ringbuffer uart2_int_rx; +struct am33xx_uart uart2 = +{ + UART2_BASE, + UART2_INT, +}; +struct rt_serial_device serial2; +#endif + +#ifdef RT_USING_UART3 +struct serial_ringbuffer uart3_int_rx; +struct am33xx_uart uart3 = +{ + UART3_BASE, + UART3_INT, +}; +struct rt_serial_device serial3; +#endif + +#ifdef RT_USING_UART4 +struct serial_ringbuffer uart4_int_rx; +struct am33xx_uart uart4 = +{ + UART4_BASE, + UART4_INT, +}; +struct rt_serial_device serial4; +#endif + +#ifdef RT_USING_UART5 +struct serial_ringbuffer uart5_int_rx; +struct am33xx_uart uart5 = +{ + UART5_BASE, + UART5_INT, +}; +struct rt_serial_device serial5; +#endif #define write_reg(base, value) *(int*)(base) = value #define read_reg(base) *(int*)(base) @@ -226,7 +274,6 @@ static void start_uart_clk(void) /* enable uart1 */ #ifdef RT_USING_UART1 CM_PER_UART1_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart1 clk */ while ((CM_PER_UART1_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -234,7 +281,6 @@ static void start_uart_clk(void) #ifdef RT_USING_UART2 CM_PER_UART2_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart2 clk */ while ((CM_PER_UART2_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -242,7 +288,6 @@ static void start_uart_clk(void) #ifdef RT_USING_UART3 CM_PER_UART3_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart3 clk */ while ((CM_PER_UART3_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -250,7 +295,6 @@ static void start_uart_clk(void) #ifdef RT_USING_UART4 CM_PER_UART4_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart4 clk */ while ((CM_PER_UART4_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -258,7 +302,6 @@ static void start_uart_clk(void) #ifdef RT_USING_UART5 CM_PER_UART5_CLKCTRL_REG(prcm_base) |= 0x2; - /* wait for uart5 clk */ while ((CM_PER_UART5_CLKCTRL_REG(prcm_base) & (0x3<<16)) != 0) ; @@ -299,156 +342,150 @@ static void config_pinmux(void) REG32(ctlm_base + 0x800 + 0x0C4) = 0x24; REG32(ctlm_base + 0x800 + 0x0C0) = 0x04; #endif - - } int rt_hw_serial_init(void) { - struct serial_configure config[6]; + struct serial_configure config; poweron_per_domain(); start_uart_clk(); config_pinmux(); #ifdef RT_USING_UART0 - config[0].baud_rate = BAUD_RATE_115200; - config[0].bit_order = BIT_ORDER_LSB; - config[0].data_bits = DATA_BITS_8; - config[0].parity = PARITY_NONE; - config[0].stop_bits = STOP_BITS_1; - config[0].invert = NRZ_NORMAL; - - serial[0].ops = &am33xx_uart_ops; - serial[0].int_rx = &uart_int_rx[0]; - serial[0].config = config[0]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + serial0.ops = &am33xx_uart_ops; + serial0.int_rx = &uart0_int_rx; + serial0.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[0].base) = 0x01; + UART_IER_REG(uart0.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[0].irq, am33xx_uart_isr, &serial[0], "uart0"); - rt_hw_interrupt_control(uart[0].irq, 0, 0); - rt_hw_interrupt_mask(uart[0].irq); + rt_hw_interrupt_install(uart0.irq, am33xx_uart_isr, &serial0, "uart0"); + rt_hw_interrupt_control(uart0.irq, 0, 0); + rt_hw_interrupt_mask(uart0.irq); /* register UART0 device */ - rt_hw_serial_register(&serial[0], "uart0", + rt_hw_serial_register(&serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[0]); + &uart0); #endif #ifdef RT_USING_UART1 - config[1].baud_rate = BAUD_RATE_115200; - config[1].bit_order = BIT_ORDER_LSB; - config[1].data_bits = DATA_BITS_8; - config[1].parity = PARITY_NONE; - config[1].stop_bits = STOP_BITS_1; - config[1].invert = NRZ_NORMAL; - - serial[1].ops = &am33xx_uart_ops; - serial[1].int_rx = &uart_int_rx[1]; - serial[1].config = config[1]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + serial1.ops = &am33xx_uart_ops; + serial1.int_rx = &uart1_int_rx; + serial1.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[1].base) = 0x01; + UART_IER_REG(uart1.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[1].irq, am33xx_uart_isr, &serial[1], "uart1"); - rt_hw_interrupt_control(uart[1].irq, 0, 0); - rt_hw_interrupt_mask(uart[1].irq); + rt_hw_interrupt_install(uart1.irq, am33xx_uart_isr, &serial1, "uart1"); + rt_hw_interrupt_control(uart1.irq, 0, 0); + rt_hw_interrupt_mask(uart1.irq); /* register UART0 device */ - rt_hw_serial_register(&serial[1], "uart1", + rt_hw_serial_register(&serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[1]); + &uart1); #endif #ifdef RT_USING_UART2 - config[2].baud_rate = BAUD_RATE_115200; - config[2].bit_order = BIT_ORDER_LSB; - config[2].data_bits = DATA_BITS_8; - config[2].parity = PARITY_NONE; - config[2].stop_bits = STOP_BITS_1; - config[2].invert = NRZ_NORMAL; - - serial[2].ops = &am33xx_uart_ops; - serial[2].int_rx = &uart_int_rx[2]; - serial[2].config = config[2]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + serial2.ops = &am33xx_uart_ops; + serial2.int_rx = &uart2_int_rx; + serial2.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[2].base) = 0x01; + UART_IER_REG(uart2.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[2].irq, am33xx_uart_isr, &serial[2], "uart2"); - rt_hw_interrupt_control(uart[2].irq, 0, 0); - rt_hw_interrupt_mask(uart[2].irq); + rt_hw_interrupt_install(uart2.irq, am33xx_uart_isr, &serial2, "uart2"); + rt_hw_interrupt_control(uart2.irq, 0, 0); + rt_hw_interrupt_mask(uart2.irq); /* register UART2 device */ - rt_hw_serial_register(&serial[2], "uart2", + rt_hw_serial_register(&serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[2]); + &uart2); #endif #ifdef RT_USING_UART3 - config[3].baud_rate = BAUD_RATE_115200; - config[3].bit_order = BIT_ORDER_LSB; - config[3].data_bits = DATA_BITS_8; - config[3].parity = PARITY_NONE; - config[3].stop_bits = STOP_BITS_1; - config[3].invert = NRZ_NORMAL; - serial[3].ops = &am33xx_uart_ops; - serial[3].int_rx = &uart_int_rx[3]; - serial[3].config = config[3]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + serial3.ops = &am33xx_uart_ops; + serial3.int_rx = &uart_3_int_rx; + serial3.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[3].base) = 0x01; + UART_IER_REG(uart3.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[3].irq, am33xx_uart_isr, &serial[3], "uart3"); - rt_hw_interrupt_control(uart[3].irq, 0, 0); - rt_hw_interrupt_mask(uart[3].irq); + rt_hw_interrupt_install(uart3.irq, am33xx_uart_isr, &serial3, "uart3"); + rt_hw_interrupt_control(uart3.irq, 0, 0); + rt_hw_interrupt_mask(uart3.irq); /* register UART3 device */ - rt_hw_serial_register(&serial[3], "uart3", + rt_hw_serial_register(&serial3, "uart3", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[3]); + &uart3); #endif #ifdef RT_USING_UART4 - config[4].baud_rate = BAUD_RATE_115200; - config[4].bit_order = BIT_ORDER_LSB; - config[4].data_bits = DATA_BITS_8; - config[4].parity = PARITY_NONE; - config[4].stop_bits = STOP_BITS_1; - config[4].invert = NRZ_NORMAL; - - serial[4].ops = &am33xx_uart_ops; - serial[4].int_rx = &uart_int_rx[4]; - serial[4].config = config[4]; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; + + serial4.ops = &am33xx_uart_ops; + serial4.int_rx = &uart4_int_rx; + serial4.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[4].base) = 0x01; + UART_IER_REG(uart4.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[4].irq, am33xx_uart_isr, &serial[4], "uart4"); - rt_hw_interrupt_control(uart[4].irq, 0, 0); - rt_hw_interrupt_mask(uart[4].irq); + rt_hw_interrupt_install(uart4.irq, am33xx_uart_isr, &serial4, "uart4"); + rt_hw_interrupt_control(uart4.irq, 0, 0); + rt_hw_interrupt_mask(uart4.irq); /* register UART4 device */ - rt_hw_serial_register(&serial[4], "uart4", + rt_hw_serial_register(&serial4, "uart4", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[4]); + &uart4); #endif #ifdef RT_USING_UART5 - config[5].baud_rate = BAUD_RATE_115200; - config[5].bit_order = BIT_ORDER_LSB; - config[5].data_bits = DATA_BITS_8; - config[5].parity = PARITY_NONE; - config[5].stop_bits = STOP_BITS_1; - config[5].invert = NRZ_NORMAL; + config.baud_rate = BAUD_RATE_115200; + config.bit_order = BIT_ORDER_LSB; + config.data_bits = DATA_BITS_8; + config.parity = PARITY_NONE; + config.stop_bits = STOP_BITS_1; + config.invert = NRZ_NORMAL; - serial[5].ops = &am33xx_uart_ops; - serial[5].int_rx = &uart_int_rx[5]; - serial[5].config = config[5]; + serial5.ops = &am33xx_uart_ops; + serial5.int_rx = &uart5_int_rx; + serial5.config = config; /* enable RX interrupt */ - UART_IER_REG(uart[5].base) = 0x01; + UART_IER_REG(uart5.base) = 0x01; /* install ISR */ - rt_hw_interrupt_install(uart[5].irq, am33xx_uart_isr, &serial[5], "uart5"); - rt_hw_interrupt_control(uart[5].irq, 0, 0); - rt_hw_interrupt_mask(uart[5].irq); + rt_hw_interrupt_install(uart5.irq, am33xx_uart_isr, &serial5, "uart5"); + rt_hw_interrupt_control(uart5.irq, 0, 0); + rt_hw_interrupt_mask(uart5.irq); /* register UART4 device */ - rt_hw_serial_register(&serial[5], "uart5", + rt_hw_serial_register(&serial5, "uart5", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart[5]); + &uart5); #endif return 0; } INIT_BOARD_EXPORT(rt_hw_serial_init); -