mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-23 20:57:20 +08:00
add raspi4 bsp
This commit is contained in:
bigmagic
@@ -9,6 +9,9 @@ cwd = GetCurrentDir()
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group = []
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list = os.listdir(cwd)
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# add common code files
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group = group + SConscript(os.path.join('common', 'SConscript'))
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# cpu porting code files
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if rtconfig.CPU != 'common':
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group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
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@@ -0,0 +1,24 @@
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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
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CPPPATH = [cwd]
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group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
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# build for sub-directory
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list = os.listdir(cwd)
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objs = []
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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group = group + objs
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Return('group')
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@@ -0,0 +1,24 @@
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# RT-Thread building script for component
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from building import *
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cwd = GetCurrentDir()
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CPPPATH = [cwd]
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gic400_group = Split('''
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gic_pl400.c
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''')
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gic500_group = Split('''
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gic_pl500.c
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''')
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src = ()
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if GetDepend('BSP_USING_GIC400'):
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src = gic400_group
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if GetDepend('BSP_USING_GIC500'):
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src = gic500_group
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group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH)
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Return('group')
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@@ -0,0 +1,368 @@
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/*
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* Copyright 2014, General Dynamics C4 Systems
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*
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* This software may be distributed and modified according to the terms of
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* the GNU General Public License version 2. Note that NO WARRANTY is provided.
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* See "LICENSE_GPLv2.txt" for details.
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*
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* @TAG(GD_GPL)
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*/
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#include "gic_pl400.h"
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#include "iomap.h"
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#define BIT(n) (1ul<<(n))
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#define MASK(n) (BIT(n)-1ul)
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/* Setters/getters helpers */
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#define IRQ_REG(IRQ) ((IRQ) / 32)
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#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
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#define IRQ_MASK MASK(10)
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#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < SPECIAL_IRQ_START)
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#define CPU(X) (1<<(X))
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#define TARGET_CPU_ALLINT(CPU) ( \
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( ((CPU)&0xff)<<0 ) |\
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( ((CPU)&0xff)<<8 ) |\
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( ((CPU)&0xff)<<16 ) |\
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( ((CPU)&0xff)<<24 ) \
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)
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#define TARGET_CPU0_ALLINT TARGET_CPU_ALLINT(CPU(0))
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#define IRQ_SET_ALL 0xffffffff;
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/* Special IRQ's */
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#define SPECIAL_IRQ_START 1020
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#define IRQ_NONE 1023
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/* Memory map for GIC distributor */
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struct gic_dist_map {
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uint32_t enable; /* 0x000 */
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uint32_t ic_type; /* 0x004 */
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uint32_t dist_ident; /* 0x008 */
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uint32_t res1[29]; /* [0x00C, 0x080) */
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uint32_t group[32]; /* [0x080, 0x100) */
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uint32_t enable_set[32]; /* [0x100, 0x180) */
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uint32_t enable_clr[32]; /* [0x180, 0x200) */
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uint32_t pending_set[32]; /* [0x200, 0x280) */
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uint32_t pending_clr[32]; /* [0x280, 0x300) */
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uint32_t active[32]; /* [0x300, 0x380) */
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uint32_t active_clr[32]; /* [0x380, 0x400) */
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uint32_t priority[255]; /* [0x400, 0x7FC) */
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uint32_t res2; /* 0x7FC */
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uint32_t targets[255]; /* [0x800, 0xBFC) */
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uint32_t res3; /* 0xBFC */
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uint32_t config[64]; /* [0xC00, 0xD00) */
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uint32_t ppi_status; /* [0xD00, 0xD04) */
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uint32_t spi_status[15]; /* [0xD04, 0xD40) */
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uint32_t res4[112]; /* [0xD40, 0xF00) */
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uint32_t sgi_control; /* 0xF00 */
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uint32_t res5[3]; /* [0xF04, 0xF10) */
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uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */
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uint32_t sgi_pending_set[4]; /* [0xF20, 0xF30) */
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uint32_t res10[40]; /* [0xF30, 0xFD0) */
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uint32_t periph_id[8]; /* [0xFD0, 0xFF0) */
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uint32_t component_id[4]; /* [0xFF0, 0xFFF] */
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};
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/* Memory map for GIC cpu interface */
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struct gic_cpu_iface_map {
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uint32_t icontrol; /* 0x000 */
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uint32_t pri_msk_c; /* 0x004 */
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uint32_t bp_c; /* 0x008 */
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uint32_t int_ack; /* 0x00C */
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uint32_t eoi; /* 0x010 */
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uint32_t run_priority; /* 0x014 */
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uint32_t hi_pend; /* 0x018 */
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uint32_t ns_alias_bp_c; /* 0x01C */
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uint32_t ns_alias_ack; /* 0x020 GIC_PL400 only */
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uint32_t ns_alias_eoi; /* 0x024 GIC_PL400 only */
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uint32_t ns_alias_hi_pend; /* 0x028 GIC_PL400 only */
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uint32_t res1[41]; /* [0x02C, 0x0D0) */
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uint32_t active_priority[4]; /* [0x0D0, 0xC0] GIC_PL400 only */
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uint32_t ns_active_priority[4]; /* [0xE0,0xF0] GIC_PL400 only */
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uint32_t res4[3]; /* [0xF0, 0xFC] */
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uint32_t cpu_if_ident; /* 0x0FC */
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uint32_t deactive; /* [0x1000] */
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};
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volatile struct gic_dist_map *gic_dist =
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(volatile struct gic_dist_map*)(GIC_PL400_DISTRIBUTOR_PPTR);
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volatile struct gic_cpu_iface_map *gic_cpuiface =
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(volatile struct gic_cpu_iface_map*)(GIC_PL400_CONTROLLER_PPTR);
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/* Helpers */
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static inline int
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is_irq_pending(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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return !!(gic_dist->pending_set[word] & BIT(bit));
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}
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static inline int
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is_irq_active(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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return !!(gic_dist->active[word] & BIT(bit));
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}
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static inline int
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is_irq_enabled(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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return !!(gic_dist->enable_set[word] & BIT(bit));
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}
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static inline int
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is_irq_edge_triggered(irq_t irq)
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{
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int word = irq / 16;
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int bit = ((irq & 0xf) * 2);
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return !!(gic_dist->config[word] & BIT(bit + 1));
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}
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static inline int
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is_irq_1_N(irq_t irq)
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{
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int word = irq / 16;
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int bit = ((irq & 0xf) * 2);
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return !!(gic_dist->config[word] & BIT(bit + 0));
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}
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static inline int
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is_irq_N_N(irq_t irq)
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{
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return !(is_irq_1_N(irq));
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}
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static inline void
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dist_pending_clr(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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/* Using |= here is detrimental to your health */
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gic_dist->pending_clr[word] = BIT(bit);
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}
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static inline void
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dist_pending_set(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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gic_dist->pending_set[word] = BIT(bit);
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}
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static inline void
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dist_enable_clr(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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/* Using |= here is detrimental to your health */
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gic_dist->enable_clr[word] = BIT(bit);
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}
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static inline void
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dist_enable_set(irq_t irq)
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{
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int word = irq / 32;
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int bit = irq & 0x1f;
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gic_dist->enable_set[word] = BIT(bit);
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}
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/**
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DONT_TRANSLATE
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*/
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static void dist_init(void)
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{
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int i;
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int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
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gic_dist->enable = 0;
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#if 0
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/* configure to group 0 for security */
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for (i = 0; i < nirqs; i += 32) {
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gic_dist->group[i / 32] = 0xffffffff;
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}
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#endif
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for (i = 0; i < nirqs; i += 32) {
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/* disable */
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gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
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/* clear pending */
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gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
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}
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/* reset interrupts priority */
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for (i = 32; i < nirqs; i += 4) {
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gic_dist->priority[i / 4] = 0x0;
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}
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/*
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* reset int target to cpu 0
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* (Should really query which processor we're running on and use that)
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*/
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for (i = 0; i < nirqs; i += 4) {
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gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
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}
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/* level-triggered, 1-N */
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for (i = 64; i < nirqs; i += 32) {
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gic_dist->config[i / 32] = 0;
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//gic_dist->config[i / 32] = 0x55555555;
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}
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/* enable the int controller */
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gic_dist->enable = 1;
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}
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/**
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DONT_TRANSLATE
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*/
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static void cpu_iface_init(void)
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{
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uint32_t i;
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/* For non-Exynos4, the registers are banked per CPU, need to clear them */
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gic_dist->enable_clr[0] = IRQ_SET_ALL;
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gic_dist->pending_clr[0] = IRQ_SET_ALL;
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gic_dist->priority[0] = 0x00;
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/* put everything in group 0 */
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/* clear any software generated interrupts */
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for (i = 0; i < 16; i += 4) {
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gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
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}
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gic_cpuiface->icontrol = 0;
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gic_cpuiface->pri_msk_c = 0x000000f0;
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gic_cpuiface->bp_c = 0x00000003;
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while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != IRQ_NONE) {
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gic_cpuiface->eoi = i;
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}
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gic_cpuiface->icontrol = 0x1;
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}
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/**
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DONT_TRANSLATE
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*/
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void initIRQController(void)
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{
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dist_init();
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cpu_iface_init();
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}
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||||
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/*
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* The only sane way to get an GIC IRQ number that can be properly
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||||
* ACKED later is through the int_ack register. Unfortunately, reading
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* this register changes the interrupt state to pending so future
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* reads will not return the same value For this reason, we have a
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* global variable to store the IRQ number.
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*/
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static uint32_t active_irq = IRQ_NONE;
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/**
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DONT_TRANSLATE
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*/
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interrupt_t
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getActiveIRQ(void)
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{
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||||
uint32_t irq;
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if (!IS_IRQ_VALID(active_irq)) {
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active_irq = gic_cpuiface->int_ack;
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}
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if (IS_IRQ_VALID(active_irq)) {
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irq = active_irq & IRQ_MASK;
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} else {
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irq = 1023;
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||||
}
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||||
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||||
return irq;
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||||
}
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||||
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/*
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* GIC has 4 states: pending->active(+pending)->inactive
|
||||
* seL4 expects two states: active->inactive.
|
||||
* We ignore the active state in GIC to conform
|
||||
*/
|
||||
/**
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||||
DONT_TRANSLATE
|
||||
*/
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||||
bool_t
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||||
isIRQPending(void)
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||||
{
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||||
return IS_IRQ_VALID(gic_cpuiface->hi_pend);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
DONT_TRANSLATE
|
||||
*/
|
||||
void
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||||
maskInterrupt(bool_t disable, interrupt_t irq)
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||||
{
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||||
if (disable) {
|
||||
dist_enable_clr(irq);
|
||||
} else {
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||||
dist_enable_set(irq);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
DONT_TRANSLATE
|
||||
*/
|
||||
void
|
||||
ackInterrupt(irq_t irq)
|
||||
{
|
||||
if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq)) {
|
||||
return;
|
||||
}
|
||||
if (is_irq_edge_triggered(irq)) {
|
||||
dist_pending_clr(irq);
|
||||
}
|
||||
gic_cpuiface->eoi = active_irq;
|
||||
active_irq = IRQ_NONE;
|
||||
}
|
||||
|
||||
void
|
||||
handleSpuriousIRQ(void)
|
||||
{
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_mask(int vector)
|
||||
{
|
||||
maskInterrupt(1, vector);
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_umask(int vector)
|
||||
{
|
||||
maskInterrupt(0, vector);
|
||||
}
|
||||
|
||||
int rt_hw_interrupt_get_irq(void)
|
||||
{
|
||||
return getActiveIRQ();
|
||||
}
|
||||
|
||||
void rt_hw_interrupt_ack(int fiq_irq)
|
||||
{
|
||||
return ackInterrupt(fiq_irq);
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
|
||||
#ifndef __ARCH_MACHINE_GIC_PL400_H
|
||||
#define __ARCH_MACHINE_GIC_PL400_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef uint16_t interrupt_t;
|
||||
typedef uint16_t irq_t;
|
||||
typedef uint64_t bool_t;
|
||||
|
||||
/** MODIFIES: [*] */
|
||||
interrupt_t getActiveIRQ(void);
|
||||
/** MODIFIES: [*] */
|
||||
interrupt_t getPendingIRQ(void);
|
||||
/** MODIFIES: [*] */
|
||||
bool_t isIRQPending(void);
|
||||
/** MODIFIES: [*] */
|
||||
void maskInterrupt(bool_t disable, interrupt_t irq);
|
||||
/** MODIFIES: [*] */
|
||||
void ackInterrupt(irq_t irq);
|
||||
/** MODIFIES: [*] */
|
||||
static inline void setInterruptMode(irq_t irq, bool_t levelTrigger, bool_t polarityLow) { }
|
||||
|
||||
/** MODIFIES: [*] */
|
||||
void initIRQController(void);
|
||||
|
||||
void handleSpuriousIRQ(void);
|
||||
|
||||
void rt_hw_interrupt_umask(int vector);
|
||||
|
||||
int rt_hw_interrupt_get_irq(void);
|
||||
|
||||
void rt_hw_interrupt_ack(int fiq_irq);
|
||||
#endif /* !__ARCH_MACHINE_GIC400_H */
|
||||
|
||||
@@ -1,16 +1,13 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
Import('rtconfig')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp')
|
||||
asm_src = Split('''
|
||||
context_gcc.S
|
||||
vector_gcc.S
|
||||
entry_point.S
|
||||
cpu_gcc.S
|
||||
cache.S
|
||||
''')
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('cpu', src + asm_src, depend = [''], CPPPATH = CPPPATH)
|
||||
group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
||||
@@ -1,11 +1,11 @@
|
||||
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef __INTERRUPT_H__
|
||||
@@ -19,8 +19,6 @@
|
||||
#define INT_IRQ 0x00
|
||||
#define INT_FIQ 0x01
|
||||
|
||||
//void rt_hw_vector_init(void);
|
||||
|
||||
void rt_hw_interrupt_init(void);
|
||||
void rt_hw_interrupt_mask(int vector);
|
||||
void rt_hw_interrupt_umask(int vector);
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
# RT-Thread building script for component
|
||||
|
||||
from building import *
|
||||
|
||||
Import('rtconfig')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,111 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Date Author Notes
|
||||
* 2020-01-15 bigmagic the first version
|
||||
*/
|
||||
|
||||
.section ".text.entrypoint"
|
||||
|
||||
.set EL1_stack, __el1_stack
|
||||
|
||||
.global _start
|
||||
|
||||
// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
|
||||
// loads 'kernel8.img' file in.
|
||||
_start:
|
||||
// read cpu id, stop slave cores
|
||||
mrs x1, mpidr_el1 // MPIDR_EL1: Multi-Processor Affinity Register
|
||||
and x1, x1, #3
|
||||
cbz x1, .L__cpu_0 // .L prefix is the local label in ELF
|
||||
|
||||
// cpu id > 0, stop
|
||||
// cpu id == 0 will also goto here after returned from entry() if possible
|
||||
.L__current_cpu_idle:
|
||||
wfe
|
||||
b .L__current_cpu_idle
|
||||
|
||||
.L__cpu_0: // cpu id == 0
|
||||
|
||||
// set stack before our code
|
||||
|
||||
/* Define stack pointer for current exception level */
|
||||
// ldr x2, =EL1_stack
|
||||
// mov sp, x2
|
||||
|
||||
ldr x1, =_start
|
||||
|
||||
// set up EL1
|
||||
mrs x0, CurrentEL // CurrentEL Register. bit 2, 3. Others reserved
|
||||
and x0, x0, #12 // clear reserved bits
|
||||
|
||||
// running at EL3?
|
||||
cmp x0, #12 // 1100b. So, EL3
|
||||
bne .L__not_in_el3 // 11? !EL3 -> 5:
|
||||
|
||||
// should never be executed, just for completeness. (EL3)
|
||||
mov x2, #0x5b1
|
||||
msr scr_el3, x2 // SCR_ELn Secure Configuration Register
|
||||
mov x2, #0x3c9
|
||||
msr spsr_el3, x2 // SPSR_ELn. Saved Program Status Register. 1111001001
|
||||
adr x2, .L__not_in_el3
|
||||
msr elr_el3, x2
|
||||
eret // Exception Return: from EL3, continue from .L__not_in_el3
|
||||
|
||||
// running at EL2 or EL1
|
||||
.L__not_in_el3:
|
||||
cmp x0, #4 // 0x04 0100 EL1
|
||||
beq .L__in_el1 // EL1 -> 5:
|
||||
|
||||
// in EL2
|
||||
msr sp_el1, x1 // Set sp of EL1 to _start
|
||||
|
||||
// enable CNTP for EL1
|
||||
mrs x0, cnthctl_el2 // Counter-timer Hypervisor Control register
|
||||
orr x0, x0, #3
|
||||
msr cnthctl_el2, x0
|
||||
msr cntvoff_el2, xzr
|
||||
|
||||
// enable AArch64 in EL1
|
||||
mov x0, #(1 << 31) // AArch64
|
||||
orr x0, x0, #(1 << 1) // SWIO hardwired on Pi3
|
||||
msr hcr_el2, x0
|
||||
mrs x0, hcr_el2
|
||||
|
||||
// change execution level to EL1
|
||||
mov x2, #0x3c4
|
||||
msr spsr_el2, x2 // 1111000100
|
||||
adr x2, .L__in_el1
|
||||
msr elr_el2, x2
|
||||
eret // exception return. from EL2. continue from .L__in_el1
|
||||
|
||||
.L__in_el1:
|
||||
mov sp, x1 // in EL1. Set sp to _start
|
||||
|
||||
// Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
|
||||
mov x1, #0x00300000 // Don't trap any SIMD/FP instructions in both EL0 and EL1
|
||||
msr cpacr_el1, x1
|
||||
|
||||
mrs x1, sctlr_el1
|
||||
orr x1, x1, #(1 << 12)
|
||||
bic x1, x1, #(3 << 3)
|
||||
bic x1, x1, #(1 << 1)
|
||||
msr sctlr_el1, x1
|
||||
|
||||
// clear bss
|
||||
ldr x1, =__bss_start
|
||||
ldr w2, =__bss_size
|
||||
|
||||
.L__clean_bss_loop:
|
||||
cbz w2, .L__jump_to_entry
|
||||
str xzr, [x1], #8
|
||||
sub w2, w2, #1
|
||||
cbnz w2, .L__clean_bss_loop
|
||||
|
||||
// jump to C code, should not return
|
||||
.L__jump_to_entry:
|
||||
bl entry
|
||||
// for failsafe, halt this core too
|
||||
b .L__current_cpu_idle
|
||||
@@ -0,0 +1,73 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include <gic_pl400.h>
|
||||
#include <board.h>
|
||||
#include <armv8.h>
|
||||
|
||||
#define MAX_HANDLERS 256
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
#define rt_interrupt_nest rt_cpu_self()->irq_nest
|
||||
#else
|
||||
extern volatile rt_uint8_t rt_interrupt_nest;
|
||||
#endif
|
||||
|
||||
extern int system_vectors;
|
||||
|
||||
/* exception and interrupt handler table */
|
||||
struct rt_irq_desc isr_table[MAX_HANDLERS];
|
||||
|
||||
rt_ubase_t rt_interrupt_from_thread;
|
||||
rt_ubase_t rt_interrupt_to_thread;
|
||||
rt_ubase_t rt_thread_switch_interrupt_flag;
|
||||
|
||||
void rt_hw_vector_init(void)
|
||||
{
|
||||
rt_hw_set_current_vbar((rt_ubase_t)&system_vectors); // cpu_gcc.S
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initialize hardware interrupt
|
||||
*/
|
||||
void rt_hw_interrupt_init(void)
|
||||
{
|
||||
initIRQController();
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will install a interrupt service routine to a interrupt.
|
||||
* @param vector the interrupt number
|
||||
* @param new_handler the interrupt service routine to be installed
|
||||
* @param old_handler the old interrupt service routine
|
||||
*/
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name)
|
||||
{
|
||||
rt_isr_handler_t old_handler = RT_NULL;
|
||||
|
||||
if (vector < MAX_HANDLERS)
|
||||
{
|
||||
old_handler = isr_table[vector].handler;
|
||||
|
||||
if (handler != RT_NULL)
|
||||
{
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
|
||||
#endif /* RT_USING_INTERRUPT_INFO */
|
||||
isr_table[vector].handler = handler;
|
||||
isr_table[vector].param = param;
|
||||
}
|
||||
}
|
||||
|
||||
return old_handler;
|
||||
}
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2020-04-16 bigmagic first version
|
||||
*/
|
||||
|
||||
#ifndef __INTERRUPT_H__
|
||||
#define __INTERRUPT_H__
|
||||
|
||||
#include <rthw.h>
|
||||
#include <board.h>
|
||||
|
||||
#define INT_IRQ 0x00
|
||||
#define INT_FIQ 0x01
|
||||
|
||||
void rt_hw_interrupt_init(void);
|
||||
void rt_hw_interrupt_mask(int vector);
|
||||
void rt_hw_interrupt_umask(int vector);
|
||||
|
||||
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
|
||||
void *param, const char *name);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2011-09-23 Bernard the first version
|
||||
* 2011-10-05 Bernard add thumb mode
|
||||
*/
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
#include <armv8.h>
|
||||
|
||||
#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
|
||||
#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
|
||||
#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
|
||||
|
||||
/**
|
||||
* This function will initialize thread stack
|
||||
*
|
||||
* @param tentry the entry of thread
|
||||
* @param parameter the parameter of entry
|
||||
* @param stack_addr the beginning stack address
|
||||
* @param texit the function will be called when thread exit
|
||||
*
|
||||
* @return stack address
|
||||
*/
|
||||
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
|
||||
rt_uint8_t *stack_addr, void *texit)
|
||||
{
|
||||
rt_ubase_t *stk;
|
||||
rt_ubase_t current_el;
|
||||
|
||||
stk = (rt_ubase_t*)stack_addr;
|
||||
|
||||
*(--stk) = ( rt_ubase_t ) 11; /* X1 */
|
||||
*(--stk) = ( rt_ubase_t ) parameter; /* X0 */
|
||||
*(--stk) = ( rt_ubase_t ) 33; /* X3 */
|
||||
*(--stk) = ( rt_ubase_t ) 22; /* X2 */
|
||||
*(--stk) = ( rt_ubase_t ) 55; /* X5 */
|
||||
*(--stk) = ( rt_ubase_t ) 44; /* X4 */
|
||||
*(--stk) = ( rt_ubase_t ) 77; /* X7 */
|
||||
*(--stk) = ( rt_ubase_t ) 66; /* X6 */
|
||||
*(--stk) = ( rt_ubase_t ) 99; /* X9 */
|
||||
*(--stk) = ( rt_ubase_t ) 88; /* X8 */
|
||||
*(--stk) = ( rt_ubase_t ) 11; /* X11 */
|
||||
*(--stk) = ( rt_ubase_t ) 10; /* X10 */
|
||||
*(--stk) = ( rt_ubase_t ) 13; /* X13 */
|
||||
*(--stk) = ( rt_ubase_t ) 12; /* X12 */
|
||||
*(--stk) = ( rt_ubase_t ) 15; /* X15 */
|
||||
*(--stk) = ( rt_ubase_t ) 14; /* X14 */
|
||||
*(--stk) = ( rt_ubase_t ) 17; /* X17 */
|
||||
*(--stk) = ( rt_ubase_t ) 16; /* X16 */
|
||||
*(--stk) = ( rt_ubase_t ) 19; /* X19 */
|
||||
*(--stk) = ( rt_ubase_t ) 18; /* X18 */
|
||||
*(--stk) = ( rt_ubase_t ) 21; /* X21 */
|
||||
*(--stk) = ( rt_ubase_t ) 20; /* X20 */
|
||||
*(--stk) = ( rt_ubase_t ) 23; /* X23 */
|
||||
*(--stk) = ( rt_ubase_t ) 22; /* X22 */
|
||||
*(--stk) = ( rt_ubase_t ) 25; /* X25 */
|
||||
*(--stk) = ( rt_ubase_t ) 24; /* X24 */
|
||||
*(--stk) = ( rt_ubase_t ) 27; /* X27 */
|
||||
*(--stk) = ( rt_ubase_t ) 26; /* X26 */
|
||||
*(--stk) = ( rt_ubase_t ) 29; /* X29 */
|
||||
*(--stk) = ( rt_ubase_t ) 28; /* X28 */
|
||||
*(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */
|
||||
*(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */
|
||||
|
||||
current_el = rt_hw_get_current_el();
|
||||
|
||||
if(current_el == 3)
|
||||
{
|
||||
*(--stk) = INITIAL_SPSR_EL3;
|
||||
}
|
||||
else if(current_el == 2)
|
||||
{
|
||||
*(--stk) = INITIAL_SPSR_EL2;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(--stk) = INITIAL_SPSR_EL1;
|
||||
}
|
||||
|
||||
*(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */
|
||||
|
||||
/* return task's current stack address */
|
||||
return (rt_uint8_t *)stk;
|
||||
}
|
||||
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Date Author Notes
|
||||
* 2018-10-06 ZhaoXiaowei the first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#include "interrupt.h"
|
||||
#include "armv8.h"
|
||||
|
||||
extern struct rt_thread *rt_current_thread;
|
||||
#ifdef RT_USING_FINSH
|
||||
extern long list_thread(void);
|
||||
#endif
|
||||
|
||||
/**
|
||||
* this function will show registers of CPU
|
||||
*
|
||||
* @param regs the registers point
|
||||
*/
|
||||
void rt_hw_show_register(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("Execption:\n");
|
||||
rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
|
||||
rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
|
||||
rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
|
||||
rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
|
||||
rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
|
||||
rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
|
||||
rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
|
||||
rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
|
||||
rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
|
||||
rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
|
||||
}
|
||||
|
||||
/**
|
||||
* When comes across an instruction which it cannot handle,
|
||||
* it takes the undefined instruction trap.
|
||||
*
|
||||
* @param regs system registers
|
||||
*
|
||||
* @note never invoke this function in application
|
||||
*/
|
||||
void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
|
||||
{
|
||||
rt_kprintf("error exception:\n");
|
||||
rt_hw_show_register(regs);
|
||||
#ifdef RT_USING_FINSH
|
||||
list_thread();
|
||||
#endif
|
||||
rt_hw_cpu_shutdown();
|
||||
}
|
||||
|
||||
#define GIC_ACK_INTID_MASK 0x000003ff
|
||||
|
||||
int rt_hw_interrupt_get_irq(void);
|
||||
void rt_hw_interrupt_ack(int fiq_irq);
|
||||
|
||||
void rt_hw_trap_irq(void)
|
||||
{
|
||||
void *param;
|
||||
int ir;
|
||||
rt_isr_handler_t isr_func;
|
||||
extern struct rt_irq_desc isr_table[];
|
||||
|
||||
ir = rt_hw_interrupt_get_irq();
|
||||
if (ir == 1023)
|
||||
{
|
||||
/* Spurious interrupt */
|
||||
return;
|
||||
}
|
||||
|
||||
/* get interrupt service routine */
|
||||
isr_func = isr_table[ir].handler;
|
||||
#ifdef RT_USING_INTERRUPT_INFO
|
||||
isr_table[ir].counter++;
|
||||
#endif
|
||||
if (isr_func)
|
||||
{
|
||||
/* Interrupt for myself. */
|
||||
param = isr_table[ir].param;
|
||||
/* turn to interrupt service routine */
|
||||
isr_func(ir, param);
|
||||
}
|
||||
|
||||
/* end of interrupt */
|
||||
rt_hw_interrupt_ack(ir);
|
||||
|
||||
}
|
||||
|
||||
void rt_hw_trap_fiq(void)
|
||||
{
|
||||
}
|
||||
Reference in New Issue
Block a user