mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-23 04:04:15 +08:00
[libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568 (#5722)
* [libcpu/aarch64] add smp support * [libcpu/aarch64] rt_hw_trap_irq get irq instead of iar when using gicv2 * [libcpu/aarch64] disable irq/fiq when switch thread * [libcpu/aarch64] add gtimer frq set and stack align * [libcpu/aarch64] add gicv3 support and bsp/rockchip/rk3568
This commit is contained in:
GUI
@@ -6,10 +6,6 @@ Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
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if not GetDepend('BSP_USING_GIC'):
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SrcRemove(src, 'gic.c')
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CPPPATH = [cwd]
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group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
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+40
-28
@@ -9,20 +9,25 @@
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* 2014-04-03 Grissiom many enhancements
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* 2018-11-22 Jesven add rt_hw_ipi_send()
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* add rt_hw_ipi_handler_install()
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* 2022-03-08 GuEe-GUI add BSP bind SPI CPU self support
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#if defined(BSP_USING_GIC) && defined(BSP_USING_GICV2)
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#include <gic.h>
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#include <cpuport.h>
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#include <board.h>
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struct arm_gic
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{
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rt_uint64_t offset; /* the first interrupt index in the vector table */
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rt_uint64_t dist_hw_base; /* the base address of the gic distributor */
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rt_uint64_t cpu_hw_base; /* the base addrees of the gic cpu interface */
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rt_uint64_t cpu_hw_base; /* the base address of the gic cpu interface */
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};
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/* 'ARM_GIC_MAX_NR' is the number of cores */
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@@ -30,33 +35,33 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
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/** Macro to access the Generic Interrupt Controller Interface (GICC)
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*/
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#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00U)
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#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04U)
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#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08U)
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#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0cU)
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#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10U)
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#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14U)
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#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18U)
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#define GIC_CPU_IIDR(hw_base) __REG32((hw_base) + 0xFCU)
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#define GIC_CPU_CTRL(hw_base) HWREG32((hw_base) + 0x00U)
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#define GIC_CPU_PRIMASK(hw_base) HWREG32((hw_base) + 0x04U)
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#define GIC_CPU_BINPOINT(hw_base) HWREG32((hw_base) + 0x08U)
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#define GIC_CPU_INTACK(hw_base) HWREG32((hw_base) + 0x0cU)
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#define GIC_CPU_EOI(hw_base) HWREG32((hw_base) + 0x10U)
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#define GIC_CPU_RUNNINGPRI(hw_base) HWREG32((hw_base) + 0x14U)
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#define GIC_CPU_HIGHPRI(hw_base) HWREG32((hw_base) + 0x18U)
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#define GIC_CPU_IIDR(hw_base) HWREG32((hw_base) + 0xFCU)
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/** Macro to access the Generic Interrupt Controller Distributor (GICD)
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*/
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#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000U)
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#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004U)
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#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
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#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
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#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
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#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
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#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
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#define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
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#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
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#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400U + ((n)/4U) * 4U)
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#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800U + ((n)/4U) * 4U)
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#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
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#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00U)
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#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
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#define GIC_DIST_SPENDSGI(hw_base, n) __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
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#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8U)
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#define GIC_DIST_CTRL(hw_base) HWREG32((hw_base) + 0x000U)
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#define GIC_DIST_TYPE(hw_base) HWREG32((hw_base) + 0x004U)
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#define GIC_DIST_IGROUP(hw_base, n) HWREG32((hw_base) + 0x080U + ((n)/32U) * 4U)
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#define GIC_DIST_ENABLE_SET(hw_base, n) HWREG32((hw_base) + 0x100U + ((n)/32U) * 4U)
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#define GIC_DIST_ENABLE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x180U + ((n)/32U) * 4U)
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#define GIC_DIST_PENDING_SET(hw_base, n) HWREG32((hw_base) + 0x200U + ((n)/32U) * 4U)
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#define GIC_DIST_PENDING_CLEAR(hw_base, n) HWREG32((hw_base) + 0x280U + ((n)/32U) * 4U)
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#define GIC_DIST_ACTIVE_SET(hw_base, n) HWREG32((hw_base) + 0x300U + ((n)/32U) * 4U)
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#define GIC_DIST_ACTIVE_CLEAR(hw_base, n) HWREG32((hw_base) + 0x380U + ((n)/32U) * 4U)
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#define GIC_DIST_PRI(hw_base, n) HWREG32((hw_base) + 0x400U + ((n)/4U) * 4U)
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#define GIC_DIST_TARGET(hw_base, n) HWREG32((hw_base) + 0x800U + ((n)/4U) * 4U)
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#define GIC_DIST_CONFIG(hw_base, n) HWREG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
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#define GIC_DIST_SOFTINT(hw_base) HWREG32((hw_base) + 0xf00U)
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#define GIC_DIST_CPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
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#define GIC_DIST_SPENDSGI(hw_base, n) HWREG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
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#define GIC_DIST_ICPIDR2(hw_base) HWREG32((hw_base) + 0xfe8U)
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static unsigned int _gic_max_irq;
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@@ -179,7 +184,7 @@ void arm_gic_clear_pending_irq(rt_uint64_t index, int irq)
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}
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}
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void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config)
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void arm_gic_set_configuration(rt_uint64_t index, int irq, rt_uint32_t config)
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{
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rt_uint64_t icfgr;
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rt_uint64_t shift;
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@@ -323,6 +328,8 @@ void arm_gic_send_sgi(rt_uint64_t index, int irq, rt_uint64_t target_list, rt_ui
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GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) =
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((filter_list & 0x3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (irq & 0x0FUL);
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__DSB();
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}
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rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index)
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@@ -341,8 +348,8 @@ rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index)
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void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group)
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{
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uint32_t igroupr;
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uint32_t shift;
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rt_uint32_t igroupr;
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rt_uint32_t shift;
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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RT_ASSERT(group <= 1U);
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@@ -373,6 +380,10 @@ int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start)
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unsigned int gic_type, i;
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rt_uint64_t cpumask = 1U << 0U;
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#ifdef ARM_SPI_BIND_CPU_ID
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cpumask = 1U << ARM_SPI_BIND_CPU_ID;
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#endif
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RT_ASSERT(index < ARM_GIC_MAX_NR);
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_gic_table[index].dist_hw_base = dist_base;
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@@ -502,3 +513,4 @@ long gic_dump(void)
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}
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MSH_CMD_EXPORT(gic_dump, show gic status);
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#endif /* defined(BSP_USING_GIC) && defined(BSP_USING_GICV2) */
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@@ -11,9 +11,9 @@
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#ifndef __GIC_H__
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#define __GIC_H__
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#include <rthw.h>
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#include <stdint.h>
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#include <board.h>
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#include <rtdef.h>
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#if defined(BSP_USING_GIC) && defined(BSP_USING_GICV2)
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int arm_gic_get_active_irq(rt_uint64_t index);
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void arm_gic_ack(rt_uint64_t index, int irq);
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@@ -25,7 +25,7 @@ rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq);
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void arm_gic_set_pending_irq(rt_uint64_t index, int irq);
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void arm_gic_clear_pending_irq(rt_uint64_t index, int irq);
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void arm_gic_set_configuration(rt_uint64_t index, int irq, uint32_t config);
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void arm_gic_set_configuration(rt_uint64_t index, int irq, rt_uint32_t config);
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rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq);
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void arm_gic_clear_active(rt_uint64_t index, int irq);
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@@ -59,5 +59,7 @@ int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base);
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void arm_gic_dump_type(rt_uint64_t index);
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void arm_gic_dump(rt_uint64_t index);
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#endif /* defined(BSP_USING_GIC) && defined(BSP_USING_GICV2) */
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#endif
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,77 @@
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/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-20 Bernard first version
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* 2014-04-03 Grissiom many enhancements
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* 2018-11-22 Jesven add rt_hw_ipi_send()
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* add rt_hw_ipi_handler_install()
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*/
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#ifndef __GICV3_H__
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#define __GICV3_H__
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#include <rtdef.h>
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#if defined(BSP_USING_GIC) && defined(BSP_USING_GICV3)
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#define GICV3_ROUTED_TO_ALL 1UL
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#define GICV3_ROUTED_TO_SPEC 0UL
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int arm_gic_get_active_irq(rt_uint64_t index);
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void arm_gic_ack(rt_uint64_t index, int irq);
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void arm_gic_mask(rt_uint64_t index, int irq);
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void arm_gic_umask(rt_uint64_t index, int irq);
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rt_uint64_t arm_gic_get_pending_irq(rt_uint64_t index, int irq);
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void arm_gic_set_pending_irq(rt_uint64_t index, int irq);
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void arm_gic_clear_pending_irq(rt_uint64_t index, int irq);
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void arm_gic_set_configuration(rt_uint64_t index, int irq, rt_uint32_t config);
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rt_uint64_t arm_gic_get_configuration(rt_uint64_t index, int irq);
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void arm_gic_clear_active(rt_uint64_t index, int irq);
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void arm_gic_set_cpu(rt_uint64_t index, int irq, unsigned int cpumask);
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rt_uint64_t arm_gic_get_target_cpu(rt_uint64_t index, int irq);
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void arm_gic_set_priority(rt_uint64_t index, int irq, rt_uint64_t priority);
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rt_uint64_t arm_gic_get_priority(rt_uint64_t index, int irq);
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void arm_gic_set_interface_prior_mask(rt_uint64_t index, rt_uint64_t priority);
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rt_uint64_t arm_gic_get_interface_prior_mask(rt_uint64_t index);
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void arm_gic_set_binary_point(rt_uint64_t index, rt_uint64_t binary_point);
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rt_uint64_t arm_gic_get_binary_point(rt_uint64_t index);
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rt_uint64_t arm_gic_get_irq_status(rt_uint64_t index, int irq);
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#ifdef RT_USING_SMP
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void arm_gic_send_affinity_sgi(rt_uint64_t index, int irq, rt_uint64_t cpu_masks[], rt_uint64_t routing_mode);
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#endif
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rt_uint64_t arm_gic_get_high_pending_irq(rt_uint64_t index);
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rt_uint64_t arm_gic_get_interface_id(rt_uint64_t index);
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void arm_gic_set_group(rt_uint64_t index, int irq, rt_uint64_t group);
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rt_uint64_t arm_gic_get_group(rt_uint64_t index, int irq);
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int arm_gic_redist_address_set(rt_uint64_t index, rt_uint64_t redist_addr, int cpu_id);
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int arm_gic_cpu_interface_address_set(rt_uint64_t index, rt_uint64_t interface_addr, int cpu_id);
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int arm_gic_dist_init(rt_uint64_t index, rt_uint64_t dist_base, int irq_start);
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int arm_gic_redist_init(rt_uint64_t index, rt_uint64_t redist_base);
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int arm_gic_cpu_init(rt_uint64_t index, rt_uint64_t cpu_base);
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void arm_gic_dump_type(rt_uint64_t index);
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void arm_gic_dump(rt_uint64_t index);
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#endif /* defined(BSP_USING_GIC) && defined(BSP_USING_GICV3) */
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#endif
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@@ -13,6 +13,7 @@
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#include <rtthread.h>
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#include "interrupt.h"
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#include "gic.h"
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#include "gicv3.h"
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#include "armv8.h"
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#include "mmu.h"
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#include "cpuport.h"
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@@ -52,6 +53,9 @@ void rt_hw_interrupt_init(void)
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/* initialize ARM GIC */
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arm_gic_dist_init(0, platform_get_gic_dist_base(), GIC_IRQ_START);
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arm_gic_cpu_init(0, platform_get_gic_cpu_base());
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#ifdef BSP_USING_GICV3
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arm_gic_redist_init(0, platform_get_gic_redist_base());
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#endif
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#endif
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}
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@@ -346,7 +350,11 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
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void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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{
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#ifdef BSP_USING_GIC
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#ifdef BSP_USING_GICV2
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arm_gic_send_sgi(0, ipi_vector, cpu_mask, 0);
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#else
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arm_gic_send_affinity_sgi(0, ipi_vector, (rt_uint64_t *)&cpu_mask, GICV3_ROUTED_TO_SPEC);
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#endif
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#else
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int i;
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@@ -359,8 +367,9 @@ void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
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IPI_MAILBOX_SET(i) = 1 << ipi_vector;
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}
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}
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#endif
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__DSB();
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#endif
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}
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void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
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@@ -29,11 +29,19 @@ static psci_call_handle psci_call = psci_smc_call;
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static uint64_t shutdown_args[3] = {0, 0, 0};
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static uint64_t reboot_args[3] = {0, 0, 0};
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void arm_psci_init(uint64_t *platform_shutdown_args, uint64_t *platform_reboot_args)
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void arm_psci_init(uint64_t method, uint64_t *platform_shutdown_args, uint64_t *platform_reboot_args)
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{
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if (rt_hw_get_current_el() < 2)
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switch (method)
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{
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psci_call = psci_hvc_call;
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case PSCI_METHOD_SMC:
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psci_call = psci_smc_call;
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break;
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case PSCI_METHOD_HVC:
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if (rt_hw_get_current_el() < 2)
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{
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psci_call = psci_hvc_call;
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}
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break;
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}
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if (platform_shutdown_args != RT_NULL)
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@@ -18,6 +18,9 @@
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*/
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#define PSCI_VER_0_2 0x00000002
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#define PSCI_METHOD_SMC 3
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#define PSCI_METHOD_HVC 2
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/* PSCI 0.2 interface */
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#define PSCI_0_2_FN_BASE 0x84000000
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#define PSCI_0_2_FN(n) (PSCI_0_2_FN_BASE + (n))
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@@ -114,7 +117,7 @@
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#define PSCI_RET_DISABLED (-8)
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#define PSCI_RET_INVALID_ADDRESS (-9)
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void arm_psci_init(uint64_t *platform_shutdown_args, uint64_t *platform_reboot_args);
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void arm_psci_init(uint64_t method, uint64_t *platform_shutdown_args, uint64_t *platform_reboot_args);
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||||
uint32_t arm_psci_get_version();
|
||||
uint32_t arm_psci_get_affinity_info(uint64_t target_affinity, uint64_t lowest_affinity_level);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020, RT-Thread Development Team
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -11,19 +11,28 @@
|
||||
*/
|
||||
|
||||
#include "rtconfig.h"
|
||||
.section ".text.entrypoint","ax"
|
||||
|
||||
#define SECONDARY_STACK_SIZE 4096
|
||||
|
||||
.section ".text.entrypoint","ax"
|
||||
|
||||
.globl _start
|
||||
.globl secondary_cpu_start
|
||||
_start:
|
||||
#ifdef RT_USING_SMP
|
||||
mrs x1, mpidr_el1
|
||||
and x1, x1, #0xff
|
||||
cbnz x1, cpu_idle /* If cpu id > 0, stop slave cores */
|
||||
adr x4, .boot_cpu_mpidr
|
||||
str x1, [x4]
|
||||
dsb sy
|
||||
#endif
|
||||
|
||||
bl __asm_flush_dcache_all /* The kernel and data must flush to DDR */
|
||||
|
||||
secondary_cpu_start:
|
||||
#ifdef RT_USING_SMP
|
||||
adr x4, .boot_cpu_mpidr
|
||||
ldr x4, [x4]
|
||||
dsb sy
|
||||
/* Read cpu mpidr_el1 */
|
||||
mrs x1, mpidr_el1
|
||||
|
||||
@@ -34,6 +43,7 @@ secondary_cpu_start:
|
||||
cpu_id_confirm:
|
||||
add x2, x2, #1 /* Next cpu id inc */
|
||||
ldr x3, [x0], #8
|
||||
dsb sy
|
||||
cmp x3, #0
|
||||
beq cpu_idle /* Mean that `rt_cpu_mpidr_early' table is end */
|
||||
cmp x3, x1
|
||||
@@ -42,7 +52,8 @@ cpu_id_confirm:
|
||||
/* Get cpu id success */
|
||||
sub x0, x2, #1
|
||||
msr tpidr_el1, x0 /* Save cpu id global */
|
||||
cbz x0, cpu_setup /* Only go to cpu_setup when cpu id = 0 */
|
||||
cmp x3, x4 /* If it is boot cpu */
|
||||
beq boot_cpu_setup
|
||||
|
||||
/* Set current cpu's stack top */
|
||||
sub x0, x0, #1
|
||||
@@ -53,14 +64,9 @@ cpu_id_confirm:
|
||||
b cpu_check_el
|
||||
#else
|
||||
msr tpidr_el1, xzr
|
||||
b cpu_setup
|
||||
#endif /* RT_USING_SMP */
|
||||
|
||||
cpu_idle:
|
||||
wfe
|
||||
b cpu_idle
|
||||
|
||||
cpu_setup:
|
||||
boot_cpu_setup:
|
||||
ldr x1, =_start
|
||||
|
||||
cpu_check_el:
|
||||
@@ -75,7 +81,7 @@ cpu_check_el:
|
||||
mov x2, #(1 << 0) /* EL0 and EL1 are in Non-Secure state */
|
||||
orr x2, x2, #(1 << 4) /* RES1 */
|
||||
orr x2, x2, #(1 << 5) /* RES1 */
|
||||
orr x2, x2, #(1 << 7) /* SMC instructions are undefined at EL1 and above */
|
||||
bic x2, x2, #(1 << 7) /* SMC instructions are enabled at EL1 and above */
|
||||
orr x2, x2, #(1 << 8) /* HVC instructions are enabled at EL1 and above */
|
||||
orr x2, x2, #(1 << 10) /* The next lower level is AArch64 */
|
||||
msr scr_el3, x2
|
||||
@@ -91,7 +97,7 @@ cpu_check_el:
|
||||
eret
|
||||
|
||||
cpu_not_in_el3: /* Running at EL2 or EL1 */
|
||||
cmp x0, #4 /* EL1 = 0100 */
|
||||
cmp x0, #4 /* EL1 = 0100 */
|
||||
beq cpu_in_el1
|
||||
|
||||
cpu_in_el2:
|
||||
@@ -159,9 +165,16 @@ clean_bss_check:
|
||||
|
||||
jump_to_entry:
|
||||
b rtthread_startup
|
||||
b cpu_idle /* For failsafe, halt this core too */
|
||||
|
||||
cpu_idle:
|
||||
wfe
|
||||
b cpu_idle
|
||||
|
||||
#ifdef RT_USING_SMP
|
||||
.align 3
|
||||
.boot_cpu_mpidr:
|
||||
.quad 0x0
|
||||
|
||||
.align 12
|
||||
.secondary_cpu_stack:
|
||||
.space (SECONDARY_STACK_SIZE * (RT_CPUS_NR - 1))
|
||||
|
||||
Reference in New Issue
Block a user