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[rt-smart] porting c906 and D1s to mm (#6848)

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* [rv64/bsp] porting to mm

* [mm] report more info for debugging

* [fix] code format

* [libcpu/c906] porting to RTOS

* [fix] using rtdbg api

* [fix] add return

* [fix] report more information for debugging

* [fix] use assert 0 for unrecoverable error
This commit is contained in:
Shell
2023-01-16 08:24:03 +08:00
committed by GitHub
parent fec7404506
commit f0dadcb3c3
30 changed files with 1271 additions and 432 deletions
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libcpu/risc-v/t-head/c906/context_gcc.S
-1
View File
@@ -10,7 +10,6 @@
* 2021/02/02 lizhirui Add userspace support
*/
#define __ASSEMBLY__
#include "cpuport.h"
#include "stackframe.h"
libcpu/risc-v/t-head/c906/cpuport.c
+2 -1
View File
@@ -17,8 +17,9 @@
#include "sbi.h"
#include "stack.h"
#ifdef RT_USING_SMART
#include <lwp_arch.h>
#endif
/**
* @brief from thread used interrupt context switch
libcpu/risc-v/t-head/c906/interrupt_gcc.S
+6 -1
View File
@@ -11,7 +11,6 @@
* 2021/12/24 JasonHu Add user setting save/restore
*/
#define __ASSEMBLY__
#include "cpuport.h"
#include "encoding.h"
#include "stackframe.h"
@@ -31,10 +30,12 @@ trap_entry:
RESTORE_SYS_GP
#ifdef RT_USING_SMART
//check syscall
csrr t0, scause
li t1, 8//environment call from u-mode
beq t0, t1, syscall_entry
#endif
csrr a0, scause
csrrc a1, stval, zero
@@ -53,21 +54,25 @@ trap_entry:
.global rt_hw_context_switch_interrupt_do
rt_hw_context_switch_interrupt_do:
#ifdef RT_USING_SMART
//swap to thread kernel stack
csrr t0, sstatus
andi t0, t0, 0x100
beqz t0, __restore_sp_from_tcb_interrupt
#endif
__restore_sp_from_sscratch_interrupt:
csrr t0, sscratch
j __move_stack_context_interrupt
#ifdef RT_USING_SMART
__restore_sp_from_tcb_interrupt:
la s0, rt_interrupt_from_thread
LOAD a0, 0(s0)
jal rt_thread_sp_to_thread
jal get_thread_kernel_stack_top
mv t0, a0
#endif
__move_stack_context_interrupt:
mv t1, sp//src
libcpu/risc-v/t-head/c906/mmu.c
+15 -14
View File
@@ -6,13 +6,17 @@
* Change Logs:
* Date Author Notes
* 2021-01-30 lizhirui first version
* 2022-12-13 WangXiaoyao Port to new mm
*/
#include "rtconfig.h"
#include <rtthread.h>
#include <stddef.h>
#include <stdint.h>
#define DBG_TAG "hw.mmu"
#define DBG_LVL DBG_WARNING
#include <rtdbg.h>
#include <cache.h>
#include <mm_aspace.h>
#include <mm_page.h>
@@ -23,13 +27,8 @@
#ifdef RT_USING_SMART
#include <ioremap.h>
#include <lwp_user_mm.h>
#include <tlb.h>
#endif
#define DBG_TAG "MMU"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
#ifndef RT_USING_SMART
#define PV_OFFSET 0
#define USER_VADDR_START 0
@@ -37,20 +36,21 @@
static size_t _unmap_area(struct rt_aspace *aspace, void *v_addr, size_t size);
static void *current_mmu_table = RT_NULL;
volatile __attribute__((aligned(4 * 1024)))
rt_ubase_t MMUTable[__SIZE(VPN2_BIT)];
void rt_hw_aspace_switch(rt_aspace_t aspace)
{
uintptr_t page_table = (uintptr_t)_rt_kmem_v2p(aspace->page_table);
current_mmu_table = aspace->page_table;
write_csr(satp, (((size_t)SATP_MODE) << SATP_MODE_OFFSET) |
((rt_ubase_t)page_table >> PAGE_OFFSET_BIT));
rt_hw_tlb_invalidate_all_local();
}
static void *current_mmu_table = RT_NULL;
volatile __attribute__((aligned(4 * 1024)))
rt_ubase_t MMUTable[__SIZE(VPN2_BIT)];
void *rt_hw_mmu_tbl_get()
{
return current_mmu_table;
@@ -256,7 +256,7 @@ static inline void _init_region(void *vaddr, size_t size)
rt_ioremap_start = vaddr;
rt_ioremap_size = size;
rt_mpr_start = rt_ioremap_start - rt_mpr_size;
rt_kprintf("rt_ioremap_start: %p, rt_mpr_start: %p\n", rt_ioremap_start, rt_mpr_start);
LOG_D("rt_ioremap_start: %p, rt_mpr_start: %p", rt_ioremap_start, rt_mpr_start);
}
#else
static inline void _init_region(void *vaddr, size_t size)
@@ -382,7 +382,8 @@ void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr)
}
else
{
paddr = 0;
LOG_I("%s: failed at %p", __func__, vaddr);
paddr = (uintptr_t)ARCH_MAP_FAILED;
}
return (void *)paddr;
}
@@ -418,7 +419,7 @@ int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
{
uintptr_t *pte = _query(aspace, vaddr, &level);
void *range_end = vaddr + _get_level_size(level);
RT_ASSERT(range_end < vend);
RT_ASSERT(range_end <= vend);
if (pte)
{
libcpu/risc-v/t-head/c906/mmu.h
-9
View File
@@ -50,8 +50,6 @@ struct mem_desc
#define COMBINEPTE(paddr, attr) \
((((paddr) >> PAGE_OFFSET_BIT) << PTE_PPN_SHIFT) | (attr))
#define ARCH_ADDRESS_WIDTH_BITS 64
#define MMU_MAP_ERROR_VANOTALIGN -1
#define MMU_MAP_ERROR_PANOTALIGN -2
#define MMU_MAP_ERROR_NOPAGE -3
@@ -82,13 +80,6 @@ static inline void *rt_kmem_v2p(void *vaddr)
return paddr;
}
enum rt_mmu_cntl
{
MMU_CNTL_NONCACHE,
MMU_CNTL_CACHE,
MMU_CNTL_DUMMY_END,
};
int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
enum rt_mmu_cntl cmd);
libcpu/risc-v/t-head/c906/plic.c
+27
View File
@@ -19,6 +19,7 @@
#include "encoding.h"
static void *c906_plic_regs = RT_NULL;
extern struct rt_irq_desc isr_table[];
struct plic_handler
{
@@ -44,6 +45,32 @@ rt_inline void plic_irq_toggle(int hwirq, int enable)
}
}
static void generic_handle_irq(int irq)
{
rt_isr_handler_t isr;
void *param;
if (irq < 0 || irq >= IRQ_MAX_NR)
{
LOG_E("bad irq number %d!\n", irq);
return;
}
if (!irq) // irq = 0 => no irq
{
LOG_W("no irq!\n");
return;
}
isr = isr_table[IRQ_OFFSET + irq].handler;
param = isr_table[IRQ_OFFSET + irq].param;
if (isr != RT_NULL)
{
isr(irq, param);
}
/* complete irq. */
plic_complete(irq);
}
void plic_complete(int irqno)
{
int cpu = 0;
libcpu/risc-v/t-head/c906/riscv_mmu.h
+16 -11
View File
@@ -51,20 +51,25 @@
#define PHYSICAL_ADDRESS_WIDTH_BITS 56
#define PAGE_ATTR_NEXT_LEVEL (0)
#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
#define PAGE_ATTR_READONLY (PTE_R)
#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R)
#define PAGE_ATTR_NEXT_LEVEL (0)
#define PAGE_ATTR_RWX (PTE_X | PTE_W | PTE_R)
#define PAGE_ATTR_READONLY (PTE_R)
#define PAGE_ATTR_XN (PTE_W | PTE_R)
#define PAGE_ATTR_READEXECUTE (PTE_X | PTE_R)
#define PAGE_ATTR_USER (PTE_U)
#define PAGE_ATTR_SYSTEM (0)
#define PAGE_DEFAULT_ATTR_LEAF (PAGE_ATTR_RWX | PAGE_ATTR_USER | PTE_V | PTE_G)
#define PAGE_DEFAULT_ATTR_NEXT (PAGE_ATTR_NEXT_LEVEL | PTE_V | PTE_G)
#define PAGE_ATTR_CB (PTE_BUF | PTE_CACHE)
#define PAGE_ATTR_DEV (PTE_SO)
#define PAGE_DEFAULT_ATTR_LEAF (PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_U | PAGE_ATTR_RWX | PTE_V)
#define PAGE_DEFAULT_ATTR_NEXT (PTE_SHARE | PTE_BUF | PTE_CACHE | PTE_A | PTE_D | PTE_G | PTE_V)
#define PAGE_IS_LEAF(pte) __MASKVALUE(pte, PAGE_ATTR_RWX)
#define PTE_USED(pte) __MASKVALUE(pte, PTE_V)
#define PTE_WRAP(attr) (attr | PTE_A | PTE_D)
/**
* encoding of SATP (Supervisor Address Translation and Protection register)
@@ -79,11 +84,11 @@
#define ARCH_VADDR_WIDTH 39
#define SATP_MODE SATP_MODE_SV39
#define MMU_MAP_K_DEVICE (PTE_G | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_K_RWCB (PTE_G | PTE_X | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_U_RWCB (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_U_RWCB_XN (PTE_U | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_U_RW (PTE_U | PTE_X | PTE_W | PTE_R | PTE_V)
#define MMU_MAP_K_DEVICE PTE_WRAP(PAGE_ATTR_DEV | PTE_G | PAGE_ATTR_XN | PTE_V)
#define MMU_MAP_K_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_G | PAGE_ATTR_RWX | PTE_V)
#define MMU_MAP_U_RWCB PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_RWX | PTE_V)
#define MMU_MAP_U_RWCB_XN PTE_WRAP(PAGE_ATTR_CB | PTE_U | PAGE_ATTR_XN | PTE_V)
#define MMU_MAP_U_RW PTE_WRAP(PTE_U | PAGE_ATTR_RWX | PTE_V)
#define PTE_XWR_MASK 0xe
libcpu/risc-v/t-head/c906/rt_interrupt.h
-2
View File
@@ -43,6 +43,4 @@ void rt_hw_interrupt_mask(int vector);
void rt_hw_interrupt_umask(int vector);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
void generic_handle_irq(int irq);
#endif
libcpu/risc-v/t-head/c906/sbi.c
+2 -2
View File
@@ -68,8 +68,8 @@ static struct sbi_ret sbi_get_impl_version(void)
void sbi_print_version(void)
{
u_int major;
u_int minor;
unsigned int major;
unsigned int minor;
/* For legacy SBI implementations. */
if (sbi_spec_version == 0)
libcpu/risc-v/t-head/c906/startup_gcc.S
+70 -58
View File
@@ -10,72 +10,84 @@
* 2020/6/12 Xim Port to QEMU and remove SMP support
*/
#define __ASSEMBLY__
#define SSTATUS_FS 0x00006000U /* initial state of FPU, clear to disable */
#include <encoding.h>
#include <cpuport.h>
.global _start
.section ".start", "ax"
boot_hartid: .int
.global boot_hartid
.global _start
.section ".start", "ax"
_start:
j 1f
.word 0xdeadbeef
.align 3
.global g_wake_up
g_wake_up:
.dword 1
.dword 0
j 1f
.word 0xdeadbeef
.align 3
.global g_wake_up
g_wake_up:
.dword 1
.dword 0
1:
csrw sie, 0
csrw sip, 0
la t0, trap_entry
csrw stvec, t0
/* save hartid */
la t0, boot_hartid /* global varible rt_boot_hartid */
mv t1, a0 /* get hartid in S-mode frome a0 register */
sw t1, (t0) /* store t1 register low 4 bits in memory address which is stored in t0 */
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
/* clear Interrupt Registers */
csrw sie, 0
csrw sip, 0
/* set Trap Vector Base Address Register */
la t0, trap_entry
csrw stvec, t0
/* set to disable FPU */
li t0, SSTATUS_FS
csrc sstatus, t0
li t0, 0x40000 // SUM in sstatus
csrs sstatus, t0
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
/* set to disable FPU */
li t0, SSTATUS_FS
csrc sstatus, t0
li t0, SSTATUS_SUM
csrs sstatus, t0
.option push
.option norelax
la gp, __global_pointer$
la gp, __global_pointer$
.option pop
// removed SMP support here
la sp, __stack_start__
li t0, __STACKSIZE__
add sp, sp, t0
csrw sscratch, sp
j primary_cpu_entry
/* removed SMP support here */
la sp, __stack_start__
li t0, __STACKSIZE__
add sp, sp, t0
csrw sscratch, sp
call init_bss
call sbi_init
j primary_cpu_entry
libcpu/risc-v/t-head/c906/syscall_c.c
+3 -1
View File
@@ -12,6 +12,8 @@
#include <rthw.h>
#include <rtthread.h>
#ifdef RT_USING_SMART
#define DBG_TAG "syscall"
#define DBG_LVL DBG_WARNING
#include <rtdbg.h>
@@ -19,7 +21,6 @@
#include <stdint.h>
#include <mmu.h>
#include <page.h>
#include <lwp_mm_area.h>
#include <lwp_user_mm.h>
#include "riscv_mmu.h"
@@ -58,3 +59,4 @@ void syscall_handler(struct rt_hw_stack_frame *regs)
regs->epc += 4; // skip ecall instruction
LOG_I("[0x%lx] %s ret: 0x%lx", rt_thread_self(), syscall_name, regs->a0);
}
#endif /* RT_USING_SMART */
libcpu/risc-v/t-head/c906/tlb.h
+6 -6
View File
@@ -10,17 +10,17 @@
#ifndef __TLB_H__
#define __TLB_H__
#include "mm_aspace.h"
#include "riscv_mmu.h"
#include "rtdbg.h"
#include "rtthread.h"
#include <sbi.h>
#include <stddef.h>
#include <stdint.h>
#include <rtthread.h>
#include <mm_aspace.h>
#include "sbi.h"
#include "riscv_mmu.h"
#define HANDLE_FAULT(ret) \
if (__builtin_expect((ret) != SBI_SUCCESS, 0)) \
LOG_W("%s failed", __FUNCTION__);
LOG_W("%s failed\n", __FUNCTION__);
static inline void rt_hw_tlb_invalidate_all(void)
{
libcpu/risc-v/t-head/c906/trap.c
+190 -154
View File
@@ -11,115 +11,68 @@
#include <rthw.h>
#include <rtthread.h>
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
#include <stdint.h>
#include "board.h"
#include "tick.h"
#include "drv_uart.h"
#include <mm_fault.h>
#include "mmu.h"
#include "encoding.h"
#include "stack.h"
#include "sbi.h"
#include "riscv.h"
#include "rt_interrupt.h"
#include "plic.h"
#ifdef RT_USING_SMART
#include "riscv_mmu.h"
#include "mmu.h"
#include "page.h"
#include "lwp_arch.h"
#include <lwp_arch.h>
#else
#define rt_hw_backtrace(...) (0)
#endif
#define DBG_TAG "libcpu.trap"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void dump_regs(struct rt_hw_stack_frame *regs)
{
rt_kprintf("--------------Dump Registers-----------------\n");
rt_kprintf("Function Registers:\n");
rt_kprintf("\tra(x1) = 0x%p(",regs->ra);
rt_kprintf(")\n");
rt_kprintf("\tuser_sp(x2) = 0x%p(",regs->user_sp_exc_stack);
rt_kprintf(")\n");
rt_kprintf("\tgp(x3) = 0x%p(",regs->gp);
rt_kprintf(")\n");
rt_kprintf("\ttp(x4) = 0x%p(",regs->tp);
rt_kprintf(")\n");
rt_kprintf("\tra(x1) = 0x%p\tuser_sp = 0x%p\n", regs->ra, regs->user_sp_exc_stack);
rt_kprintf("\tgp(x3) = 0x%p\ttp(x4) = 0x%p\n", regs->gp, regs->tp);
rt_kprintf("Temporary Registers:\n");
rt_kprintf("\tt0(x5) = 0x%p(",regs->t0);
rt_kprintf(")\n");
rt_kprintf("\tt1(x6) = 0x%p(",regs->t1);
rt_kprintf(")\n");
rt_kprintf("\tt2(x7) = 0x%p(",regs->t2);
rt_kprintf(")\n");
rt_kprintf("\tt3(x28) = 0x%p(",regs->t3);
rt_kprintf(")\n");
rt_kprintf("\tt4(x29) = 0x%p(",regs->t4);
rt_kprintf(")\n");
rt_kprintf("\tt5(x30) = 0x%p(",regs->t5);
rt_kprintf(")\n");
rt_kprintf("\tt6(x31) = 0x%p(",regs->t6);
rt_kprintf(")\n");
rt_kprintf("\tt0(x5) = 0x%p\tt1(x6) = 0x%p\n", regs->t0, regs->t1);
rt_kprintf("\tt2(x7) = 0x%p\n", regs->t2);
rt_kprintf("\tt3(x28) = 0x%p\tt4(x29) = 0x%p\n", regs->t3, regs->t4);
rt_kprintf("\tt5(x30) = 0x%p\tt6(x31) = 0x%p\n", regs->t5, regs->t6);
rt_kprintf("Saved Registers:\n");
rt_kprintf("\ts0/fp(x8) = 0x%p(",regs->s0_fp);
rt_kprintf(")\n");
rt_kprintf("\ts1(x9) = 0x%p(",regs->s1);
rt_kprintf(")\n");
rt_kprintf("\ts2(x18) = 0x%p(",regs->s2);
rt_kprintf(")\n");
rt_kprintf("\ts3(x19) = 0x%p(",regs->s3);
rt_kprintf(")\n");
rt_kprintf("\ts4(x20) = 0x%p(",regs->s4);
rt_kprintf(")\n");
rt_kprintf("\ts5(x21) = 0x%p(",regs->s5);
rt_kprintf(")\n");
rt_kprintf("\ts6(x22) = 0x%p(",regs->s6);
rt_kprintf(")\n");
rt_kprintf("\ts7(x23) = 0x%p(",regs->s7);
rt_kprintf(")\n");
rt_kprintf("\ts8(x24) = 0x%p(",regs->s8);
rt_kprintf(")\n");
rt_kprintf("\ts9(x25) = 0x%p(",regs->s9);
rt_kprintf(")\n");
rt_kprintf("\ts10(x26) = 0x%p(",regs->s10);
rt_kprintf(")\n");
rt_kprintf("\ts11(x27) = 0x%p(",regs->s11);
rt_kprintf(")\n");
rt_kprintf("\ts0/fp(x8) = 0x%p\ts1(x9) = 0x%p\n", regs->s0_fp, regs->s1);
rt_kprintf("\ts2(x18) = 0x%p\ts3(x19) = 0x%p\n", regs->s2, regs->s3);
rt_kprintf("\ts4(x20) = 0x%p\ts5(x21) = 0x%p\n", regs->s4, regs->s5);
rt_kprintf("\ts6(x22) = 0x%p\ts7(x23) = 0x%p\n", regs->s6, regs->s7);
rt_kprintf("\ts8(x24) = 0x%p\ts9(x25) = 0x%p\n", regs->s8, regs->s9);
rt_kprintf("\ts10(x26) = 0x%p\ts11(x27) = 0x%p\n", regs->s10, regs->s11);
rt_kprintf("Function Arguments Registers:\n");
rt_kprintf("\ta0(x10) = 0x%p(",regs->a0);
rt_kprintf(")\n");
rt_kprintf("\ta1(x11) = 0x%p(",regs->a1);
rt_kprintf(")\n");
rt_kprintf("\ta2(x12) = 0x%p(",regs->a2);
rt_kprintf(")\n");
rt_kprintf("\ta3(x13) = 0x%p(",regs->a3);
rt_kprintf(")\n");
rt_kprintf("\ta4(x14) = 0x%p(",regs->a4);
rt_kprintf(")\n");
rt_kprintf("\ta5(x15) = 0x%p(",regs->a5);
rt_kprintf(")\n");
rt_kprintf("\ta6(x16) = 0x%p(",regs->a6);
rt_kprintf(")\n");
rt_kprintf("\ta7(x17) = 0x%p(",regs->a7);
rt_kprintf(")\n");
rt_kprintf("sstatus = 0x%p\n",regs->sstatus);
rt_kprintf("\t%s\n",(regs->sstatus & SSTATUS_SIE) ? "Supervisor Interrupt Enabled" : "Supervisor Interrupt Disabled");
rt_kprintf("\t%s\n",(regs->sstatus & SSTATUS_SPIE) ? "Last Time Supervisor Interrupt Enabled" : "Last Time Supervisor Interrupt Disabled");
rt_kprintf("\t%s\n",(regs->sstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode");
rt_kprintf("\t%s\n",(regs->sstatus & SSTATUS_SUM) ? "Permit to Access User Page" : "Not Permit to Access User Page");
rt_kprintf("\t%s\n",(regs->sstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page");
rt_kprintf("\ta0(x10) = 0x%p\ta1(x11) = 0x%p\n", regs->a0, regs->a1);
rt_kprintf("\ta2(x12) = 0x%p\ta3(x13) = 0x%p\n", regs->a2, regs->a3);
rt_kprintf("\ta4(x14) = 0x%p\ta5(x15) = 0x%p\n", regs->a4, regs->a5);
rt_kprintf("\ta6(x16) = 0x%p\ta7(x17) = 0x%p\n", regs->a6, regs->a7);
rt_kprintf("sstatus = 0x%p\n", regs->sstatus);
rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SIE) ? "Supervisor Interrupt Enabled" : "Supervisor Interrupt Disabled");
rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SPIE) ? "Last Time Supervisor Interrupt Enabled" : "Last Time Supervisor Interrupt Disabled");
rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SPP) ? "Last Privilege is Supervisor Mode" : "Last Privilege is User Mode");
rt_kprintf("\t%s\n", (regs->sstatus & SSTATUS_SUM) ? "Permit to Access User Page" : "Not Permit to Access User Page");
rt_kprintf("\t%s\n", (regs->sstatus & (1 << 19)) ? "Permit to Read Executable-only Page" : "Not Permit to Read Executable-only Page");
rt_size_t satp_v = read_csr(satp);
rt_kprintf("satp = 0x%p\n",satp_v);
#ifdef RT_USING_SMART
rt_kprintf("\tCurrent Page Table(Physical) = 0x%p\n",__MASKVALUE(satp_v,__MASK(44)) << PAGE_OFFSET_BIT);
rt_kprintf("\tCurrent ASID = 0x%p\n",__MASKVALUE(satp_v >> 44,__MASK(16)) << PAGE_OFFSET_BIT);
#endif
rt_kprintf("satp = 0x%p\n", satp_v);
rt_kprintf("\tCurrent Page Table(Physical) = 0x%p\n", __MASKVALUE(satp_v, __MASK(44)) << PAGE_OFFSET_BIT);
rt_kprintf("\tCurrent ASID = 0x%p\n", __MASKVALUE(satp_v >> 44, __MASK(16)) << PAGE_OFFSET_BIT);
const char *mode_str = "Unknown Address Translation/Protection Mode";
switch(__MASKVALUE(satp_v >> 60,__MASK(4)))
switch (__MASKVALUE(satp_v >> 60, __MASK(4)))
{
case 0:
mode_str = "No Address Translation/Protection Mode";
@@ -134,73 +87,55 @@ void dump_regs(struct rt_hw_stack_frame *regs)
break;
}
rt_kprintf("\tMode = %s\n",mode_str);
rt_kprintf("\tMode = %s\n", mode_str);
rt_kprintf("-----------------Dump OK---------------------\n");
}
static const char *Exception_Name[] =
{
"Instruction Address Misaligned",
"Instruction Access Fault",
"Illegal Instruction",
"Breakpoint",
"Load Address Misaligned",
"Load Access Fault",
"Store/AMO Address Misaligned",
"Store/AMO Access Fault",
"Environment call from U-mode",
"Environment call from S-mode",
"Reserved-10",
"Reserved-11",
"Instruction Page Fault",
"Load Page Fault",
"Reserved-14",
"Store/AMO Page Fault"
};
{
"Instruction Address Misaligned",
"Instruction Access Fault",
"Illegal Instruction",
"Breakpoint",
"Load Address Misaligned",
"Load Access Fault",
"Store/AMO Address Misaligned",
"Store/AMO Access Fault",
"Environment call from U-mode",
"Environment call from S-mode",
"Reserved-10",
"Reserved-11",
"Instruction Page Fault",
"Load Page Fault",
"Reserved-14",
"Store/AMO Page Fault"};
static const char *Interrupt_Name[] =
{
"User Software Interrupt",
"Supervisor Software Interrupt",
"Reversed-2",
"Reversed-3",
"User Timer Interrupt",
"Supervisor Timer Interrupt",
"Reversed-6",
"Reversed-7",
"User External Interrupt",
"Supervisor External Interrupt",
"Reserved-10",
"Reserved-11",
};
extern struct rt_irq_desc isr_table[];
void generic_handle_irq(int irq)
{
rt_isr_handler_t isr;
void *param;
if (irq < 0 || irq >= IRQ_MAX_NR)
{
LOG_E("bad irq number %d!\n", irq);
return;
}
"User Software Interrupt",
"Supervisor Software Interrupt",
"Reversed-2",
"Reversed-3",
"User Timer Interrupt",
"Supervisor Timer Interrupt",
"Reversed-6",
"Reversed-7",
"User External Interrupt",
"Supervisor External Interrupt",
"Reserved-10",
"Reserved-11",
};
if (!irq) // irq = 0 => no irq
{
LOG_W("no irq!\n");
return;
}
isr = isr_table[IRQ_OFFSET + irq].handler;
param = isr_table[IRQ_OFFSET + irq].param;
if (isr != RT_NULL)
{
isr(irq, param);
}
/* complete irq. */
plic_complete(irq);
}
#ifndef RT_USING_SMP
static volatile int nested = 0;
#define ENTER_TRAP \
nested += 1
#define EXIT_TRAP \
nested -= 1
#define CHECK_NESTED_PANIC(cause, tval, epc, eframe) \
if (nested != 1) \
handle_nested_trap_panic(cause, tval, epc, eframe)
#endif /* RT_USING_SMP */
static const char *get_exception_msg(int id)
{
@@ -216,33 +151,134 @@ static const char *get_exception_msg(int id)
return msg;
}
#ifdef RT_USING_SMART
void handle_user(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw_stack_frame *sp)
{
rt_size_t id = __MASKVALUE(scause, __MASK(63UL));
#ifdef RT_USING_USERSPACE
/* user page fault */
if (id == EP_LOAD_PAGE_FAULT ||
id == EP_STORE_PAGE_FAULT)
enum rt_mm_fault_op fault_op;
enum rt_mm_fault_type fault_type;
switch (id)
{
if (arch_expand_user_stack((void *)stval))
case EP_LOAD_PAGE_FAULT:
fault_op = MM_FAULT_OP_READ;
fault_type = MM_FAULT_TYPE_PAGE_FAULT;
break;
case EP_LOAD_ACCESS_FAULT:
fault_op = MM_FAULT_OP_READ;
fault_type = MM_FAULT_TYPE_ACCESS_FAULT;
break;
case EP_LOAD_ADDRESS_MISALIGNED:
fault_op = MM_FAULT_OP_READ;
fault_type = MM_FAULT_TYPE_BUS_ERROR;
break;
case EP_STORE_PAGE_FAULT:
fault_op = MM_FAULT_OP_WRITE;
fault_type = MM_FAULT_TYPE_PAGE_FAULT;
break;
case EP_STORE_ACCESS_FAULT:
fault_op = MM_FAULT_OP_WRITE;
fault_type = MM_FAULT_TYPE_ACCESS_FAULT;
break;
case EP_STORE_ADDRESS_MISALIGNED:
fault_op = MM_FAULT_OP_WRITE;
fault_type = MM_FAULT_TYPE_BUS_ERROR;
break;
case EP_INSTRUCTION_PAGE_FAULT:
fault_op = MM_FAULT_OP_EXECUTE;
fault_type = MM_FAULT_TYPE_PAGE_FAULT;
break;
case EP_INSTRUCTION_ACCESS_FAULT:
fault_op = MM_FAULT_OP_EXECUTE;
fault_type = MM_FAULT_TYPE_ACCESS_FAULT;
break;
case EP_INSTRUCTION_ADDRESS_MISALIGNED:
fault_op = MM_FAULT_OP_EXECUTE;
fault_type = MM_FAULT_TYPE_BUS_ERROR;
break;
default:
fault_op = 0;
}
if (fault_op)
{
struct rt_mm_fault_msg msg = {
.fault_op = fault_op,
.fault_type = fault_type,
.vaddr = (void *)stval,
};
if (rt_mm_fault_try_fix(&msg))
{
return;
}
}
#endif
LOG_E("[FATAL ERROR] Exception %ld:%s", id, get_exception_msg(id));
LOG_E("scause:0x%p,stval:0x%p,sepc:0x%p", scause, stval, sepc);
LOG_E("[FATAL ERROR] Exception %ld:%s\n", id, get_exception_msg(id));
LOG_E("scause:0x%p,stval:0x%p,sepc:0x%p\n", scause, stval, sepc);
dump_regs(sp);
rt_hw_backtrace((uint32_t *)sp->s0_fp, sepc);
LOG_E("User Fault, killing thread: %s", rt_thread_self()->name);
EXIT_TRAP;
sys_exit(-1);
}
#endif
#ifdef ENABLE_VECTOR
static void vector_enable(struct rt_hw_stack_frame *sp)
{
sp->sstatus |= SSTATUS_VS_INITIAL;
}
/**
* detect V/D support, and do not distinguish V/D instruction
*/
static int illegal_inst_recoverable(rt_ubase_t stval, struct rt_hw_stack_frame *sp)
{
// first 7 bits is opcode
int opcode = stval & 0x7f;
int csr = (stval & 0xFFF00000) >> 20;
// ref riscv-v-spec-1.0, [Vector Instruction Formats]
int width = ((stval & 0x7000) >> 12) - 1;
int flag = 0;
switch (opcode)
{
case 0x57: // V
case 0x27: // scalar FLOAT
case 0x07:
case 0x73: // CSR
flag = 1;
break;
}
if (flag)
{
vector_enable(sp);
}
return flag;
}
#endif
static void handle_nested_trap_panic(
rt_size_t cause,
rt_size_t tval,
rt_size_t epc,
struct rt_hw_stack_frame *eframe)
{
LOG_E("\n-------- [SEVER ERROR] --------");
LOG_E("Nested trap detected");
LOG_E("scause:0x%p,stval:0x%p,sepc:0x%p\n", cause, tval, epc);
dump_regs(eframe);
rt_hw_cpu_shutdown();
}
/* Trap entry */
void handle_trap(rt_size_t scause,rt_size_t stval,rt_size_t sepc,struct rt_hw_stack_frame *sp)
void handle_trap(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw_stack_frame *sp)
{
rt_size_t id = __MASKVALUE(scause,__MASK(63UL));
const char *msg;
@@ -277,13 +313,14 @@ void handle_trap(rt_size_t scause,rt_size_t stval,rt_size_t sepc,struct rt_hw_st
}
else
{
#ifdef RT_USING_SMART
if (!(sp->sstatus & 0x100))
{
handle_user(scause, stval, sepc, sp);
// after handle_user(), return to user space.
// otherwise it never returns
// if handle_user() return here, jump to u mode then
return ;
}
#endif
// handle kernel exception:
rt_kprintf("Unhandled Exception %ld:%s\n", id, get_exception_msg(id));
@@ -293,7 +330,6 @@ void handle_trap(rt_size_t scause,rt_size_t stval,rt_size_t sepc,struct rt_hw_st
dump_regs(sp);
rt_kprintf("--------------Thread list--------------\n");
rt_kprintf("current thread: %s\n", rt_thread_self()->name);
list_process();
extern struct rt_thread *rt_current_thread;
rt_kprintf("--------------Backtrace--------------\n");
libcpu/risc-v/virt64/interrupt.h
+23 -6
View File
@@ -11,19 +11,36 @@
#ifndef INTERRUPT_H__
#define INTERRUPT_H__
#define MAX_HANDLERS 128
#define MAX_HANDLERS 128
#include <rthw.h>
#include "stack.h"
// int rt_hw_clint_ipi_enable(void);
// int rt_hw_clint_ipi_disable(void);
enum
{
EP_INSTRUCTION_ADDRESS_MISALIGNED = 0,
EP_INSTRUCTION_ACCESS_FAULT,
EP_ILLEGAL_INSTRUCTION,
EP_BREAKPOINT,
EP_LOAD_ADDRESS_MISALIGNED,
EP_LOAD_ACCESS_FAULT,
EP_STORE_ADDRESS_MISALIGNED,
EP_STORE_ACCESS_FAULT,
EP_ENVIRONMENT_CALL_U_MODE,
EP_ENVIRONMENT_CALL_S_MODE,
EP_RESERVED10,
EP_ENVIRONMENT_CALL_M_MODE,
EP_INSTRUCTION_PAGE_FAULT, /* page attr */
EP_LOAD_PAGE_FAULT, /* read data */
EP_RESERVED14,
EP_STORE_PAGE_FAULT, /* write data */
};
int rt_hw_plic_irq_enable(int irq_number);
int rt_hw_plic_irq_disable(int irq_number);
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, const char *name);
void handle_trap(rt_size_t xcause,rt_size_t xtval,rt_size_t xepc,struct rt_hw_stack_frame *sp);
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
void handle_trap(rt_size_t xcause, rt_size_t xtval, rt_size_t xepc, struct rt_hw_stack_frame *sp);
#endif
libcpu/risc-v/virt64/mmu.c
+5 -5
View File
@@ -13,6 +13,10 @@
#include <stddef.h>
#include <stdint.h>
#define DBG_TAG "hw.mmu"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
#include <cache.h>
#include <mm_aspace.h>
#include <mm_page.h>
@@ -23,13 +27,8 @@
#ifdef RT_USING_SMART
#include <ioremap.h>
#include <lwp_user_mm.h>
#include <tlb.h>
#endif
#define DBG_TAG "hw.mmu"
#define DBG_LVL DBG_LOG
#include <rtdbg.h>
#ifndef RT_USING_SMART
#define PV_OFFSET 0
#define USER_VADDR_START 0
@@ -257,6 +256,7 @@ static inline void _init_region(void *vaddr, size_t size)
rt_ioremap_start = vaddr;
rt_ioremap_size = size;
rt_mpr_start = rt_ioremap_start - rt_mpr_size;
LOG_D("rt_ioremap_start: %p, rt_mpr_start: %p", rt_ioremap_start, rt_mpr_start);
}
#else
static inline void _init_region(void *vaddr, size_t size)
libcpu/risc-v/virt64/mmu.h
-2
View File
@@ -50,8 +50,6 @@ struct mem_desc
#define COMBINEPTE(paddr, attr) \
((((paddr) >> PAGE_OFFSET_BIT) << PTE_PPN_SHIFT) | (attr))
#define ARCH_ADDRESS_WIDTH_BITS 64
#define MMU_MAP_ERROR_VANOTALIGN -1
#define MMU_MAP_ERROR_PANOTALIGN -2
#define MMU_MAP_ERROR_NOPAGE -3
libcpu/risc-v/virt64/startup_gcc.S
+68 -68
View File
@@ -14,83 +14,83 @@
#include <cpuport.h>
boot_hartid: .int
.global boot_hartid
.global boot_hartid
.global _start
.section ".start", "ax"
.global _start
.section ".start", "ax"
_start:
j 1f
.word 0xdeadbeef
.align 3
.global g_wake_up
g_wake_up:
.dword 1
.dword 0
j 1f
.word 0xdeadbeef
.align 3
.global g_wake_up
g_wake_up:
.dword 1
.dword 0
1:
# save hartid
la t0, boot_hartid # global varible rt_boot_hartid
mv t1, a0 # get hartid in S-mode frome a0 register
sw t1, (t0) # store t1 register low 4 bits in memory address which is stored in t0
/* save hartid */
la t0, boot_hartid /* global varible rt_boot_hartid */
mv t1, a0 /* get hartid in S-mode frome a0 register */
sw t1, (t0) /* store t1 register low 4 bits in memory address which is stored in t0 */
# clear Interrupt Registers
csrw sie, 0
csrw sip, 0
# set Trap Vector Base Address Register
la t0, trap_entry
csrw stvec, t0
/* clear Interrupt Registers */
csrw sie, 0
csrw sip, 0
/* set Trap Vector Base Address Register */
la t0, trap_entry
csrw stvec, t0
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10,0
li x11,0
li x12,0
li x13,0
li x14,0
li x15,0
li x16,0
li x17,0
li x18,0
li x19,0
li x20,0
li x21,0
li x22,0
li x23,0
li x24,0
li x25,0
li x26,0
li x27,0
li x28,0
li x29,0
li x30,0
li x31,0
/* set to disable FPU */
li t0, SSTATUS_FS + SSTATUS_VS
csrc sstatus, t0
li t0, 0x40000 // SUM in sstatus
csrs sstatus, t0
/* set to disable FPU */
li t0, SSTATUS_FS + SSTATUS_VS
csrc sstatus, t0
li t0, SSTATUS_SUM
csrs sstatus, t0
.option push
.option norelax
la gp, __global_pointer$
la gp, __global_pointer$
.option pop
// removed SMP support here
la sp, __stack_start__
li t0, __STACKSIZE__
add sp, sp, t0
/* removed SMP support here */
la sp, __stack_start__
li t0, __STACKSIZE__
add sp, sp, t0
/**
* sscratch is always zero on kernel mode
*/
csrw sscratch, zero
call init_bss
call sbi_init
j primary_cpu_entry
/**
* sscratch is always zero on kernel mode
*/
csrw sscratch, zero
call init_bss
call sbi_init
j primary_cpu_entry
libcpu/risc-v/virt64/tlb.h
+5 -5
View File
@@ -10,14 +10,14 @@
#ifndef __TLB_H__
#define __TLB_H__
#include "mm_aspace.h"
#include "riscv_mmu.h"
#include "rtdbg.h"
#include "rtthread.h"
#include <sbi.h>
#include <stddef.h>
#include <stdint.h>
#include <rtthread.h>
#include <mm_aspace.h>
#include "sbi.h"
#include "riscv_mmu.h"
#define HANDLE_FAULT(ret) \
if (__builtin_expect((ret) != SBI_SUCCESS, 0)) \
LOG_W("%s failed", __FUNCTION__);
libcpu/risc-v/virt64/trap.c
+19 -35
View File
@@ -11,14 +11,15 @@
#include <rtthread.h>
#include <stdint.h>
#include <mm_fault.h>
#include "mmu.h"
#include "encoding.h"
#include "mm_fault.h"
#include "stack.h"
#include "sbi.h"
#include "riscv.h"
#include "tick.h"
#include "interrupt.h"
#include "plic.h"
#include "riscv_mmu.h"
#include "tick.h"
#ifdef RT_USING_SMART
#include <lwp_arch.h>
@@ -26,6 +27,10 @@
#define rt_hw_backtrace(...) (0)
#endif
#define DBG_TAG "libcpu.trap"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
void dump_regs(struct rt_hw_stack_frame *regs)
{
rt_kprintf("--------------Dump Registers-----------------\n");
@@ -64,17 +69,17 @@ void dump_regs(struct rt_hw_stack_frame *regs)
switch (__MASKVALUE(satp_v >> 60, __MASK(4)))
{
case 0:
mode_str = "No Address Translation/Protection Mode";
break;
case 0:
mode_str = "No Address Translation/Protection Mode";
break;
case 8:
mode_str = "Page-based 39-bit Virtual Addressing Mode";
break;
case 8:
mode_str = "Page-based 39-bit Virtual Addressing Mode";
break;
case 9:
mode_str = "Page-based 48-bit Virtual Addressing Mode";
break;
case 9:
mode_str = "Page-based 48-bit Virtual Addressing Mode";
break;
}
rt_kprintf("\tMode = %s\n", mode_str);
@@ -116,31 +121,8 @@ static const char *Interrupt_Name[] =
"Reserved-11",
};
enum
{
EP_INSTRUCTION_ADDRESS_MISALIGNED = 0,
EP_INSTRUCTION_ACCESS_FAULT,
EP_ILLEGAL_INSTRUCTION,
EP_BREAKPOINT,
EP_LOAD_ADDRESS_MISALIGNED,
EP_LOAD_ACCESS_FAULT,
EP_STORE_ADDRESS_MISALIGNED,
EP_STORE_ACCESS_FAULT,
EP_ENVIRONMENT_CALL_U_MODE,
EP_ENVIRONMENT_CALL_S_MODE,
EP_RESERVED10,
EP_ENVIRONMENT_CALL_M_MODE,
EP_INSTRUCTION_PAGE_FAULT, /* page attr */
EP_LOAD_PAGE_FAULT, /* read data */
EP_RESERVED14,
EP_STORE_PAGE_FAULT, /* write data */
};
extern struct rt_irq_desc irq_desc[];
#include "rtdbg.h"
#include "encoding.h"
#ifndef RT_USING_SMP
static volatile int nested = 0;
#define ENTER_TRAP \
@@ -242,6 +224,7 @@ void handle_user(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw
}
#endif
#ifdef ENABLE_VECTOR
static void vector_enable(struct rt_hw_stack_frame *sp)
{
sp->sstatus |= SSTATUS_VS_INITIAL;
@@ -276,6 +259,7 @@ static int illegal_inst_recoverable(rt_ubase_t stval, struct rt_hw_stack_frame *
return flag;
}
#endif
static void handle_nested_trap_panic(
rt_size_t cause,