[rt-smart] testcase & improvements for memory management (#7099)

* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format & modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch

libcpu/aarch64/common/cache.h

@@ -26,7 +26,6 @@ static inline void rt_hw_icache_invalidate_all(void)
     __asm_invalidate_icache_all();
 }
 
-void rt_hw_icache_invalidate_range(unsigned long start_addr, int size);
 void rt_hw_cpu_icache_invalidate(void *addr, rt_size_t size);
 void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, rt_size_t size);
 

libcpu/aarch64/common/trap.c

@@ -90,6 +90,7 @@ int check_user_stack(unsigned long esr, struct rt_hw_exp_stack *regs)
         break;
     case 0x21:
     case 0x24:
+    case 0x25:
         fault_op = MM_FAULT_OP_WRITE;
         fault_type = _get_type(esr);
         break;
@@ -101,12 +102,12 @@ int check_user_stack(unsigned long esr, struct rt_hw_exp_stack *regs)
     if (fault_op)
     {
         asm volatile("mrs %0, far_el1":"=r"(dfar));
-        struct rt_mm_fault_msg msg = {
+        struct rt_aspace_fault_msg msg = {
             .fault_op = fault_op,
             .fault_type = fault_type,
-            .vaddr = dfar,
+            .fault_vaddr = dfar,
         };
-        if (rt_mm_fault_try_fix(&msg))
+        if (rt_aspace_fault_try_fix(&msg))
         {
             ret = 1;
         }