[rt-smart] testcase & improvements for memory management (#7099)

* [utest/mm] add testcase for create/init
format codes of create/init in components/mm

* [libcpu/aarch64] fix user stack check routine

* [kservice] export API for utest

* [utest/mm] testcase for aspace_map
format & modify the files under components/mm related with aspace_map

* [lwp/user_mm] add user_map_varea for mmap feature

* [mm] rename rt_mm_fault_try_fix to rt_aspace_fault_try_fix

* [utest/mm] testcase for synchronization

* [mm] modify unmap api to improve throughput

* [utest/mm] testcases for cache and varea map

* [format] remove extra space

* [utest/mm] fix testcase problem in header

* [lwp] extend map_user_varea with a flag

* [utest/mm] testcase for lwp_map_user_varea

* [libcpu/arm/cortex-a] fix kernel space layout

* [utest/mm] adjust for armv7 arch

libcpu/aarch64/common/cache.h

@@ -26,7 +26,6 @@ static inline void rt_hw_icache_invalidate_all(void)
     __asm_invalidate_icache_all();
 }
 
-void rt_hw_icache_invalidate_range(unsigned long start_addr, int size);
 void rt_hw_cpu_icache_invalidate(void *addr, rt_size_t size);
 void rt_hw_cpu_dcache_clean_and_invalidate(void *addr, rt_size_t size);
 

libcpu/aarch64/common/trap.c

@@ -90,6 +90,7 @@ int check_user_stack(unsigned long esr, struct rt_hw_exp_stack *regs)
         break;
     case 0x21:
     case 0x24:
+    case 0x25:
         fault_op = MM_FAULT_OP_WRITE;
         fault_type = _get_type(esr);
         break;
@@ -101,12 +102,12 @@ int check_user_stack(unsigned long esr, struct rt_hw_exp_stack *regs)
     if (fault_op)
     {
         asm volatile("mrs %0, far_el1":"=r"(dfar));
-        struct rt_mm_fault_msg msg = {
+        struct rt_aspace_fault_msg msg = {
             .fault_op = fault_op,
             .fault_type = fault_type,
-            .vaddr = dfar,
+            .fault_vaddr = dfar,
         };
-        if (rt_mm_fault_try_fix(&msg))
+        if (rt_aspace_fault_try_fix(&msg))
         {
             ret = 1;
         }

libcpu/arm/cortex-a/mmu.c

@@ -11,6 +11,10 @@
 #include <rthw.h>
 #include <rtthread.h>
 
+#define DBG_TAG "hw.mmu"
+#define DBG_LVL DBG_LOG
+#include <rtdbg.h>
+
 #include <board.h>
 #include "cp15.h"
 #include "mm_page.h"
@@ -55,11 +59,26 @@ void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
 
 void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size)
 {
+    void *vaddr;
+    size_t length;
+    /* init kernel space */
+#ifdef RT_USING_SMART
+    rt_aspace_init(&rt_kernel_space, (void *)USER_VADDR_TOP, -USER_VADDR_TOP, (void *)MMUTable);
+#else
+    rt_aspace_init(&rt_kernel_space, (void *)0x1000, 0 - 0x1000, (void *)MMUTable);
+#endif /* RT_USING_SMART */
+
     /* set page table */
     for(; size > 0; size--)
     {
         if (mdesc->paddr_start == (rt_uint32_t)ARCH_MAP_FAILED)
             mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET;
+
+        vaddr = (void *)mdesc->vaddr_start;
+        length = mdesc->vaddr_end - mdesc->vaddr_start;
+        rt_aspace_map_static(&rt_kernel_space, &mdesc->varea, &vaddr, length,
+                             mdesc->attr, MMF_MAP_FIXED, &rt_mm_dummy_mapper, 0);
+
         rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
                 mdesc->paddr_start, mdesc->attr);
         mdesc++;
@@ -123,12 +142,10 @@ int rt_hw_mmu_map_init(struct rt_aspace *aspace, void* v_address, size_t size, s
     }
 
 #ifdef RT_USING_SMART
-    rt_aspace_init(&rt_kernel_space, (void *)USER_VADDR_TOP, 0 - USER_VADDR_TOP, vtable);
     rt_ioremap_start = v_address;
     rt_ioremap_size = size;
     rt_mpr_start = rt_ioremap_start - rt_mpr_size;
 #else
-    rt_aspace_init(&rt_kernel_space, (void *)0x1000, 0 - 0x1000, vtable);
     rt_mpr_start = (void *)0 - rt_mpr_size;
 #endif
 

libcpu/arm/cortex-a/mmu.h

@@ -52,6 +52,7 @@ struct mem_desc
     rt_uint32_t vaddr_end;
     rt_uint32_t paddr_start;
     rt_uint32_t attr;
+    struct rt_varea varea;
 };
 
 #define MMU_MAP_MTBL_XN       (1<<0)

libcpu/arm/cortex-a/trap.c

@@ -50,12 +50,12 @@ int check_user_stack(struct rt_hw_exp_stack *regs)
 
     if ((dfar >= (void *)USER_STACK_VSTART) && (dfar < (void *)USER_STACK_VEND))
     {
-        struct rt_mm_fault_msg msg = {
+        struct rt_aspace_fault_msg msg = {
             .fault_op = MM_FAULT_OP_WRITE,
             .fault_type = MM_FAULT_TYPE_PAGE_FAULT,
-            .vaddr = dfar,
+            .fault_vaddr = dfar,
         };
-        if (rt_mm_fault_try_fix(&msg))
+        if (rt_aspace_fault_try_fix(&msg))
         {
             regs->pc -= 8;
             return 1;

libcpu/risc-v/t-head/c906/trap.c

@@ -203,13 +203,13 @@ void handle_user(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw
 
     if (fault_op)
     {
-        struct rt_mm_fault_msg msg = {
+        struct rt_aspace_fault_msg msg = {
             .fault_op = fault_op,
             .fault_type = fault_type,
-            .vaddr = (void *)stval,
+            .fault_vaddr = (void *)stval,
         };
 
-        if (rt_mm_fault_try_fix(&msg))
+        if (rt_aspace_fault_try_fix(&msg))
         {
             return;
         }

libcpu/risc-v/virt64/cache.h

@@ -48,7 +48,7 @@ ALWAYS_INLINE void rt_hw_cpu_icache_invalidate_all_local() {}
 #define rt_hw_icache_invalidate_all rt_hw_cpu_icache_invalidate_all
 
 /** instruction barrier */
-void rt_hw_cpu_sync(void);
+static inline void rt_hw_cpu_sync(void) {}
 
 /**
  * @brief local cpu icahce & dcache synchronization

libcpu/risc-v/virt64/trap.c

@@ -200,13 +200,13 @@ void handle_user(rt_size_t scause, rt_size_t stval, rt_size_t sepc, struct rt_hw
 
     if (fault_op)
     {
-        struct rt_mm_fault_msg msg = {
+        struct rt_aspace_fault_msg msg = {
             .fault_op = fault_op,
             .fault_type = fault_type,
-            .vaddr = (void *)stval,
+            .fault_vaddr = (void *)stval,
         };
 
-        if (rt_mm_fault_try_fix(&msg))
+        if (rt_aspace_fault_try_fix(&msg))
         {
             return;
         }