mirror of
https://github.com/RT-Thread/rt-thread.git
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AT91SAM9260 branch
1. Support Keil MDK development environment 2. Modify EMAC driver according to the changes of lwIP API in reversion 1668 and 1669 git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1681 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
luohui2320@gmail.com
@@ -203,6 +203,10 @@ struct rt_hw_register
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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extern struct clk *clk_get(const char *id);
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extern rt_uint32_t clk_get_rate(struct clk *clk);
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extern void rt_hw_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,107 @@
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;/*
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; * File : context_rvds.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2011-08-14 weety copy from mini2440
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; */
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NOINT EQU 0xc0 ; disable interrupt in psr
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AREA |.text|, CODE, READONLY, ALIGN=2
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ARM
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REQUIRE8
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PRESERVE8
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;/*
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; * rt_base_t rt_hw_interrupt_disable();
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; */
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rt_hw_interrupt_disable PROC
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EXPORT rt_hw_interrupt_disable
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MRS r0, cpsr
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ORR r1, r0, #NOINT
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MSR cpsr_c, r1
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BX lr
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ENDP
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;/*
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; * void rt_hw_interrupt_enable(rt_base_t level);
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; */
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rt_hw_interrupt_enable PROC
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EXPORT rt_hw_interrupt_enable
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MSR cpsr_c, r0
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BX lr
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ENDP
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;/*
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; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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; * r0 --> from
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; * r1 --> to
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; */
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rt_hw_context_switch PROC
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EXPORT rt_hw_context_switch
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STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC)
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STMFD sp!, {r0-r12, lr} ; push lr & register file
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MRS r4, cpsr
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STMFD sp!, {r4} ; push cpsr
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MRS r4, spsr
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STMFD sp!, {r4} ; push spsr
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STR sp, [r0] ; store sp in preempted tasks TCB
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LDR sp, [r1] ; get new task stack pointer
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LDMFD sp!, {r4} ; pop new task spsr
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MSR spsr_cxsf, r4
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LDMFD sp!, {r4} ; pop new task cpsr
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MSR cpsr_cxsf, r4
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LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
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ENDP
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;/*
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; * void rt_hw_context_switch_to(rt_uint32 to);
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; * r0 --> to
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; */
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rt_hw_context_switch_to PROC
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EXPORT rt_hw_context_switch_to
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LDR sp, [r0] ; get new task stack pointer
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LDMFD sp!, {r4} ; pop new task spsr
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MSR spsr_cxsf, r4
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LDMFD sp!, {r4} ; pop new task cpsr
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MSR cpsr_cxsf, r4
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LDMFD sp!, {r0-r12, lr, pc} ; pop new task r0-r12, lr & pc
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ENDP
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;/*
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; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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; */
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IMPORT rt_thread_switch_interrput_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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rt_hw_context_switch_interrupt PROC
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EXPORT rt_hw_context_switch_interrupt
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LDR r2, =rt_thread_switch_interrput_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1 ; set rt_thread_switch_interrput_flag to 1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR r0, [r2]
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_reswitch
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LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR r1, [r2]
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BX lr
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ENDP
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END
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@@ -1,6 +1,7 @@
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#ifndef __GPIO_H__
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#define __GPIO_H__
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#include <rtthread.h>
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#include <at91_aic.h>
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#define PIN_BASE AIC_IRQS
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@@ -111,7 +112,7 @@
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#define AT91_PIN_PC31 (PIN_BASE + 0x40 + 31)
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static inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
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rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
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{
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return gpio;
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}
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@@ -76,6 +76,9 @@ static rt_uint32_t at91sam9260_default_irq_priority[MAX_HANDLERS] = {
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*/
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/*@{*/
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void rt_hw_interrupt_mask(int irq);
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void rt_hw_interrupt_umask(int irq);
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rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
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{
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rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
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@@ -102,7 +105,7 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector)
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irq_n = AIC_IRQS + 32*2;
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}
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else
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return;
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return RT_NULL;
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isr = at91_sys_read(pio+PIO_ISR) & at91_sys_read(pio+PIO_IMR);
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while (isr)
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{
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@@ -113,6 +116,8 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t vector)
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isr >>= 1;
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irq_n++;
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}
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return RT_NULL;
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}
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/*
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@@ -28,16 +28,16 @@
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#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
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static inline unsigned int at91_sys_read(unsigned int reg_offset)
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rt_inline unsigned int at91_sys_read(unsigned int reg_offset)
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{
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void *addr = (void *)AT91_BASE_SYS;
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unsigned int addr = AT91_BASE_SYS;
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return readl(addr + reg_offset);
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}
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static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
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rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
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{
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void *addr = (void *)AT91_BASE_SYS;
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unsigned int addr = AT91_BASE_SYS;
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writel(value, addr + reg_offset);
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}
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@@ -0,0 +1,315 @@
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;/*
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; * File : start_rvds.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2006, RT-Thread Development Team
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; *
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; * The license and distribution terms for this file may be
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; * found in the file LICENSE in this distribution or at
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; * http://www.rt-thread.org/license/LICENSE
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2011-08-14 weety first version
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; */
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; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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SVCMODE EQU 0x13
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MODEMASK EQU 0x1f
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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;----------------------- Stack and Heap Definitions ----------------------------
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;// <h> Stack Configuration (Stack Sizes in Bytes)
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;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
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;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
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;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
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;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
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;// </h>
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UND_Stack_Size EQU 512
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SVC_Stack_Size EQU 4096
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ABT_Stack_Size EQU 512
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FIQ_Stack_Size EQU 1024
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IRQ_Stack_Size EQU 1024
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USR_Stack_Size EQU 512
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ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size)
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE USR_Stack_Size
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__initial_sp SPACE ISR_Stack_Size
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Stack_Top
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;// <h> Heap Configuration
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;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
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;// </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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;----------------------- Memory Definitions ------------------------------------
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AT91_MATRIX_BASE EQU 0xffffee00
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AT91_MATRIX_MRCR EQU (AT91_MATRIX_BASE + 0x100)
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AT91_MATRIX_RCB0 EQU 0x00000001
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AT91_MATRIX_RCB1 EQU 0x00000002
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AT91_AIC_BASE EQU 0xfffff000
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AT91_AIC_IDCR EQU 0x124
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AT91_AIC_ICCR EQU 0x128
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;----------------------- CODE --------------------------------------------------
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PRESERVE8
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; Area Definition and Entry Point
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; Startup Code must be linked first at Address at which it expects to run.
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AREA RESET, CODE, READONLY
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ARM
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; Exception Vectors
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; Mapped to Address 0.
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; Absolute addressing mode must be used.
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; Dummy Handlers are implemented as infinite loops which can be modified.
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EXPORT Entry_Point
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Entry_Point
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Vectors LDR PC, Reset_Addr
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LDR PC, Undef_Addr
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LDR PC, SWI_Addr
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LDR PC, PAbt_Addr
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LDR PC, DAbt_Addr
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NOP
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LDR PC, IRQ_Addr
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LDR PC, FIQ_Addr
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Reset_Addr DCD Reset_Handler
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Undef_Addr DCD Undef_Handler
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SWI_Addr DCD SWI_Handler
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PAbt_Addr DCD PAbt_Handler
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DAbt_Addr DCD DAbt_Handler
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DCD 0 ; Reserved Address
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IRQ_Addr DCD IRQ_Handler
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FIQ_Addr DCD FIQ_Handler
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Undef_Handler B Undef_Handler
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SWI_Handler B SWI_Handler
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PAbt_Handler B PAbt_Handler
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;DAbt_Handler B DAbt_Handler
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FIQ_Handler B FIQ_Handler
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;*
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;*************************************************************************
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;*
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;* Interrupt handling
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;*
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;*************************************************************************
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;*
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; DAbt Handler
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DAbt_Handler
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IMPORT rt_hw_trap_dabt
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sub sp, sp, #72
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stmia sp, {r0 - r12} ;/* Calling r0-r12 */
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add r8, sp, #60
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stmdb r8, {sp, lr} ;/* Calling SP, LR */
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str lr, [r8, #0] ;/* Save calling PC */
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mrs r6, spsr
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str r6, [r8, #4] ;/* Save CPSR */
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str r0, [r8, #8] ;/* Save OLD_R0 */
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mov r0, sp
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bl rt_hw_trap_dabt
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;##########################################
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; Reset Handler
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EXPORT Reset_Handler
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Reset_Handler
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; set the cpu to SVC32 mode-----------------------------------------------------
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MRS R0,CPSR
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BIC R0,R0,#MODEMASK
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ORR R0,R0,#SVCMODE
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MSR CPSR_cxsf,R0
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LDR R1, =AT91_AIC_BASE
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LDR R0, =0xffffffff
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STR R0, [R1, #AT91_AIC_IDCR]
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STR R0, [R1, #AT91_AIC_ICCR]
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; remap internal ram to 0x00000000 address
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LDR R0, =AT91_MATRIX_MRCR
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LDR R1, =(AT91_MATRIX_RCB0|AT91_MATRIX_RCB1)
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STR R1, [R0]
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; Copy Exception Vectors to Internal RAM ---------------------------------------
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ADR R8, Vectors ; Source
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LDR R9, =0x00 ; Destination
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LDMIA R8!, {R0-R7} ; Load Vectors
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STMIA R9!, {R0-R7} ; Store Vectors
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LDMIA R8!, {R0-R7} ; Load Handler Addresses
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STMIA R9!, {R0-R7} ; Store Handler Addresses
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; Setup Stack for each mode ----------------------------------------------------
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LDR R0, =Stack_Top
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; Enter Undefined Instruction Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #UND_Stack_Size
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; Enter Abort Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #ABT_Stack_Size
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; Enter FIQ Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #FIQ_Stack_Size
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; Enter IRQ Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #IRQ_Stack_Size
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|
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; Enter Supervisor Mode and set its Stack Pointer
|
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MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
|
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MOV SP, R0
|
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SUB R0, R0, #SVC_Stack_Size
|
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|
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; Enter User Mode and set its Stack Pointer
|
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; MSR CPSR_c, #Mode_USR
|
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MOV SP, R0
|
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SUB SL, SP, #USR_Stack_Size
|
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|
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; Enter the C code -------------------------------------------------------------
|
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|
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IMPORT __main
|
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LDR R0, =__main
|
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BX R0
|
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|
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IMPORT rt_interrupt_enter
|
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IMPORT rt_interrupt_leave
|
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IMPORT rt_thread_switch_interrput_flag
|
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IMPORT rt_interrupt_from_thread
|
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IMPORT rt_interrupt_to_thread
|
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IMPORT rt_hw_trap_irq
|
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|
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IRQ_Handler PROC
|
||||
EXPORT IRQ_Handler
|
||||
STMFD sp!, {r0-r12,lr}
|
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BL rt_interrupt_enter
|
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BL rt_hw_trap_irq
|
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BL rt_interrupt_leave
|
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|
||||
; if rt_thread_switch_interrput_flag set, jump to
|
||||
; rt_hw_context_switch_interrupt_do and don't return
|
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LDR r0, =rt_thread_switch_interrput_flag
|
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LDR r1, [r0]
|
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CMP r1, #1
|
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BEQ rt_hw_context_switch_interrupt_do
|
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|
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LDMFD sp!, {r0-r12,lr}
|
||||
SUBS pc, lr, #4
|
||||
ENDP
|
||||
|
||||
; /*
|
||||
; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
|
||||
; */
|
||||
rt_hw_context_switch_interrupt_do PROC
|
||||
EXPORT rt_hw_context_switch_interrupt_do
|
||||
MOV r1, #0 ; clear flag
|
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STR r1, [r0]
|
||||
|
||||
LDMFD sp!, {r0-r12,lr}; reload saved registers
|
||||
STMFD sp!, {r0-r3} ; save r0-r3
|
||||
MOV r1, sp
|
||||
ADD sp, sp, #16 ; restore sp
|
||||
SUB r2, lr, #4 ; save old task's pc to r2
|
||||
|
||||
MRS r3, spsr ; get cpsr of interrupt thread
|
||||
|
||||
; switch to SVC mode and no interrupt
|
||||
MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
|
||||
|
||||
STMFD sp!, {r2} ; push old task's pc
|
||||
STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
|
||||
MOV r4, r1 ; Special optimised code below
|
||||
MOV r5, r3
|
||||
LDMFD r4!, {r0-r3}
|
||||
STMFD sp!, {r0-r3} ; push old task's r3-r0
|
||||
STMFD sp!, {r5} ; push old task's cpsr
|
||||
MRS r4, spsr
|
||||
STMFD sp!, {r4} ; push old task's spsr
|
||||
|
||||
LDR r4, =rt_interrupt_from_thread
|
||||
LDR r5, [r4]
|
||||
STR sp, [r5] ; store sp in preempted tasks's TCB
|
||||
|
||||
LDR r6, =rt_interrupt_to_thread
|
||||
LDR r6, [r6]
|
||||
LDR sp, [r6] ; get new task's stack pointer
|
||||
|
||||
LDMFD sp!, {r4} ; pop new task's spsr
|
||||
MSR spsr_cxsf, r4
|
||||
LDMFD sp!, {r4} ; pop new task's psr
|
||||
MSR cpsr_cxsf, r4
|
||||
|
||||
LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
|
||||
ENDP
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
; User Initial Stack & Heap
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + USR_Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
|
||||
@@ -26,34 +26,52 @@ struct clk {
|
||||
};
|
||||
|
||||
static struct clk clk32k = {
|
||||
.name = "clk32k",
|
||||
.rate_hz = AT91_SLOW_CLOCK,
|
||||
"clk32k",
|
||||
AT91_SLOW_CLOCK,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk main_clk = {
|
||||
.name = "main",
|
||||
"main",
|
||||
0,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk plla = {
|
||||
.name = "plla",
|
||||
"plla",
|
||||
0,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk mck = {
|
||||
.name = "mck",
|
||||
"mck",
|
||||
0,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk uhpck = {
|
||||
.name = "uhpck",
|
||||
"uhpck",
|
||||
0,
|
||||
RT_NULL,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk pllb = {
|
||||
.name = "pllb",
|
||||
.parent = &main_clk,
|
||||
"pllb",
|
||||
0,
|
||||
&main_clk,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk udpck = {
|
||||
.name = "udpck",
|
||||
.parent = &pllb,
|
||||
"udpck",
|
||||
0,
|
||||
&pllb,
|
||||
{RT_NULL, RT_NULL},
|
||||
};
|
||||
|
||||
static struct clk *const standard_pmc_clocks[] = {
|
||||
@@ -75,7 +93,7 @@ struct clk *clk_get(const char *id)
|
||||
for (list = (&clocks)->next; list != &clocks; list = list->next)
|
||||
{
|
||||
clk = (struct clk *)rt_list_entry(list, struct clk, node);
|
||||
if (strcmp(id, clk->name) == 0)
|
||||
if (rt_strcmp(id, clk->name) == 0)
|
||||
return clk;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user