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[bsp][synopsys] add the support of synopsys arc emsk

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* the initial support of synopsys designware arc processor
* the initial support of synospsy ARC EM Starter Kit
* the bsp code is based on embarc which is a common SDK for
all synopsys ARC-based boards
* use "scons --gdb" to debug emsk with em9d configuration
* for detailed board information, pls go embarc.org

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
This commit is contained in:
Wayne Ren
2019-01-25 10:29:34 +08:00
parent 99bef01983
commit d8aa99a29c
66 changed files with 15704 additions and 0 deletions
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bsp/synopsys/embarc/SConscript
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from building import *
cwd = GetCurrentDir()
embarc_arc_hal_SRCS = Split("""
arc/arc_cache.c
arc/arc_exc_asm.S
arc/arc_exception.c
arc/arc_timer.c
arc/startup/arc_cxx_support.c
arc/startup/arc_startup.S
device/designware/uart/dw_uart.c
device/designware/gpio/dw_gpio.c
""")
ASFLAGS = ' -I' + cwd
src = embarc_arc_hal_SRCS
path = [cwd,
cwd + '/arc',
cwd + '/arc/startup'
]
group = DefineGroup('embarc', src, depend = [], CPPPATH = path, ASFLAGS = ASFLAGS)
Return('group')
bsp/synopsys/embarc/arc/arc_cache.c
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bsp/synopsys/embarc/arc/arc_exc_asm.S
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bsp/synopsys/embarc/arc/arc_exception.c
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bsp/synopsys/embarc/arc/arc_timer.c
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bsp/synopsys/embarc/arc/startup/arc_cxx_support.c
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/*
* Copyright (c) 2012-2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* ------------------------------------------
* Copyright (c) 2015, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2016-03-02
* \author Wayne Ren(wei.ren@synopsys.com)
--------------------------------------------- */
#include "embARC_BSP_config.h"
#if defined(__GNU__)
/* embARC's GNU C++ support takes reference from Zephyr (cpp_xxx.c) */
/**
* @file - Constructor module
* @brief
* The ctors section contains a list of function pointers that execute the
* C++ constructors of static global objects. These must be executed before
* the application's main() routine.
*
* NOTE: Not all compilers put those function pointers into the ctors section;
* some put them into the init_array section instead.
*/
/* What a constructor function pointer looks like */
typedef void (*CtorFuncPtr)(void);
/* Constructor function pointer list is generated by the linker script. */
extern CtorFuncPtr __CTOR_LIST__[];
extern CtorFuncPtr __CTOR_END__[];
/**
*
* @brief Invoke all C++ style global object constructors
*
* This routine is invoked before the execution of the
* application's main().
*/
void __do_global_ctors_aux(void)
{
unsigned int nCtors;
nCtors = (unsigned int)__CTOR_LIST__[0];
while (nCtors >= 1) {
__CTOR_LIST__[nCtors--]();
}
}
typedef void (*DtorFuncPtr)(void);
extern DtorFuncPtr __DTOR_LIST__[];
extern DtorFuncPtr __DTOR_END__[];
/**
*
* @brief Invoke all C++ style global object destructors
*
* This routine is invoked after the execution of the
* application's main().
*/
void __do_global_dtors_aux(void)
{
unsigned int nDtors;
unsigned int i;
nDtors = (unsigned int)__DTOR_LIST__[0];
i = 0;
while (i <= nDtors) {
__DTOR_LIST__[i++]();
}
}
void *__dso_handle = 0;
/**
* @brief Register destructor for a global object
*
* @param destructor the global object destructor function
* @param objptr global object pointer
* @param dso Dynamic Shared Object handle for shared libraries
*
* Function does nothing at the moment, assuming the global objects
* do not need to be deleted
*
* @return N/A
*/
int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso)
{
return 0;
}
typedef void (*func_ptr)(void);
extern func_ptr __init_array_start[0];
extern func_ptr __init_array_end[0];
/**
* @brief Execute initialization routines referenced in .init_array section
*
* @return N/A
*/
void __do_init_array_aux(void)
{
for (func_ptr *func = __init_array_start;
func < __init_array_end;
func++) {
(*func)();
}
}
/**
* @brief Stub for pure virtual functions
*
* This routine is needed for linking C++ code that uses pure virtual
* functions.
*
* @return N/A
*/
void __cxa_pure_virtual(void)
{
while (1) {
;
}
}
#endif
bsp/synopsys/embarc/arc/startup/arc_startup.S
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bsp/synopsys/embarc/device/designware/gpio/dw_gpio.c
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bsp/synopsys/embarc/device/designware/gpio/dw_gpio.h
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/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-22
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \brief designware gpio driver
* \ingroup DEVICE_DW_GPIO
* \brief Designware GPIO driver header file
*/
#ifndef _DW_GPIO_H_
#define _DW_GPIO_H_
#include "device/device_hal/inc/dev_gpio.h"
#include "inc/arc/arc_exception.h"
#define DW_GPIO_PORT_A (0x00)
#define DW_GPIO_PORT_B (0x01)
#define DW_GPIO_PORT_C (0x02)
#define DW_GPIO_PORT_D (0x03)
#define DW_GPIO_INT_ACT_LOW GPIO_INT_ACTIVE_LOW
#define DW_GPIO_INT_ACT_HIGH GPIO_INT_ACTIVE_HIGH
#define DW_GPIO_INT_LEVEL_TRIG GPIO_INT_LEVEL_TRIG
#define DW_GPIO_INT_EDGE_TRIG GPIO_INT_EDGE_TRIG
#define DW_GPIO_INT_NO_DEBOUNCE GPIO_INT_NO_DEBOUNCE
#define DW_GPIO_INT_DEBOUNCE GPIO_INT_DEBOUNCE
#define DW_GPIO_ALL_ZERO (0x0)
#define DW_GPIO_ALL_ONE (0xffffffff)
#define DW_GPIO_MASK_ALL (0xffffffff)
#define DW_GPIO_INPUT_ALL (0x0)
#define DW_GPIO_OUTPUT_ALL (0xffffffff)
/**
* \name DesignWare GPIO Register Structure
* \brief contains definitions of DesignWare GPIO register structure.
* @{
*/
typedef struct port_ctrl {
uint32_t DR;
uint32_t DDR;
uint32_t CTRL;
} PORT_CTRL;
/* DW GPIO PORTS Registers */
typedef volatile struct dw_gpio_reg {
PORT_CTRL SWPORTS[4];
uint32_t INTEN; /*!< (0x30) */
uint32_t INTMASK; /*!< (0x34) */
uint32_t INTTYPE_LEVEL; /*!< (0x38) */
uint32_t INT_POLARITY; /*!< (0x3c) */
uint32_t INTSTATUS; /*!< (0x40) */
uint32_t RAW_INTSTATUS; /*!< (0x44) */
uint32_t DEBOUNCE; /*!< (0x48) */
uint32_t PORTA_EOI; /*!< (0x4c) */
uint32_t EXT_PORTS[4]; /*!< (0x50) -A
(0x54) -B
(0x58) -C
(0x5c) -D */
uint32_t LS_SYNC; /*!< (0x60) */
uint32_t ID_CODE; /*!< (0x64) */
uint32_t RESERVED_3; /*!< (0x68) */
uint32_t VER_ID_CODE; /*!< (0x6c) */
uint32_t CONFIG_REG2; /*!< (0x70) */
uint32_t CONFIG_REG1; /*!< (0x74) */
} DW_GPIO_REG, *DW_GPIO_REG_PTR;
/** @} */
/** interrupt handler for each port bit */
typedef struct dw_gpio_bit_isr {
uint32_t int_bit_max_cnt; /*!< max bit count for each port */
DEV_GPIO_HANDLER *int_bit_handler_ptr; /*!< interrupt handler pointer */
} DW_GPIO_BIT_ISR, * DW_GPIO_BIT_ISR_PTR;
/**
* \brief DesignWare GPIO control structure definition
* \details implement of dev_gpio_info::gpio_ctrl
*/
typedef struct dw_gpio_port {
uint32_t no; /*!< gpio port number */
DW_GPIO_REG_PTR regs; /*!< gpio port register */
uint32_t intno; /*!< gpio interrupt vector number */
uint32_t valid_bit_mask; /*!< valid bit mask of gpio port */
INT_HANDLER int_handler; /*!< gpio interrupt handler */
DW_GPIO_BIT_ISR_PTR gpio_bit_isr; /*!< gpio bit handler struct */
} DW_GPIO_PORT, *DW_GPIO_PORT_PTR;
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name DesignWare GPIO Function Declaration
* \brief contains declarations of designware gpio functions.
* \details This are only used in gpio object implementation source file
* @{
*/
extern int32_t dw_gpio_open(DEV_GPIO *gpio_obj, uint32_t dir);
extern int32_t dw_gpio_close(DEV_GPIO *gpio_obj);
extern int32_t dw_gpio_read(DEV_GPIO *gpio_obj, uint32_t *val, uint32_t mask);
extern int32_t dw_gpio_write(DEV_GPIO *gpio_obj, uint32_t val, uint32_t mask);
extern int32_t dw_gpio_control(DEV_GPIO *gpio_obj, uint32_t ctrl_cmd, void *param);
extern int32_t dw_gpio_isr_handler(DEV_GPIO *gpio_obj, void *ptr);
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* _DW_GPIO_H_ */
bsp/synopsys/embarc/device/designware/iic/dw_iic.c
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bsp/synopsys/embarc/device/designware/iic/dw_iic.h
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bsp/synopsys/embarc/device/designware/iic/dw_iic_hal.h
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/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-06-30
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup DEVICE_DW_IIC
* \brief DesignWare IIC driver hardware description related header file
* \details detailed hardware related definitions of DesignWare IIC driver
*/
#ifndef _DEVICE_DW_IIC_HAL_H_
#define _DEVICE_DW_IIC_HAL_H_
#include "device/designware/iic/dw_iic_hal_cfg.h"
/** Enable Designware IIC */
#define DW_IIC_ENABLE (1)
/** Disable Designware IIC */
#define DW_IIC_DISABLE (0)
/** Stop Condition issue after this byte */
#define IC_DATA_CMD_STOP (1 << 9)
/** Restart Condition issue after this byte */
#define IC_DATA_CMD_RESTART (1 << 10)
/** No Restart or stop condition after this byte */
#define IC_DATA_CMD_NONE (0)
/** Perform a write request */
#define IC_DATA_CMD_WRITE_REQ (0)
/** Perform a read request */
#define IC_DATA_CMD_READ_REQ (1 << 8)
/** Fields of IC_CON register */
/* DW_APB I2C IP Config Dependencies. */
#if DW_IIC_ALLOW_RESTART
#define IC_CON_RESTART_EN (1 << 5)
#else
#define IC_CON_RESTART_EN (0x00)
#endif
/* Master Addressing Mode Config */
#if DW_IIC_MST_10_BIT_ADDR_SUPPORT
#define MST_10_BIT_ADDR_MODE (1 << 4)
#define IC_10BITADDR_MASTER (1 << 12)
#else
#define MST_10_BIT_ADDR_MODE (0x00)
#define IC_10BITADDR_MASTER (0x00)
#endif
/* Slave Addressing Mode Config */
#if DW_IIC_SLV_10_BIT_ADDR_SUPPORT
#define SLV_10_BIT_ADDR_MODE (1 << 3)
#else
#define SLV_10_BIT_ADDR_MODE (0x00)
#endif
#if DW_IIC_SPECIAL_START_BYTE
#define IC_TAR_SPECIAL (1 << 11)
#define IC_TAR_GC_OR_START (1 << 10)
#else
#define IC_TAR_SPECIAL (0x00)
#define IC_TAR_GC_OR_START (0x00)
#endif
/** 7bit IIC address mask for target address register */
#define IC_TAR_7BIT_ADDR_MASK (0x7F)
/** 7bit IIC address mask for slave address register */
#define IC_SAR_7BIT_ADDR_MASK (0x7F)
/** 10bit IIC address mask for target address register */
#define IC_TAR_10BIT_ADDR_MASK (0x3FF)
/** 10bit IIC address mask for slave address register */
#define IC_SAR_10BIT_ADDR_MASK (0x3FF)
/** Speed modes of IC_CON */
#define IC_CON_SPEED_MASK (0x6)
#define IC_CON_SPEED_STANDARD (0x2)
#define IC_CON_SPEED_FAST (0x4)
#define IC_CON_SPEED_HIGH (0x6)
/** Working mode of IC_CON */
#define IC_CON_MST_SLV_MODE_MASK (0x41)
#define IC_CON_ENA_MASTER_MODE (0x41)
#define IC_CON_ENA_SLAVE_MODE (0)
/* IIC interrupt control */
#define IC_INT_DISABLE_ALL (0x0)
#define IC_INT_ENABLE_ALL (0x7FF)
/* Interrupt Register Fields */
#define IC_INTR_STAT_GEN_CALL (1 << 11)
#define IC_INTR_STAT_START_DET (1 << 10)
#define IC_INTR_STAT_STOP_DET (1 << 9)
#define IC_INTR_STAT_ACTIVITY (1 << 8)
#define IC_INTR_STAT_RX_DONE (1 << 7)
#define IC_INTR_STAT_TX_ABRT (1 << 6)
#define IC_INTR_STAT_RD_REQ (1 << 5)
#define IC_INTR_STAT_TX_EMPTY (1 << 4)
#define IC_INTR_STAT_TX_OVER (1 << 3)
#define IC_INTR_STAT_RX_FULL (1 << 2)
#define IC_INTR_STAT_RX_OVER (1 << 1)
#define IC_INTR_STAT_RX_UNDER (1 << 0)
/* Interrupt enable mask as master */
#define IC_INT_MST_TX_ENABLE (IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_TX_OVER|IC_INTR_STAT_TX_ABRT)
#define IC_INT_MST_RX_ENABLE (IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER|IC_INTR_STAT_TX_ABRT)
/* Interrupt enable mask as master */
#define IC_INT_SLV_COMMON_ENABLE (IC_INTR_STAT_START_DET|IC_INTR_STAT_STOP_DET)
#define IC_INT_SLV_TX_ENABLE (IC_INTR_STAT_RD_REQ|IC_INTR_STAT_TX_ABRT)
#define IC_INT_SLV_RX_ENABLE (IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)
/* IC_ENABLE_STATUS Bits */
#define IC_ENABLE_STATUS_IC_EN (1 << 0)
#define IC_ENABLE_STATUS_SLV_DIS (1 << 1)
#define IC_ENABLE_STATUS_SLV_RX_LOST (1 << 2)
/* IIC TX & RX threshold settings */
#define IIC_TX_THRESHOLD (0)
#define IIC_RX_THRESHOLD (0)
/* DW_APB IIC (DW_IC_STATUS) Status Register Fields. */
#define IC_STATUS_ACTIVITY (0x01)
#define IC_STATUS_TFNF (0x02) /* (1 << 1) */
#define IC_STATUS_TFE (0x04) /* (1 << 2) */
#define IC_STATUS_RFNE (0x08) /* (1 << 3) */
#define IC_STATUS_RFF (0x10) /* (1 << 4) */
#define IC_STATUS_MASTER_ACT (0x20) /* (1 << 5) */
#define IC_STATUS_SLAVE_ACT (0x40) /* (1 << 6) */
/* IC_TX_ABRT_SOURCE Register Bit Fields */
#define IC_TX_ABRT_7B_ADDR_NOACK (1 << 0)
#define IC_TX_ABRT_10ADDR1_NOACK (1 << 1)
#define IC_TX_ABRT_10ADDR2_NOACK (1 << 2)
#define IC_TX_ABRT_TXDATA_NOACK (1 << 3)
#define IC_TX_ABRT_GCALL_NOACK (1 << 4)
#define IC_TX_ABRT_GCALL_READ (1 << 5)
#define IC_TX_ABRT_HS_ACKDET (1 << 6)
#define IC_TX_ABRT_SBYTE_ACKDET (1 << 7)
#define IC_TX_ABRT_HS_NORSTRT (1 << 8)
#define IC_TX_ABRT_SBYTE_NORSTRT (1 << 9)
#define IC_TX_ABRT_10B_RD_NORSTRT (1 << 10)
#define IC_TX_ABRT_MASTER_DIS (1 << 11)
#define IC_TX_ABRT_ARB_LOST (1 << 12)
#define IC_TX_ABRT_SLVFLUSH_TXFIFO (1 << 13)
#define IC_TX_ABRT_SLV_ARBLOST (1 << 14)
#define IC_TX_ABRT_SLVRD_INTX (1 << 15)
/* Combined bits for iic abort source as master */
#define IIC_MST_ABRT_ADDR_NOACK (IC_TX_ABRT_7B_ADDR_NOACK|IC_TX_ABRT_10ADDR1_NOACK|IC_TX_ABRT_10ADDR1_NOACK)
#define IIC_MST_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST)
#define IIC_MST_ABRT_DATA_NOACK (IC_TX_ABRT_TXDATA_NOACK)
/* Combined bits for iic abort source as slave */
#define IIC_SLV_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST|IC_TX_ABRT_SLV_ARBLOST)
/** @} */
#endif /* _DEVICE_DW_IIC_HAL_H_ */
bsp/synopsys/embarc/device/designware/iic/dw_iic_hal_cfg.h
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/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-07-01
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup DEVICE_DW_IIC
* \brief DesignWare IIC driver hardware description
* related header file configuration file
* \details configuration file to enable or disable some function of iic
*/
#ifndef _DEVICE_DW_IIC_HAL_CFG_H_
#define _DEVICE_DW_IIC_HAL_CFG_H_
#ifndef DW_IIC_ALLOW_RESTART
#define DW_IIC_ALLOW_RESTART (1) /*!< allow restart configuration */
#endif
#ifdef DW_IIC_SPECIAL_START_BYTE
#define DW_IIC_SPECIAL_START_BYTE (0) /*!< SPECIAL bit enable in IC_TAR */
#endif
#ifndef DW_IIC_MST_10_BIT_ADDR_SUPPORT
#define DW_IIC_MST_10_BIT_ADDR_SUPPORT (1) /*!< enable 10-bit address mode */
#endif
#ifdef DW_IIC_SLV_10_BIT_ADDR_SUPPORT
#define DW_IIC_SLV_10_BIT_ADDR_SUPPORT (1) /*!< slave 10-bit addressing mode */
#endif
#ifndef DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT
#define DW_IIC_DYNAMIC_TAR_UPDATE_SUPPORT (0) /*!< Dynamic target address update support */
#endif
#ifndef DW_IIC_DISABLE_MAX_T_POLL_CNT
#define DW_IIC_DISABLE_MAX_T_POLL_CNT (1250) /*!< Timeout count, approximate to be 25us in 50MHz CPU @ Standard mode */
#endif
#ifndef DW_IIC_CALC_FIFO_LEN_ENABLE
#define DW_IIC_CALC_FIFO_LEN_ENABLE (1) /*!< Default enable calculate fifo length */
#endif
#ifndef DW_IIC_USE_IC_CLK_MHZ
#define DW_IIC_USE_IC_CLK_MHZ (50) /*!< Default use 50MHz IC_CLK */
#endif
#ifndef DW_IIC_USE_HS_BUS_LOADING_100PF
#define DW_IIC_USE_HS_BUS_LOADING_100PF (1) /*!< Use bus loading 100pf */
#endif
#endif /* _DEVICE_DW_IIC_HAL_CFG_H_ */
bsp/synopsys/embarc/device/designware/spi/dw_spi.c
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bsp/synopsys/embarc/device/designware/spi/dw_spi.h
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/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-06-25
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \brief DesignWare SPI driver header file
* \ingroup DEVICE_DW_SPI
*/
#ifndef _DEVICE_DW_SPI_H_
#define _DEVICE_DW_SPI_H_
#include "device/device_hal/inc/dev_spi.h"
/**
* if this header file is included,
* will indicate that this designware spi device
* is used
*/
#define DEVICE_USE_DESIGNWARE_SPI
#define DW_SPI_IN_FREE (0) /*!< Currently not in spi transfer */
#define DW_SPI_IN_XFER (DEV_IN_TX|DEV_IN_RX|DEV_IN_XFER) /*!< Currently in spi transfer */
#define DW_SPI_IN_TX (DEV_IN_TX|DEV_IN_XFER) /*!< Currently in spi tx */
#define DW_SPI_IN_RX (DEV_IN_RX|DEV_IN_XFER) /*!< Currently in spi rx */
#define DW_SPI_GINT_DISABLED (0) /*!< designware interrupt disabled for control iic irq/fiq */
#define DW_SPI_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control iic irq/fiq */
#define DW_SPI_MASTER_SUPPORTED (0x1) /*!< Support Designware SPI Master Mode */
#define DW_SPI_SLAVE_SUPPORTED (0x2) /*!< Support Designware SPI Slave Mode */
/*!< Support Designware SPI Both Master and Slave Mode */
#define DW_SPI_BOTH_SUPPORTED (DW_SPI_MASTER_SUPPORTED|DW_SPI_SLAVE_SUPPORTED)
/**
* \defgroup DEVICE_DW_SPI_REGSTRUCT DesignWare SPI Register Structure
* \ingroup DEVICE_DW_SPI
* \brief contains definitions of DesignWare SPI register structure.
* \details detailed description of DesignWare SPI register information
* @{
*/
/**
* \brief DesignWare SPI register structure
* \details Detailed struct description of DesignWare SPI
* block register information, implementation of dev_spi_info::spi_regs
*/
typedef volatile struct dw_spi_reg
{
/*!< Control Register */
/*!< SPI Control Register 0 (0x0) */
uint32_t CTRLR0;
/*!< SPI Control Register 1 (0x4) */
uint32_t CTRLR1;
/*!< Enable Register */
/*!< SPI Enable Register (0x8) */
uint32_t SSIENR;
/*!< SPI Microwire Control Register (0xC) */
uint32_t MWCR;
/*!< SPI Slave Enable Register (0x10) */
uint32_t SER;
/*!< SPI Baud Rate Select Register (0x14) */
uint32_t BAUDR;
/*!< TX and RX FIFO Control Register */
/*!< SPI Transmit FIFO Threshold Level Register (0x18) */
uint32_t TXFTLR;
/*!< SPI Receive FIFO Threshold Level Register (0x1C) */
uint32_t RXFTLR;
/*!< SPI Transmit FIFO Level Register (0x20) */
uint32_t TXFLR;
/*!< SPI Receive FIFO Level Register (0x24) */
uint32_t RXFLR;
/*!< SPI Status Register (0x28) */
uint32_t SR;
/*!< Interrupt Enable/Disable/Control Registers */
/*!< SPI Interrupt Mask Register (0x2C) */
uint32_t IMR;
/*!< SPI Interrupt Status Register (0x30) */
uint32_t ISR;
/*!< SPI Raw Interrupt Status Register (0x34) */
uint32_t RISR;
/*!< SPI Transmit FIFO Overflow Interrupt Clear Register (0x38) */
uint32_t TXOICR;
/*!< SPI Receive FIFO Overflow Interrupt Clear Register (0x3C) */
uint32_t RXOICR;
/*!< SPI Receive FIFO Underflow Interrupt Clear Register (0x40) */
uint32_t RXUICR;
/*!< SPI Multi-Master Interrupt Clear Register (0x44) */
uint32_t MSTICR;
/*!< SPI Interrupt Clear Register (0x48) */
uint32_t ICR;
/*!< DMA Control Register (0x4C) */
uint32_t DMACR;
/*!< DMA Transmit Data Level (0x50) */
uint32_t DMATDLR;
/*!< DMA Receive Data Level (0x54) */
uint32_t DMARDLR;
/*!< SPI Identification Register (0x58) */
uint32_t IDR;
/*!< SPI CoreKit ID Register (Value after Reset : 0x3332322A) (0x5C) */
uint32_t SSI_VER_ID;
/*!< Data Register */
/*!< SPI DATA Register for both Read and Write (0x60) */
uint32_t DATAREG;
} DW_SPI_REG, *DW_SPI_REG_PTR;
/** @} */
/** Designware SPI Message Transfer */
typedef struct dw_spi_transfer {
uint32_t xfer_len;
uint32_t tx_idx;
uint32_t rx_idx;
uint32_t nbytes;
DEV_SPI_TRANSFER *tx_xfer;
DEV_SPI_TRANSFER *rx_xfer;
} DW_SPI_TRANSFER, *DW_SPI_TRANSFER_PTR;
/**
* \brief DesignWare SPI control structure definition
* \details implement of dev_spi_info::dev_spi_info
*/
typedef struct dw_spi_ctrl {
DW_SPI_REG *dw_spi_regs; /*!< spi register */
/* Variables which should be set during object implementation */
uint32_t support_modes; /*!< supported spi modes */
uint32_t intno; /*!< interrupt no */
uint32_t dw_apb_bus_freq; /*!< spi ip apb bus frequency */
uint32_t tx_fifo_len; /*!< transmit fifo length */
uint32_t rx_fifo_len; /*!< receive fifo length */
INT_HANDLER dw_spi_int_handler; /*!< spi interrupt handler */
/* Variables which always change during iic operation */
uint32_t int_status; /*!< iic interrupt status */
DW_SPI_TRANSFER dw_xfer; /*!< designware spi transfer */
} DW_SPI_CTRL, *DW_SPI_CTRL_PTR;
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup DEVICE_DW_SPI_FUNCDLR DesignWare SPI Function Declaration
* \ingroup DEVICE_DW_SPI
* \brief contains declarations of designware spi functions.
* \details This are only used in \ref dw_spi_obj.c
* @{
*/
extern int32_t dw_spi_open (DEV_SPI *spi_obj, uint32_t mode, uint32_t param);
extern int32_t dw_spi_close (DEV_SPI *spi_obj);
extern int32_t dw_spi_control (DEV_SPI *spi_obj, uint32_t ctrl_cmd, void *param);
extern int32_t dw_spi_write (DEV_SPI *spi_obj, const void *data, uint32_t len);
extern int32_t dw_spi_read (DEV_SPI *spi_obj, void *data, uint32_t len);
extern void dw_spi_isr(DEV_SPI *spi_obj, void *ptr);
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* _DEVICE_DW_SPI_H_ */
bsp/synopsys/embarc/device/designware/spi/dw_spi_hal.h
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/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-06-25
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup DEVICE_DW_SPI
* \brief DesignWare SPI driver hardware description related header file
* \details detailed hardware related definitions of DesignWare SPI driver
*/
#ifndef _DEVICE_DW_SPI_HAL_H_
#define _DEVICE_DW_SPI_HAL_H_
#include "device/designware/spi/dw_spi_hal_cfg.h"
/* DW APB SPI bit definitions */
/**
* \name DesignWare SPI HAL CTRL0 Macros
* \brief DesignWare SPI hal ctrl0 macros,
* include dfs, scph, scppl, tmod, etc
* @{
*/
#define DW_SPI_CTRLR0_DFS_MASK (0xf)
#define DW_SPI_CTRLR0_SC_OFS (6)
#define DW_SPI_CTRLR0_SC_MASK (0xC0)
#define DW_SPI_CTRLR0_SCPH_HIGH (0x40)
#define DW_SPI_CTRLR0_SCPH_LOW (0)
#define DW_SPI_CTRLR0_SCPOL_HIGH (0x80)
#define DW_SPI_CTRLR0_SCPOL_LOW (0)
#define DW_SPI_CTRLR0_TMOD_MASK (0x300)
#define DW_SPI_TMOD_TRANSMIT_RECEIVE (0)
#define DW_SPI_TMOD_TRANSMIT_ONLY (0x100)
#define DW_SPI_TMOD_RECEIVE_ONLY (0x200)
#define DW_SPI_TMOD_EEPROM_READ_ONLY (0x300)
#define DW_SPI_CTRLR0_FRF_MOTOROLA (0x0)
#define DW_SPI_CTRLR0_FRF_TI (0x10)
#define DW_SPI_CTRLR0_FRF_MICROWIRE (0x20)
#define DW_SPI_CTRLR0_SLV_OE_DISABLE (1<<10)
#define DW_SPI_CTRLR0_SLV_OE_ENABLE (0)
/** @} */
/**
* \name DesignWare SPI HAL ISR Flags
* \brief DesignWare SPI hal Interrupt Status Flags
* @{
*/
#define DW_SPI_TX_OVERFLOW_ERROR (0x2)
#define DW_SPI_RX_UNDERFLOW_ERROR (0x4)
#define DW_SPI_RX_OVERFLOW_ERROR (0x8)
#define DW_SPI_ISR_RX_FIFO_INT_MASK (0x10)
#define DW_SPI_ISR_TX_FIFO_INT_MASK (0x1)
#define DW_SPI_ISR_TX_OVERFLOW_INT_MASK (0x2)
#define DW_SPI_ISR_RX_UNDERFLOW_INT_MASK (0x4)
#define DW_SPI_ISR_RX_OVERFLOW_INT_MASK (0x8)
/** @} */
/**
* \name DesignWare SPI HAL SR Flags
* \brief DesignWare SPI hal Status Flags
* @{
*/
#define DW_SPI_SR_DCOL (0x40)
#define DW_SPI_SR_TXE (0x20)
#define DW_SPI_SR_RFF (0x10)
#define DW_SPI_SR_RFNE (0x8)
#define DW_SPI_SR_TFE (0x4)
#define DW_SPI_SR_TFNF (0x2)
#define DW_SPI_SR_BUSY (0x1)
/** @} */
/**
* \name DesignWare SPI HAL SSI Enable Macros
* \brief DesignWare SPI hal ssi enable macros
* @{
*/
/* Macros */
#define DW_SPI_SSI_ENABLE (1) /*!< SSI Enable */
#define DW_SPI_SSI_DISABLE (0) /*!< SSI Disable */
/** @} */
/**
* \name DesignWare SPI HAL IMR Macros
* \brief DesignWare SPI hal interrupt mask macros
* @{
*/
#define DW_SPI_IMR_MSTIM (0x20) /*!< Multi-Master Contention Interrupt Mask */
#define DW_SPI_IMR_RXFIM (0x10) /*!< Receive FIFO Full Interrupt Mask */
#define DW_SPI_IMR_RXOIM (0x08) /*!< Receive FIFO Overflow Interrupt Mask */
#define DW_SPI_IMR_RXUIM (0x04) /*!< Receive FIFO Underflow Interrupt Mask */
#define DW_SPI_IMR_TXOIM (0x02) /*!< Transmit FIFO Overflow Interrupt Mask */
#define DW_SPI_IMR_TXEIM (0x01) /*!< Transmit FIFO Empty Interrupt Mask */
#define DW_SPI_IMR_XFER (DW_SPI_IMR_TXEIM|DW_SPI_IMR_RXFIM|DW_SPI_IMR_TXOIM|DW_SPI_IMR_RXOIM|DW_SPI_IMR_RXUIM)
/** @} */
#define DW_SPI_SSI_IDLE (1)
#define DW_SPI_SPI_TRANSMIT (1)
#define DW_SPI_SPI_RECEIVE (2)
#define DW_SPI_SSI_MASTER (1)
#define DW_SPI_SSI_SLAVE (0)
#endif /* _DEVICE_DW_SPI_HAL_H_ */
bsp/synopsys/embarc/device/designware/spi/dw_spi_hal_cfg.h
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/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2015-09-09
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup DEVICE_DW_SPI
* \brief DesignWare SPI driver hardware description
* related header file configuration file
* \details configuration file to enable or disable some function of spi
*/
#ifndef _DEVICE_DW_SPI_HAL_CFG_H_
#define _DEVICE_DW_SPI_HAL_CFG_H_
#ifndef DW_SPI_CALC_FIFO_LEN_ENABLE
#define DW_SPI_CALC_FIFO_LEN_ENABLE (1) /*!< Defaultly enable calculate fifo length */
#endif
#ifndef DW_SPI_MAX_FIFO_LENGTH
#define DW_SPI_MAX_FIFO_LENGTH (256) /*!< Max FIFO depth for designware SPI device */
#endif
#ifndef DW_SPI_MIN_FIFO_LENGTH
#define DW_SPI_MIN_FIFO_LENGTH (2) /*!< Min FIFO depth for designware SPI device */
#endif
#endif /* _DEVICE_DW_SPI_HAL_CFG_H_ */
bsp/synopsys/embarc/device/designware/uart/dw_uart.c
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bsp/synopsys/embarc/device/designware/uart/dw_uart.h
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/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-06-20
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup DEVICE_DW_UART
* \brief DesignWare UART driver header file
* \details detailed definitions of designware uart driver
*/
#ifndef _DW_UART_H_
#define _DW_UART_H_
#include "device/device_hal/inc/dev_uart.h"
#include "inc/arc/arc_exception.h"
/**
* if this header file is included,
* will indicate that this designware uart device
* is used
*/
#define DEVICE_USE_DESIGNWARE_UART
/**
* \name DesignWare UART Register Structure
* \brief contains definitions of DesignWare UART register structure.
* @{
*/
/**
* \brief DesignWare UART register structure
* \details Detailed struct description of DesignWare UART
* block register information, implementation of dev_uart_info::uart_regs
*/
typedef volatile struct dw_uart_reg {
uint32_t DATA; /*!< data in/out and DLL */
uint32_t IER; /*!< Interrupt enable register and DLH */
uint32_t IIR; /*!< Interrupt Id register and FCR */
uint32_t LCR; /*!< Line control Register */
uint32_t MCR; /*!< Modem control register */
uint32_t LSR; /*!< Line Status Register */
uint32_t MSR; /*!< Modem status Register */
uint32_t SCRATCHPAD; /*!< Uart scratch pad register */
uint32_t LPDLL; /*!< Low Power Divisor Latch (Low) Reg */
uint32_t LPDLH; /*!< Low Power Divisor Latch (High) Reg */
uint32_t RES1[2]; /*!< Reserved */
uint32_t SHR[16]; /*!< Shadow data register(SRBR and STHR) */
uint32_t FAR; /*!< FIFO Access register */
uint32_t TFR; /*!< Transmit FIFO Read */
uint32_t RFW; /*!< Receive FIFO write */
uint32_t USR; /*!< UART status register */
uint32_t TFL; /*!< Transmit FIFO level */
uint32_t RFL; /*!< Receive FIFO level */
uint32_t SRR; /*!< Software reset register */
uint32_t SRTS; /*!< Shadow request to send */
uint32_t SBCR; /*!< Shadow break control */
uint32_t SDMAM; /*!< Shadow DMA mode */
uint32_t SFE; /*!< Shadow FIFO enable */
uint32_t SRT; /*!< Shadow RCVR Trigger */
uint32_t STET; /*!< Shadow TX empty register */
uint32_t HTX; /*!< Halt TX */
uint32_t DMASA; /*!< DMA Software ACK */
uint32_t RES2[18]; /*!< Reserved */
uint32_t CPR; /*!< Camponent parameter register */
uint32_t UCV; /*!< UART Component Version */
uint32_t CTR; /*!< Component typw register */
} DW_UART_REG, *DW_UART_REG_PTR;
/** @} */
#define DW_UART_GINT_DISABLED (0) /*!< designware interrupt disabled for control uart irq/fiq */
#define DW_UART_GINT_ENABLE (1<<0) /*!< designware interrupt enabled for control uart irq/fiq */
#define DW_UART_TXINT_ENABLE (1<<1) /*!< designware interrupt enabled for control transmit process */
#define DW_UART_RXINT_ENABLE (1<<2) /*!< designware interrupt enabled for control transmit process */
/**
* \brief DesignWare UART control structure definition
* \details implement of dev_uart_info::uart_ctrl
*/
typedef struct dw_uart_ctrl {
uint32_t dw_uart_regbase; /*!< uart ip register base */
uint32_t dw_apb_bus_freq; /*!< uart ip apb bus frequency */
uint32_t intno; /*!< uart interrupt vector number */
INT_HANDLER dw_uart_int_handler; /*!< uart interrupt handler */
uint32_t tx_fifo_len; /*!< transmit fifo length, set by user in object implementation */
uint32_t rx_fifo_len; /*!< receive fifo length, set by user in object implementation */
uint32_t int_status; /*!< interrupt status for designware uart */
} DW_UART_CTRL, *DW_UART_CTRL_PTR;
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name DesignWare UART Function Declaration
* \brief contains declarations of designware uart functions.
* \details This are only used in uart object implementation source file
* @{
*/
extern int32_t dw_uart_open (DEV_UART *uart_obj, uint32_t baud);
extern int32_t dw_uart_close (DEV_UART *uart_obj);
extern int32_t dw_uart_control (DEV_UART *uart_obj, uint32_t ctrl_cmd, void *param);
extern int32_t dw_uart_write (DEV_UART *uart_obj, const void *data, uint32_t len);
extern int32_t dw_uart_read (DEV_UART *uart_obj, void *data, uint32_t len);
extern void dw_uart_isr(DEV_UART *uart_obj, void *ptr);
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* _DW_UART_H_ */
bsp/synopsys/embarc/device/designware/uart/dw_uart_hal.h
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bsp/synopsys/embarc/device/device_hal/inc/dev_common.h
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/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-06-16
* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
--------------------------------------------- */
/**
* \defgroup DEVICE_HAL_COMMON Common Device Layer Definitions
* \ingroup DEVICE_HAL_DEF
* \brief common definitions for device layer (\ref dev_common.h)
*
* @{
*
* \file
* \brief header file to define common definitions for device layer
* \details Here in this file provide definitions that need by other
* devices in device layer
*/
#ifndef _DEVICE_HAL_COMMON_H_
#define _DEVICE_HAL_COMMON_H_
#include <stdint.h>
/**
* \defgroup DEVICE_HAL_COMMON_DEVSTATE Common Device State
* \ingroup DEVICE_HAL_COMMON
* \brief definitions for device state
* \details here defines macros for device open/close,
* device working good/error, used in
* \ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
* \ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO
* @{
*/
/*
* macros for device open and close state
*/
#define DEV_CLOSED (0) /*!< Indicate that device was closed */
#define DEV_OPENED (1) /*!< Indicate that the device was opened */
/*
* macros for device good and error state
*/
#define DEV_GOOD (0) /*!< Indicate device is good */
#define DEV_ERROR (1) /*!< Indicate device error */
/** @} */
/**
* \defgroup DEVICE_HAL_COMMON_DEVMTHD Common Device Working Method
* \ingroup DEVICE_HAL_COMMON
* \brief definitions for device working method(interrupt or poll)
* \details here defines macros for working method,
* interrupt or poll method,used in
* \ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
* \ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO
* @{
*/
/*
* macros for device working method
*/
#define DEV_POLL_METHOD (0) /*!< Indicate that the device running in poll method */
#define DEV_INTERRUPT_METHOD (1) /*!< Indicate that the device running in interrupt method */
/** @} */
/**
* \defgroup DEVICE_HAL_COMMON_DEVMODE Common Device Working Mode
* \ingroup DEVICE_HAL_COMMON
* \brief definitions for device working mode(master or slave)
* \details here defines macros for working mode,
* Master or Slave mode,used in
* \ref DEV_HAL_IIC, \ref DEV_HAL_SPI.
* @{
*/
/*
* macros for device working mode
*/
#define DEV_MASTER_MODE (0) /*!< Indicate that the device working as master */
#define DEV_SLAVE_MODE (1) /*!< Indicate that the device working as slave */
/** @} */
/**
* \defgroup DEVICE_HAL_COMMON_DEVSTATUS Common Device Status
* \ingroup DEVICE_HAL_COMMON
* \brief definitions for device status, 1 bit for 1 function
* @{
*/
#define DEV_DISABLED (0) /*!< Bit 0 for device enabled state, disabled */
#define DEV_ENABLED (1<<0) /*!< Bit 0 for device enabled state, enabled */
#define DEV_IN_TX (1<<1) /*!< Bit 1 for device in transmit state */
#define DEV_IN_RX (1<<2) /*!< Bit 2 for device in receive state */
#define DEV_IN_XFER (1<<3) /*!< Bit 3 for device in transfer state */
#define DEV_IN_TX_ABRT (1<<4) /*!< Bit 4 for device in transmit abort state */
#define DEV_IN_RX_ABRT (1<<5) /*!< Bit 5 for device in receive abort state */
#define DEV_IN_XFER_ABRT (1<<6) /*!< Bit 6 for device in transfer abort state */
/** @} */
/**
* \defgroup DEVICE_HAL_COMMON_DEFCMD Common Device Defining Command
* \ingroup DEVICE_HAL_COMMON
* \brief definitions for defining command code
* \details here defines macros to define command code,
* in system code, use \ref DEV_SET_SYSCMD to define command code.
* in user code, use \ref DEV_SET_USRCMD to define command code.
* So that there will be no conflicts in system and user defined command code.
* this used used in
* \ref DEVICE_HAL_UART, \ref DEVICE_HAL_SPI,
* \ref DEVICE_HAL_IIC, \ref DEVICE_HAL_GPIO,
* and in user code
* @{
*/
/*
* macros for control command base
*/
#define DEV_SYS_CMDBSE (0x00000000) /*!< default system device control command base(defined by embARC) */
#define DEV_USR_CMDBSE (0x80000000) /*!< default user device control command base(defined by user) in user implementing */
#define DEV_SET_SYSCMD(cmd) (DEV_SYS_CMDBSE|(cmd)) /*!< set device system control command */
#define DEV_SET_USRCMD(cmd) (DEV_USR_CMDBSE|(cmd)) /*!< set device user control command */
#define CONV2VOID(param) ((void *)(param)) /*!< convert param into void * type */
/** @} */
/**
* Common Device Buffer Structure
*/
typedef struct dev_buffer {
void *buf; /*!< buffer pointer */
uint32_t len; /*!< buffer length in bytes */
uint32_t ofs; /*!< current offset in buffer */
} DEV_BUFFER;
/** Init device buffer */
#define DEV_BUFFER_INIT(devbuf, buffer, size) { \
(devbuf)->buf = (void *)(buffer); \
(devbuf)->len = (uint32_t)(size); \
(devbuf)->ofs = (uint32_t)(0); \
}
/**
* Device callback function typedef.
* This is usually used in device callback settings,
* and \ptr should be the device object pointer,
* such as DEV_IIC * */
typedef void (*DEV_CALLBACK) (void *ptr);
/** @} */
#endif /* _DEVICE_HAL_COMMON_H_ */
bsp/synopsys/embarc/device/device_hal/inc/dev_gpio.h
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bsp/synopsys/embarc/inc/arc/arc_em.h
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/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-06-12
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup ARC_HAL_CORE_EM
* \brief header file of EM series
*/
/**
* \addtogroup ARC_HAL_CORE_EM
* @{
*/
#ifndef _ARC_HAL_EM_H_
#define _ARC_HAL_EM_H_
#include "inc/arc/arc.h"
#define AUX_ACC0_LO (0x580)
#define AUX_ACC0_GLO (0x581)
#define AUX_ACC0_HI (0x582)
#define AUX_ACC0_GHI (0x583)
#define AUX_DSP_BFLY0 (0x598)
#define AUX_DSP_FFT_CTRL (0x59e)
#define AUX_DSP_CTRL (0x59f)
#define AUX_AGU_AUX_AP0 (0x5c0)
#define AUX_AGU_AUX_AP1 (0x5c1)
#define AUX_AGU_AUX_AP2 (0x5c2)
#define AUX_AGU_AUX_AP3 (0x5c3)
#define AUX_AGU_AUX_AP4 (0x5c4)
#define AUX_AGU_AUX_AP5 (0x5c5)
#define AUX_AGU_AUX_AP6 (0x5c6)
#define AUX_AGU_AUX_AP7 (0x5c7)
#define AUX_AGU_AUX_AP8 (0x5c8)
#define AUX_AGU_AUX_AP9 (0x5c9)
#define AUX_AGU_AUX_AP10 (0x5ca)
#define AUX_AGU_AUX_AP11 (0x5cb)
#define AUX_AGU_AUX_AP12 (0x5cc)
#define AUX_AGU_AUX_AP13 (0x5cd)
#define AUX_AGU_AUX_AP14 (0x5ce)
#define AUX_AGU_AUX_AP15 (0x5cf)
#define AUX_AGU_AXU_OS0 (0x5d0)
#define AUX_AGU_AXU_OS1 (0x5d1)
#define AUX_AGU_AXU_OS2 (0x5d2)
#define AUX_AGU_AXU_OS3 (0x5d3)
#define AUX_AGU_AXU_OS4 (0x5d4)
#define AUX_AGU_AXU_OS5 (0x5d5)
#define AUX_AGU_AXU_OS6 (0x5d6)
#define AUX_AGU_AXU_OS7 (0x5d7)
#define AUX_AGU_AXU_OS8 (0x5d8)
#define AUX_AGU_AXU_OS9 (0x5d9)
#define AUX_AGU_AXU_OS10 (0x5da)
#define AUX_AGU_AXU_OS11 (0x5db)
#define AUX_AGU_AXU_OS12 (0x5dc)
#define AUX_AGU_AXU_OS13 (0x5dd)
#define AUX_AGU_AXU_OS14 (0x5de)
#define AUX_AGU_AXU_OS15 (0x5df)
#define AUX_AGU_AUX_MOD0 (0x5e0)
#define AUX_AGU_AUX_MOD1 (0x5e1)
#define AUX_AGU_AUX_MOD2 (0x5e2)
#define AUX_AGU_AUX_MOD3 (0x5e3)
#define AUX_AGU_AUX_MOD4 (0x5e4)
#define AUX_AGU_AUX_MOD5 (0x5e5)
#define AUX_AGU_AUX_MOD6 (0x5e6)
#define AUX_AGU_AUX_MOD7 (0x5e7)
#define AUX_AGU_AUX_MOD8 (0x5e8)
#define AUX_AGU_AUX_MOD9 (0x5e9)
#define AUX_AGU_AUX_MOD10 (0x5ea)
#define AUX_AGU_AUX_MOD11 (0x5eb)
#define AUX_AGU_AUX_MOD12 (0x5ec)
#define AUX_AGU_AUX_MOD13 (0x5ed)
#define AUX_AGU_AUX_MOD14 (0x5ee)
#define AUX_AGU_AUX_MOD15 (0x5ef)
#define AUX_AGU_AUX_MOD16 (0x5f0)
#define AUX_AGU_AUX_MOD17 (0x5f1)
#define AUX_AGU_AUX_MOD18 (0x5f2)
#define AUX_AGU_AUX_MOD19 (0x5f3)
#define AUX_AGU_AUX_MOD20 (0x5f4)
#define AUX_AGU_AUX_MOD21 (0x5f5)
#define AUX_AGU_AUX_MOD22 (0x5f6)
#define AUX_AGU_AUX_MOD23 (0x5f7)
#define AUX_XCCM_BASE (0x5f8)
#define AUX_YCCM_BASE (0x5f9)
/** \todo add em series specific definitions here */
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _ARC_HAL_EM_H_ */
/** @} */
bsp/synopsys/embarc/inc/arc/arc_exception.h
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bsp/synopsys/embarc/inc/arc/arc_timer.h
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/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-07-15
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup ARC_HAL_MISC_TIMER
* \brief header file of ARC internal timer
*/
/**
* \addtogroup ARC_HAL_MISC_TIMER
* @{
*/
#ifndef _ARC_HAL_TIMER_H_
#define _ARC_HAL_TIMER_H_
#include "inc/arc/arc.h"
#include "inc/embARC_toolchain.h"
/**
* \name arc internal timers names
* @{
*/
#define TIMER_0 0 /*!< macro name for arc internal timer 0 */
#define TIMER_1 1 /*!< macro name for arc internal timer 1 */
#define TIMER_RTC 2 /*!< macro name for arc internal RTC */
/** @} */
/**
* \name bit definition of RTC CTRL reg
* @{
*/
#define TIMER_RTC_ENABLE 0x01 /*!< enable RTC */
#define TIMER_RTC_CLEAR 0x02 /* clears the AUX_RTC_LOW and AUX_RTC_HIGH */
#define TIMER_RTC_STATUS_A0 0x40000000 /*!< track bit of atomicity of reads of RTC */
#define TIMER_RTC_STATUS_A1 0x80000000 /*!< track bit of atomicity of reads of RTC */
/** @} */
/**
* \name bit definition of timer CTRL reg
* @{
*/
#define TIMER_CTRL_IE (1 << 0) /*!< Interrupt when count reaches limit */
#define TIMER_CTRL_NH (1 << 1) /*!< Count only when CPU NOT halted */
#define TIMER_CTRL_W (1 << 2) /*!< watchdog enable */
#define TIMER_CTRL_IP (1 << 3) /*!< interrupt pending */
/** @} */
#ifdef __cplusplus
extern "C" {
#endif
extern int32_t arc_timer_present(const uint32_t no);
extern int32_t arc_timer_start(const uint32_t no, const uint32_t mode, const uint32_t val);
extern int32_t arc_timer_stop(const uint32_t no);
extern int32_t arc_timer_current(const uint32_t no, void* val);
extern int32_t arc_timer_int_clear(const uint32_t no);
extern void arc_timer_init(void);
#ifdef __cplusplus
}
#endif
#endif /* _ARC_HAL_TIMER_H_ */
/** }@*/
bsp/synopsys/embarc/inc/embARC_debug.h
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/* ------------------------------------------
* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2017.03
* \date 2014-12-26
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup EMBARC_DEBUG
* \brief necessary definitions of debug
*/
#ifndef _EMBARC_DEBUG_H_
#define _EMBARC_DEBUG_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifndef EMBARC_PRINTF
#include "common/xprintf.h"
#define EMBARC_PRINTF xprintf
#endif
/*
* if you want to use DBG or dbg_printf,
* please define DEBUG or DBG_LESS or DBG_MORE before include embARC_debug.h
* DEBUG: enable debug print
* DBG_LESS: enable less debug msg
* DBG_MORE: enable more debug msg
**/
#if defined(DEBUG)
#if defined(DEBUG_HOSTLINK)
#include <stdio.h>
#define DBG(fmt, ...) printf(fmt, ##__VA_ARGS__)
#else
#define DBG(fmt, ...) EMBARC_PRINTF(fmt, ##__VA_ARGS__)
#endif
#else
#define DBG(fmt, ...)
#endif
#define DBG_LESS_INFO 0x01 /* less debug messages */
#define DBG_MORE_INFO 0x02 /* more debug messages */
#if defined (DBG_LESS)
#define DBG_TYPE (DBG_LESS_INFO)
#elif defined (DBG_MORE)
#define DBG_TYPE ((DBG_LESS_INFO) | (DBG_MORE_INFO))
#else
#define DBG_TYPE 0
#endif
#if DBG_TYPE > 0
#define dbg_printf(type, fmt, ...) \
if (((type) & DBG_TYPE)) { EMBARC_PRINTF(fmt, ##__VA_ARGS__); }
#else
#define dbg_printf(type, fmt, ...)
#endif
#ifdef __cplusplus
}
#endif
#endif /* DEBUG_H_ */
bsp/synopsys/embarc/inc/embARC_error.h
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/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-12-25
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup EMBARC_ERROR
* \brief header file to define common definitions error management
*/
/**
* \addtogroup EMBARC_ERROR
* @{
*/
#ifndef _EMBARC_ERROR_H_
#define _EMBARC_ERROR_H_
#include <stdint.h>
#include "inc/arc/arc_builtin.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name Main Error Code Definitions
* @{
*/
#define E_OK (0) /*!< ok */
#define E_SYS (-5) /*!< system error */
#define E_NOSPT (-9) /*!< unsupported features */
#define E_RSFN (-10) /*!< reserved function code */
#define E_RSATR (-11) /*!< reserved attribute */
#define E_PAR (-17) /*!< parameter error */
#define E_ID (-18) /*!< invalid ID number */
#define E_CTX (-25) /*!< context error */
#define E_MACV (-26) /*!< memory access violation */
#define E_OACV (-27) /*!< object access violation */
#define E_ILUSE (-28) /*!< illegal service call use */
#define E_NOMEM (-33) /*!< insufficient memory */
#define E_NOID (-34) /*!< no ID number available */
#define E_NORES (-35) /*!< no resource available */
#define E_OBJ (-41) /*!< object state error */
#define E_NOEXS (-42) /*!< non-existent object */
#define E_QOVR (-43) /*!< queue overflow */
#define E_RLWAI (-49) /*!< forced release from waiting */
#define E_TMOUT (-50) /*!< polling failure or timeout */
#define E_DLT (-51) /*!< waiting object deleted */
#define E_CLS (-52) /*!< waiting object state changed */
#define E_WBLK (-57) /*!< non-blocking accepted */
#define E_BOVR (-58) /*!< buffer overflow */
#define E_OPNED (-6) /*!< device is opened */
#define E_CLSED (-7) /*!< device is closed */
/** @} end of name */
/**
* \name Generate And Decompose Error Code
* @{
*/
#ifndef ERCD
/** generate error code using main error code and sub error code */
#define ERCD(mercd, sercd) \
((uint32_t)((((uint32_t) sercd) << 8) | (((uint32_t) mercd) & 0xffU)))
#endif /* ERCD */
#ifndef MERCD
#ifdef INT8_MAX
/** get main error code from error code */
#define MERCD(ercd) ((uint32_t)((int8_t)(ercd)))
#else /* INT8_MAX */
/** get main error code from error code */
#define MERCD(ercd) ((uint32_t)(((uint32_t) ercd) | ~0xffU))
#endif /* INT8_MAX */
#endif /* MERCD */
#ifndef SERCD
/** get sub error code from error code */
#define SERCD(ercd) ((uint32_t)((ercd) >> 8))
#endif /* SERCD */
/** @} end of name */
/**
* \name Check Error
* @{
*/
/**
* \brief check an expression to see if it is right, and when error
* set the ercd, and goto exit_label
* \param EXPR the expression that need to be checked (==0 failed)
* \param ERCD MUST pass a variable to here to get the error code
* \param ERROR_CODE error code that pass to ERCD
* \param EXIT_LABEL a label to go when error happens
*/
#define CHECK_EXP(EXPR, ERCD, ERROR_CODE, EXIT_LABEL) { \
if (_arc_rarely(!(EXPR))) { \
ERCD = (ERROR_CODE); \
goto EXIT_LABEL; \
} \
}
/**
* \brief check an expression to see if it is right, and when error
* directly goto exit_label
* \param EXPR the expression that need to be checked (==0 failed)
* \param EXIT_LABEL a label to go when error happens
* \retval
*/
#define CHECK_EXP_NOERCD(EXPR, EXIT_LABEL) { \
if (_arc_rarely(!(EXPR))) { \
goto EXIT_LABEL; \
} \
}
/** check cnt bytes align, 1 for aligned, 0 for not-aligned */
#define CHECK_ALIGN_BYTES(pointer, cnt) ((((uint32_t)(pointer)) & (cnt-1)) == 0)
/** check 2 bytes align, 1 for aligned, 0 for not-aligned */
#define CHECK_ALIGN_2BYTES(pointer) ((((uint32_t)(pointer)) & 0x1) == 0)
/** check 4 bytes align, 1 for aligned, 0 for not-aligned */
#define CHECK_ALIGN_4BYTES(pointer) ((((uint32_t)(pointer)) & 0x3) == 0)
/** check 8 bytes align, 1 for aligned, 0 for not-aligned */
#define CHECK_ALIGN_8BYTES(pointer) ((((uint32_t)(pointer)) & 0x7) == 0)
/** @} end of name */
#ifdef __cplusplus
}
#endif
#endif /* _EMBARC_ERROR_H_ */
/** @} end of group EMBARC_ERROR */
bsp/synopsys/embarc/inc/embARC_toolchain.h
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/* ------------------------------------------
* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1) Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
* be used to endorse or promote products derived from this software without
* specific prior written permission.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* \version 2016.05
* \date 2014-12-25
* \author Wayne Ren(Wei.Ren@synopsys.com)
--------------------------------------------- */
/**
* \file
* \ingroup TOOLCHAIN
* \brief toolchain dependent definitions
*/
#include <stdint.h> /* C99 standard lib */
#include <limits.h> /* C99 standard lib */
#include <stddef.h> /* C99 standard lib */
#include <stdbool.h> /* C99 standard lib */
#include "embARC_BSP_config.h"
/**
* \addtogroup TOOLCHAIN
* @{
*/
#ifndef _EMBARC_TOOLCHAIN_H_
#define _EMBARC_TOOLCHAIN_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* macro definitions of compiler extend function
*/
#ifndef __cplusplus /* C++ supports inline */
#if __STDC_VERSION__ < 199901L /* C99 supports inline */
#ifndef inline
#define inline __inline__ /* inline function */
#endif
#endif /* __STDC_VERSION__ < 199901L */
#endif /* __cplusplus */
#ifndef Inline
#define Inline static __inline__ /* inline function */
#endif
#ifndef __cplusplus /* C++ supports asm */
#ifndef asm
#define asm __asm__ /* inline asm */
#endif
#endif /* __cplusplus */
#ifndef Asm
#define Asm __asm__ volatile /* inline asm (no optimization) */
#endif
/* compiler attributes */
#define EMBARC_FORCEINLINE __attribute__((always_inline))
#define EMBARC_NOINLINE __attribute__((noinline))
#define EMBARC_PACKED __attribute__((packed))
#define EMBARC_WEAK __attribute__((weak))
#define EMBARC_ALIAS(f) __attribute__((weak, alias (#f)))
#define EMBARC_LINKTO(f) __attribute__((alias (#f)))
#define EMBARC_NORETURN __attribute__((noreturn))
#define EMBARC_NAKED __attribute__((naked)) /* function without return */
#define EMBARC_ALIGNED(x) __attribute__((aligned(x)))
/* array count macro */
#define EMBARC_ARRAY_COUNT(x) (sizeof(x)/sizeof(x[0]))
/* convert macro argument to string */
/* note: this needs one level of indirection, accomplished with the helper macro
* __EMBARC_TO_STRING */
#define __EMBARC_TO_STRING(x) #x
#define EMBARC_TO_STRING(x) __EMBARC_TO_STRING(x)
#if defined(__GNU__)
/* GNU tool specific definitions */
#elif defined(__MW__)
/* Metaware tool specific definitions */
/* Metaware toolchain related definitions */
#else
#error "unsupported toolchain"
#endif
#ifdef __cplusplus
}
#endif
#endif /* _EMBARC_TOOLCHAIN_H_ */
/** }@ */
bsp/synopsys/emsk_em9d/.config
+402
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bsp/synopsys/emsk_em9d/Kconfig
+26
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mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_EMSK
bool
select ARCH_ARC_EM
default y
source "$BSP_DIR/drivers/Kconfig"
bsp/synopsys/emsk_em9d/SConscript
+18
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# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
ASFLAGS = ' -I' + cwd
objs = objs + SConscript(os.path.join(cwd, '../embarc/SConscript'))
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/synopsys/emsk_em9d/SConstruct
+52
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import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
try:
from building import *
except:
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
print(RTT_ROOT)
exit(-1)
TARGET = 'rtthread_snps_emsk_em9d.' + rtconfig.TARGET_EXT
# use scons --gdb to debug emsk
AddOption('--gdb',
dest = 'gdb',
action = 'store_true',
default = False,
help = 'use gdb to debug the elf')
if GetOption('gdb'):
if os.path.isfile(rtconfig.TARGET):
os.system(rtconfig.DBG + rtconfig.DBG_HW_FLAGS + rtconfig.TARGET)
else:
print rtconfig.TARGET + 'not exist, please build first!!'
exit(0)
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# if the linker script changed, relink the target
Depends(TARGET, rtconfig.LINK_SCRIPT)
# make a building
DoBuilding(TARGET, objs)
bsp/synopsys/emsk_em9d/applications/SConscript
+11
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Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/synopsys/emsk_em9d/applications/application.c
+29
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <rtthread.h>
/* thread phase init */
static void rt_init_thread_entry(void *parameter)
{
/* do component initialization */
rt_components_init();
/* add your initialization here */
}
int rt_application_init()
{
rt_thread_t tid;
tid = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 2048,
RT_THREAD_PRIORITY_MAX/3, 20);
if (tid != RT_NULL)
rt_thread_startup(tid);
return 0;
}
bsp/synopsys/emsk_em9d/applications/startup.c
+71
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
extern int rt_application_init(void);
void rt_hw_interrupt_init(void)
{
/* rt-thread specific interrupt and exception init */
}
/**
* This function will startup RT-Thread RTOS.
*/
void rtthread_startup(void)
{
/* initialize hardware interrupt */
rt_hw_interrupt_init();
/* initialize board */
rt_hw_board_init();
/* show RT-Thread version */
rt_show_version();
/* initialize memory system */
#ifdef RT_USING_HEAP
rt_system_heap_init(HEAP_BEGIN, HEAP_END);
#endif
/* initialize scheduler system */
rt_system_scheduler_init();
/* initialize system timer */
rt_system_timer_init();
/* initialize soft timer thread */
rt_system_timer_thread_init();
/* initialize application */
rt_application_init();
/* initialize idle thread */
rt_thread_idle_init();
/* start scheduler */
rt_system_scheduler_start();
/* never reach here */
return ;
}
int board_main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* invoke rtthread_startup */
rtthread_startup();
return 0;
}
bsp/synopsys/emsk_em9d/drivers/Kconfig
+10
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config EMSK_USING_UART0
bool "Using UART0"
select RT_USING_SERIAL
default y
config EMSK_USING_UART1
bool "Using UART1"
select RT_USING_SERIAL
default y
bsp/synopsys/emsk_em9d/drivers/SConscript
+15
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import copy
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
ASFLAGS = ' -I' + cwd
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
Return('group')
bsp/synopsys/emsk_em9d/drivers/arc_core_config.h
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bsp/synopsys/emsk_em9d/drivers/board.c
+283
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bsp/synopsys/emsk_em9d/drivers/board.h
+28
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "emsk_hardware.h"
#define BOARD_OS_TIMER_ID 0
#define BOARD_OS_TIMER_INTNO 16
#define BOARD_CPU_CLOCK 25000000
#if defined(__GNUC__)
extern int __start_heap;
#define HEAP_BEGIN ((void*)&__start_heap)
#endif
extern int __end_heap;
#define HEAP_END (void*)(&__end_heap)
void rt_hw_board_init();
int rt_hw_uart_init(void);
#endif
bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.c
+324
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bsp/synopsys/emsk_em9d/drivers/dw_gpio_obj.h
+51
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _DW_GPIO_OBJ_H_
#define _DW_GPIO_OBJ_H_
#include "device/designware/gpio/dw_gpio.h"
/**
* \name Designware GPIO Port Bank Control Macros
* @{
*/
#define USE_DW_GPIO_PORT_A 1
#define USE_DW_GPIO_PORT_B 1
#define USE_DW_GPIO_PORT_C 1
#define USE_DW_GPIO_PORT_D 1
/** @} end of name */
/**
* \name Designware GPIO Port Interrupt Available Number Macros
* @{
*/
#define EMSK_GPIO_A_INT_MAX_COUNT 32
#define EMSK_GPIO_B_INT_MAX_COUNT 0
#define EMSK_GPIO_C_INT_MAX_COUNT 0
#define EMSK_GPIO_D_INT_MAX_COUNT 0
/** @} end of name */
/**
* \name Designware GPIO Port Available Bits Macros
* @{
*/
#define EMSK_GPIO_A_VALID_MASK DW_GPIO_MASK_ALL
#define EMSK_GPIO_B_VALID_MASK DW_GPIO_MASK_ALL
#define EMSK_GPIO_C_VALID_MASK DW_GPIO_MASK_ALL
#define EMSK_GPIO_D_VALID_MASK DW_GPIO_MASK_ALL
/** @} end of name */
#ifdef __cplusplus
extern "C" {
#endif
extern void dw_gpio_all_install(void);
#ifdef __cplusplus
}
#endif
#endif /* _DW_GPIO_OBJ_H_*/
bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.c
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bsp/synopsys/emsk_em9d/drivers/dw_uart_obj.h
+52
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _DW_UART_OBJ_H_
#define _DW_UART_OBJ_H_
#include "device/device_hal/inc/dev_uart.h"
/**
* \name DesignWare UART Object Number
* @{
*/
#define DW_UART_NUM (2) /*!< DesignWare UART valid number */
/** @} end of name */
/**
* \name Designware UART Object ID Macros
* @{
*/
#define DW_UART_0_ID 0 /*!< uart 0 id macro */
#define DW_UART_1_ID 1 /*!< uart 1 id macro */
/** @} end of name */
/**
* \name Designware UART Object Control Macros
* @{
*/
#define USE_DW_UART_0 1 /*!< enable use designware uart 0 */
#define USE_DW_UART_1 1 /*!< enable use designware uart 1 */
/** @} end of name */
/**
* \name Designware UART Ringbuffer Size Control Macros
* @{
*/
#define MAX_SNDBUF_SIZE 256 /*!< max size of uart send buffer */
#define MAX_RCVBUF_SIZE 10 /*!< max size of uart recv buffer */
/** @} end of name */
#ifdef __cplusplus
extern "C" {
#endif
extern void dw_uart_all_install(void);
#ifdef __cplusplus
}
#endif
#endif /* _DW_UART_OBJ_H_ */
bsp/synopsys/emsk_em9d/drivers/embARC_BSP_config.h
+39
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _EMBARC_BSP_CONFIG_H_
#define _EMBARC_BSP_CONFIG_H_
#ifdef __cplusplus
extern "C" {
#endif
#define BOARD_EMSK
/****************************************************************************
* BSP Definitions
****************************************************************************/
/**
* Toolchain Definition for MetaWare or GNU
*/
//#define __MW__
#define __GNU__
/**
* Must be set.
* If changed, modify .lcf file for
* .stack ALIGN(4) SIZE(524288): {}
* .heap? ALIGN(4) SIZE(524288): {}
*/
#define _STACKSIZE (4 * 1024)
#define _HEAPSZ (32 * 1024)
#ifdef __cplusplus
}
#endif
#endif /* _EMBARC_CONFIG_BSP_H_ */
bsp/synopsys/emsk_em9d/drivers/emsk_hardware.h
+85
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _EMSK_HARDWARE_H_
#define _EMSK_HARDWARE_H_
#include "inc/arc/arc_feature_config.h"
/** CPU Clock Frequency definition */
#if defined(BOARD_CPU_FREQ)
/*!< Get cpu clock frequency definition from build system */
#define CLK_CPU (BOARD_CPU_FREQ)
#elif defined(ARC_FEATURE_CPU_CLOCK_FREQ)
/*!< Get cpu clock frequency definition from tcf file */
#define CLK_CPU (ARC_FEATURE_CPU_CLOCK_FREQ)
#else
/*!< Default cpu clock frequency */
#define CLK_CPU (20000000)
#endif
/** Peripheral Bus Reference Clock definition */
#ifdef BOARD_DEV_FREQ
/*!< Get peripheral bus reference clock defintion from build system */
#define CLK_BUS_APB (BOARD_DEV_FREQ)
#else
/*!< Default peripheral bus reference clock defintion */
#define CLK_BUS_APB (50000000U)
#endif
#ifdef ARC_FEATURE_DMP_PERIPHERAL
#define PERIPHERAL_BASE ARC_FEATURE_DMP_PERIPHERAL
#else
#define PERIPHERAL_BASE _arc_aux_read(AUX_DMP_PERIPHERAL)
#endif
/* Device Register Base Address */
#define REL_REGBASE_PINMUX (0x00000000U) /*!< PINMUX */
#define REL_REGBASE_SPI_MST_CS_CTRL (0x00000014U) /*!< SPI Master Select Ctrl */
#define REL_REGBASE_GPIO0 (0x00002000U) /*!< GPIO 0 Onboard */
#define REL_REGBASE_TIMERS (0x00003000U) /*!< DW TIMER */
#define REL_REGBASE_I2C0 (0x00004000U) /*!< I2C 0 */
#define REL_REGBASE_I2C1 (0x00005000U) /*!< I2C 1 */
#define REL_REGBASE_SPI0 (0x00006000U) /*!< SPI Master */
#define REL_REGBASE_SPI1 (0x00007000U) /*!< SPI Slave */
#define REL_REGBASE_UART0 (0x00008000U) /*!< UART0 is connected to PMOD */
#define REL_REGBASE_UART1 (0x00009000U) /*!< UART1 is USB-UART£¬ use UART1 as default */
#define REL_REGBASE_UART2 (0x0000A000U) /*!< UART2 */
#define REL_REGBASE_WDT (0x0000B000U) /*!< WDT */
// #define REL_REGBASE_I2S_MASTER_IN (0x0000C000U) /*!< I2S Master In */
// #define REL_REGBASE_I2S_MASTER_OUT (0x0000D000U) /*!< I2S Master Out */
// #define REL_REGBASE_GMAC (0x0000E000U) /*!< GMAC */
/* Interrupt Connection */
#define INTNO_TIMER0 16 /*!< ARC Timer0 */
#define INTNO_TIMER1 17 /*!< ARC Timer1 */
#define INTNO_SECURE_TIMER0 20 /*!< Core Secure Timer 0 */
#define INTNO_DMA_START 22 /*!< Core DMA Controller */
#define INTNO_DMA_COMPLETE 22 /*!< Core DMA Controller Complete */
#define INTNO_DMA_ERROR 23 /*!< Core DMA Controller Error */
#define INTNO_GPIO 24 /*!< GPIO controller */
#define INTNO_I2C0 25 /*!< I2C_0 controller */
#define INTNO_I2C1 26 /*!< I2C_1 controller */
#define INTNO_SPI_MASTER 27 /*!< SPI Master controller */
#define INTNO_SPI_SLAVE 28 /*!< SPI Slave controller */
#define INTNO_UART0 29 /*!< UART0 */
#define INTNO_UART1 30 /*!< UART1 */
#define INTNO_UART2 31 /*!< UART2 */
#define INTNO_DW_WDT 32 /*!< WDT */
#define INTNO_DW_TMR0 33 /*!< DW Timer 0 */
#define INTNO_DW_TMR1 34 /*!< DW Timer 1 */
// #define INTNO_I2S_Master_In 33 /*!< I2S Master In */
// #define INTNO_I2S_Master_Out 34 /*!< I2S Master Out */
// #define INTNO_GMAC 35 /*!< GMAC */
/* SPI Mater Signals Usage */
#define EMSK_SPI_LINE_0 0 /*!< CS0 -- Pmod 6 pin1 */
#define EMSK_SPI_LINE_1 1 /*!< CS1 -- Pmod 5 pin1 or Pmod 6 pin 7 */
#define EMSK_SPI_LINE_2 2 /*!< CS2 -- Pmod 6 pin8 */
#define EMSK_SPI_LINE_SDCARD 3 /*!< CS3 -- On-board SD card */
#define EMSK_SPI_LINE_SPISLAVE 4 /*!< CS4 -- Internal SPI slave */
#define EMSK_SPI_LINE_SFLASH 5 /*!< CS5 -- On-board SPI Flash memory */
#endif /* _EMSK_HARDWARE_H_ */
bsp/synopsys/emsk_em9d/drivers/mux.c
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "mux_hal.h"
#include "mux.h"
static MUX_REG *mux_ctrl_regs = (MUX_REG *)0;
/** initialize i2c controller and set slave device address */
void mux_init(MUX_REG *mux_regs)
{
// Initialize Mux controller registers by default values
mux_regs[PMOD_MUX_CTRL] = PMOD_MUX_CTRL_DEFAULT;
mux_regs[SPI_MAP_CTRL] = SPI_MAP_CTRL_DEFAULT;
mux_regs[UART_MAP_CTRL] = UART_MAP_CTRL_DEFAULT;
mux_ctrl_regs = mux_regs;
}
/** Get mux ctrl register pointer, only valid after mux_init */
MUX_REG *get_mux_regs(void)
{
return mux_ctrl_regs;
}
/** set PMOD muxer scheme */
void set_pmod_mux(MUX_REG *mux_regs, uint32_t val)
{
mux_regs[PMOD_MUX_CTRL] = val;
}
/** get PMOD muxer scheme */
uint32_t get_pmod_mux(MUX_REG *mux_regs)
{
return (uint32_t) mux_regs[PMOD_MUX_CTRL];
}
/** set PMOD muxer scheme */
void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits)
{
mux_regs[PMOD_MUX_CTRL] = ((mux_regs[PMOD_MUX_CTRL] & ~change_bits) | val);
}
/** set SPI connection scheme */
void set_spi_map(MUX_REG *mux_regs, uint32_t val)
{
mux_regs[SPI_MAP_CTRL] = val;
}
/** get SPI connection scheme */
uint32_t get_spi_map(MUX_REG *mux_regs)
{
return (uint32_t) mux_regs[SPI_MAP_CTRL];
}
/** set UART connection scheme */
void set_uart_map(MUX_REG *mux_regs, uint32_t val)
{
mux_regs[UART_MAP_CTRL] = val;
}
/** get UART connection scheme */
uint32_t get_uart_map(MUX_REG *mux_regs)
{
return (uint32_t) mux_regs[UART_MAP_CTRL];
}
bsp/synopsys/emsk_em9d/drivers/mux.h
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MUX_H_
#define _MUX_H_
#include "inc/embARC_toolchain.h"
#define BIT0 (0)
#define BIT1 (1)
#define BIT2 (2)
#define BIT3 (3)
#define PM1_OFFSET (0)
#define PM2_OFFSET (4)
#define PM3_OFFSET (8)
#define PM4_OFFSET (12)
#define PM5_OFFSET (16)
#define PM6_OFFSET (20)
#define PM7_OFFSET (24)
#define PM1_MASK (0xf << PM1_OFFSET)
#define PM2_MASK (0xf << PM2_OFFSET)
#define PM3_MASK (0xf << PM3_OFFSET)
#define PM4_MASK (0xf << PM4_OFFSET)
#define PM5_MASK (0xf << PM5_OFFSET)
#define PM6_MASK (0xf << PM6_OFFSET)
#define PM7_MASK (0xf << PM7_OFFSET)
#define SPI_MAP_NORMAL (0)
#define SPI_MAP_LOOPBACK (1)
#define UART_MAP_TYPE4 (0xE4)
#define UART_MAP_TYPE3 (0x6C)
/**
* \name Default pin muxer settings
* @{
*/
#define PMOD_MUX_CTRL_DEFAULT (0) /*!< all pins are configured as GPIO inputs */
#define SPI_MAP_CTRL_DEFAULT (SPI_MAP_NORMAL) /*!< normal SPI mode */
#define UART_MAP_CTRL_DEFAULT (UART_MAP_TYPE4) /*!< TYPE4 PMOD compatible */
/** @} end of name */
/**
* \name PMOD 1 Multiplexor
* @{
*/
#define PM1_UR_GPIO_C ((0 << BIT0) << PM1_OFFSET) /*!< Pmod1[4:1] are connected to DW GPIO Port C[11:8] */
#define PM1_UR_UART_0 ((1 << BIT0) << PM1_OFFSET) /*!< Pmod1[4:1] are connected to DW UART0 signals */
#define PM1_LR_GPIO_A ((0 << BIT2) << PM1_OFFSET) /*!< Pmod1[10:7] are connected to DW GPIO Port A[11:8] */
#define PM1_LR_SPI_S ((1 << BIT2) << PM1_OFFSET) /*!< Pmod1[10:7] are connected to DW SPI Slave signals */
/** @} end of name */
/**
* \name PMOD 2 Multiplexor
* @{
*/
#define PM2_GPIO_AC ((0 << BIT0) << PM2_OFFSET) /*!< Pmod2[4:1] are connected to DW GPIO Port C[15:12],
Pmod2[10:7] are connected to DW GPIO Port A[15:12] */
#define PM2_I2C_HRI ((1 << BIT0) << PM2_OFFSET) /*!< connect I2C to Pmod2[4:1] and halt/run interface to Pmod2[10:7] */
/** @} end of name */
/**
* \name PMOD 3 Multiplexor
* @{
*/
#define PM3_GPIO_AC ((0 << BIT0) << PM3_OFFSET) /*!< Pmod3[4:1] are connected to DW GPIO Port C[19:16],
Pmod3[10:7] are connected to DW GPIO Port A[19:16] */
#define PM3_I2C_GPIO_D ((1 << BIT0) << PM3_OFFSET) /*!< Pmod3[4:3] are connected to DW I2C signals,
Pmod3[2:1] are connected to DW GPIO Port D[1:0],
Pmod3[10:7] are connected to DW GPIO Port D[3:2] */
/** @} end of name */
/**
* \name PMOD 4 Multiplexor
* @{
*/
#define PM4_GPIO_AC ((0 << BIT0) << PM4_OFFSET) /*!< Pmod4[4:1] are connected to DW GPIO Port C[23:20],
Pmod4[10:7] are connected to DW GPIO Port A[23:20] */
#define PM4_I2C_GPIO_D ((1 << BIT0) << PM4_OFFSET) /*!< Pmod4[4:3] are connected to DW I2C signals,
Pmod4[2:1] are connected to DW GPIO Port D[5:4],
Pmod4[10:7] are connected to DW GPIO Port D[7:6] */
/** @} end of name */
/**
* \name PMOD 5 Multiplexor
* @{
*/
#define PM5_UR_GPIO_C ((0 << BIT0) << PM5_OFFSET) /*!< Pmod5[4:1] are connected to DW GPIO Port C[27:24] */
#define PM5_UR_SPI_M1 ((1 << BIT0) << PM5_OFFSET) /*!< Pmod5[4:1] are connected to DW SPI Master signals using CS1_N */
#define PM5_LR_GPIO_A ((0 << BIT2) << PM5_OFFSET) /*!< Pmod5[10:7] are connected to DW GPIO Port A[27:24] */
#define PM5_LR_SPI_M2 ((1 << BIT2) << PM5_OFFSET) /*!< Pmod5[10:7] are connected to DW SPI Master signals using CS2_N */
/** @} end of name */
/**
* \name PMOD 6 Multiplexor
* @{
*/
#define PM6_UR_GPIO_C ((0 << BIT0) << PM6_OFFSET) /*!< Pmod6[4:1] are connected to DW GPIO Port C[31:28] */
#define PM6_UR_SPI_M0 ((1 << BIT0) << PM6_OFFSET) /*!< Pmod6[4:1] are connected to DW SPI Master signals using CS0_N */
#define PM6_LR_GPIO_A ((0 << BIT2) << PM6_OFFSET) /*!< Pmod6[10:7] are connected to DW GPIO Port A[31:28] */
#define PM6_LR_CSS_STAT ((1 << BIT2) << PM6_OFFSET) /*!< Pmod6[8:7] are connected to the DW SPI Master chip select signals CS1_N and CS2_N,
Pmod6[6:5] are connected to the ARC EM halt and sleep status signals */
/** @} end of name */
/**
* \name PMOD 7 Multiplexor
* @{
*/
#define PM7_GPIO_D ((0 << BIT0) << PM7_OFFSET) /*!< Pmod7[4:1] are connected to DW GPIO Port D[11:8] */
#define PM7_STAT ((1 << BIT0) << PM7_OFFSET) /*!< Pmod7[4:1] are connected to the ARC EM sleep status signals */
/** @} end of name */
typedef volatile uint32_t MUX_REG;
#ifdef __cplusplus
extern "C" {
#endif
extern void mux_init(MUX_REG *mux_regs);
extern MUX_REG *get_mux_regs(void);
extern void set_pmod_mux(MUX_REG *mux_regs, uint32_t val);
extern uint32_t get_pmod_mux(MUX_REG *mux_regs);
extern void change_pmod_mux(MUX_REG *mux_regs, uint32_t val, uint32_t change_bits);
extern void set_spi_map(MUX_REG *mux_regs, uint32_t val);
extern uint32_t get_spi_map(MUX_REG *mux_regs);
extern void set_uart_map(MUX_REG *mux_regs, uint32_t val);
extern uint32_t get_uart_map(MUX_REG *mux_regs);
#ifdef __cplusplus
}
#endif
#endif /* _MUX_H_ */
bsp/synopsys/emsk_em9d/drivers/mux_hal.h
+29
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/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _MUX_HAL_H_
#define _MUX_HAL_H_
/**
* \name Mux Control Register Index
* @{
*/
#define PMOD_MUX_CTRL 0 /*!< 32-bits, offset 0x0,
This register controls mapping of the peripheral device signals on Pmod connectors */
#define I2C_MAP_CTRL 1 /*!< 32-bits, offset 0x4 */
#define SPI_MAP_CTRL 2 /*!< 32-bits, offset 0x8,
SPI_MAP_CTRL[0] selects the mode of operation of the SPI Slave:
- Normal operation, SPI_MAP_CTRL[0]=0: SPI Slave is connected to Pmod1 at connector J1.
- Loop-back mode, SPI_MAP_CTRL[0]=1: SPI Slave is connected to the SPI Master inside the FPGA using CS4.
*/
#define UART_MAP_CTRL 3 /*!< 32-bits, offset 0x8,
This register controls the mapping of the UART signals on the Pmod1 connector. */
/** @} end of name */
#endif /* _MUX_HAL_H_ */
bsp/synopsys/emsk_em9d/emsk_em9d.ld
+114
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@@ -0,0 +1,114 @@
MEMORY
{
ICCM : ORIGIN = 0x00000000, LENGTH = 0x40000
DCCM : ORIGIN = 0x80000000, LENGTH = 0x20000
EXT_RAM : ORIGIN = 0x10000000, LENGTH = 0x8000000
}
ENTRY(_start)
SECTIONS
{
.init :
{
_f_init = .;
KEEP (*(.init_vector))
KEEP (*(.init_bootstrap))
_e_init = .;
} > EXT_RAM
.vector : ALIGN(1024)
{
_f_vector = .;
*(.vector)
_e_vector = .;
} > EXT_RAM
.text : ALIGN(4)
{
_f_text = .;
*(.text .text.* .gnu.linkonce.t.*)
_e_text = .;
} > EXT_RAM
.rodata : ALIGN(4)
{
_f_rodata = .;
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
KEEP(*(SORT_BY_NAME(".ctors*")))
LONG(0)
__CTOR_END__ = .;
. = ALIGN(4);
__init_array_start = .;
KEEP(*(SORT_BY_NAME(".init_array*")))
__init_array_end = .;
. = ALIGN(4);
__DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
KEEP(*(SORT_BY_NAME(".dtors*")))
LONG(0)
__DTOR_END__ = .;
*(.rodata .rodata.* .gnu.linkonce.r.*)
_e_rodata = .;
} > EXT_RAM
.data : ALIGN(4)
{
_f_data = .;
*(.data .data.* .gnu.linkonce.d.*)
_f_sdata = .;
__SDATA_BEGIN__ = .;
*(.sdata .sdata.* .gnu.linkonce.s.*)
_e_sdata = .;
_e_data = .;
} > EXT_RAM
.bss (NOLOAD) : ALIGN(8)
{
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
_f_bss = .;
_f_sbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
_e_sbss = .;
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_e_bss = .;
} > EXT_RAM
.stack (NOLOAD) :
{
. = ALIGN(4);
_f_stack = .;
. = . + 4096;
_e_stack = .;
} > EXT_RAM
.heap (NOLOAD) :
{
. = ALIGN(4);
__start_heap = . ;
_f_heap = .;
. = . + 0x8000;
_e_heap = .;
__end_heap = . ;
} > EXT_RAM
_load_addr_text = LOADADDR(.text);
_load_addr_rodata = LOADADDR(.rodata);
_load_addr_data = LOADADDR(.data);
}
bsp/synopsys/emsk_em9d/openocd.log
+9
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@@ -0,0 +1,9 @@
Warn : deprecated option: -p/--pipe. Use '-c "gdb_port pipe; log_output openocd.log"' instead.
adapter speed: 5000 kHz
Error: libusb_open() failed with LIBUSB_ERROR_NOT_SUPPORTED
Info : clock speed 5000 kHz
Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2)
Info : JTAG tap: arc-em.cpu tap/device found: 0x200044b1 (mfg: 0x258, part: 0x0004, ver: 0x2)
target state: halted
Info : accepting 'gdb' connection from pipe
Info : dropped 'gdb' connection
bsp/synopsys/emsk_em9d/rtconfig.h
+142
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@@ -0,0 +1,142 @@
/* RT-Thread config file */
#ifndef __RTTHREAD_CFG_H__
#define __RTTHREAD_CFG_H__
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX 6
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE 4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="256">256</item>
// </integer>
#define RT_THREAD_PRIORITY_MAX 32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="1000" />
#define RT_TICK_PER_SECOND 1000
// <integer name="IDLE_THREAD_STACK_SIZE" description="The stack size of idle thread" default="512" />
#define IDLE_THREAD_STACK_SIZE 512
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
// #define RT_THREAD_DEBUG
// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
#define RT_USING_OVERFLOW_CHECK
// </section>
// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
#define RT_USING_HOOK
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO 4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE 512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND 10
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
#define RT_USING_SEMAPHORE
// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
#define RT_USING_MUTEX
// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
#define RT_USING_EVENT
// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
#define RT_USING_MAILBOX
// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
#define RT_USING_MESSAGEQUEUE
// </section>
// <section name="MM" description="Memory Management" default="always" >
// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
#define RT_USING_MEMPOOL
// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
// #define RT_USING_MEMHEAP
// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
#define RT_USING_HEAP
// <bool name="RT_USING_MEMHEAP_AS_HEAP" description="Using Memory Heap Object as system heap" default="true" />
// #define RT_USING_MEMHEAP_AS_HEAP
// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
#define RT_USING_SMALL_MEM
// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
// #define RT_USING_SLAB
// </section>
// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
#define RT_USING_DEVICE
// <bool name=RT_USING_DEVICE_IPC description="Using IPC in Device Driver Framework" default="true" />
#define RT_USING_DEVICE_IPC
// <bool name="RT_USING_SERIAL" description="Using Serial Device Driver Framework" default="true" />
#define RT_USING_SERIAL
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE 64
// <bool name=RT_USING_INTERRUPT_INFO description="Using interrupt information description" default="true" />
#define RT_USING_INTERRUPT_INFO
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE 128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME "uart1"
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
#define RT_USING_COMPONENTS_INIT
// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
#define RT_USING_FINSH
// <bool name="FINSH_USING_MSH" description="Using module shell" default="true" />
#define FINSH_USING_MSH
// <bool name="FINSH_USING_MSH_DEFAULT" description="The default shell is msh" default="true" />
#define FINSH_USING_MSH_DEFAULT
// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
#define FINSH_USING_SYMTAB
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE 4096
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
// <bool name="RT_USING_LIBC" description="Using C library" default="true" />
// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
#define RT_USING_PTHREADS
// </section>
// <section name="RT_USING_DFS" description="Device file system" default="true" >
// #define RT_USING_DFS
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
// #define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX 2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX 4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// </integer>
#define RT_DFS_ELM_USE_LFN 1
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN 64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
// #define RT_USING_DFS_UFFS
// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
// #define RT_USING_DFS_DEVFS
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT "192.168.1.5:/"
// </section>
// </RDTConfigurator>
#endif
bsp/synopsys/emsk_em9d/rtconfig.py
+60
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@@ -0,0 +1,60 @@
import os
# toolchains options
ARCH='arc'
CPU='em'
CROSS_TOOL='gcc'
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
# only support GNU GCC compiler
PLATFORM = 'gcc'
EXEC_PATH = 'C:/arc/gnu/bin'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
BUILD = 'debug'
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arc-elf32-'
CC = PREFIX + 'gcc'
CXX = PREFIX + 'g++'
AS = PREFIX + 'gcc'
AR = PREFIX + 'ar'
LINK = PREFIX + 'gcc'
TARGET_EXT = 'elf'
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
DBG = PREFIX + 'gdb'
DEVICE = ' -mno-sdata -Wall -mcpu=em4_fpus -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter -mfpu=fpus_all'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
LINK_SCRIPT = 'emsk_em9d.ld'
LFLAGS = DEVICE + ' -mno-sdata -nostartfiles -Wl,--gc-sections,-Map=emsk_em9d.map,-cref,-u,system_vectors -T %s' % LINK_SCRIPT
OPENOCD_SCRIPT_ROOT = 'C:/arc/gnu/share/openocd/scripts'
OPENOCD_CFG_FILE = OPENOCD_SCRIPT_ROOT + '/board/snps_em_sk_v2.2.cfg'
OPENOCD_OPTIONS = '-s %s -f %s' % (OPENOCD_SCRIPT_ROOT, OPENOCD_CFG_FILE)
DBG_HW_FLAGS = ''' -ex "target remote | openocd --pipe %s" -ex "load" ''' % OPENOCD_OPTIONS
TARGET = 'rtthread_snps_emsk_em9d.' + TARGET_EXT
CPATH = ''
LPATH = ''
if BUILD == 'debug':
CFLAGS += ' -O0 -gdwarf-2'
AFLAGS += ' -gdwarf-2'
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' +\
SIZE + ' $TARGET \n'
#POST_ACTION = DBG + DBG_HW_FLAGS + TARGET
libcpu/arc/SConscript
+17
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@@ -0,0 +1,17 @@
# RT-Thread building script for bridge
import os
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
group = []
# add common code files
group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
# cpu porting code files
group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
Return('group')
libcpu/arc/common/SConscript
+10
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@@ -0,0 +1,10 @@
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('cpu', src, depend = [], CPPPATH = CPPPATH)
Return('group')
libcpu/arc/em/SConscript
+17
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@@ -0,0 +1,17 @@
# RT-Thread building script for component
from building import *
Import('rtconfig')
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
if rtconfig.PLATFORM == 'gcc':
src += Glob('*_gcc.S')
group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
libcpu/arc/em/contex_gcc.S
+266
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File diff suppressed because it is too large Load Diff
libcpu/arc/em/cpuport.c
+69
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@@ -0,0 +1,69 @@
/*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <rtthread.h>
#include "inc/arc/arc_exception.h"
/* enable interrupt and set interrupt priority mask */
#define ARC_INIT_STATUS (AUX_STATUS_MASK_IE | ((-1 - INT_PRI_MIN) << 1))
extern void start_r(void);
rt_uint32_t context_switch_reqflg;
rt_uint32_t rt_interrupt_from_thread;
rt_uint32_t rt_interrupt_to_thread;
struct init_stack_frame {
rt_uint32_t pc;
rt_uint32_t blink;
rt_uint32_t task;
rt_uint32_t status32;
rt_uint32_t r0;
};
/**
* shutdown CPU
*/
void rt_hw_cpu_shutdown(void)
{
}
rt_uint8_t *rt_hw_stack_init(void *tentry,
void *parameter,
rt_uint8_t *stack_addr,
void *texit)
{
struct init_stack_frame *stack_frame;
rt_uint8_t *stk;
stk = stack_addr + sizeof(rt_uint32_t);
stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
stk -= sizeof(struct init_stack_frame);
stack_frame = (struct init_stack_frame *)stk;
stack_frame->pc = (rt_uint32_t)start_r;
stack_frame->blink = (rt_uint32_t)texit;
stack_frame->task = (rt_uint32_t)tentry;
stack_frame->status32 = ARC_INIT_STATUS;
stack_frame->r0 = (rt_uint32_t)parameter;
return stk;
}
/**
* This function set the hook, which is invoked on fault exception handling.
*
* @param exception_handle the exception handling hook function.
*/
void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
{
exception_handle = exception_handle;
}