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[HC32] Add HC32F4A2/HC32F467 BSP support

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- Add chip macro for driver
 - Modify 'IDLE_THREAD_STACK_SIZE' to 512
 - Modify 'HWTIMER' to 'CLOCK_TIMER'
 - Use 'clang-format' format driver and BSP code
 - Fix SPI clock division configuration
This commit is contained in:
Leeto1970
2026-07-14 19:55:12 +08:00
committed by Rbb666
parent f8a65e4092
commit d513da02db
429 changed files with 66445 additions and 25702 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.github/ALL_BSP_COMPILE.json
+4 -2
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@@ -53,12 +53,14 @@
"at32/at32f457-start", "at32/at32f457-start",
"at32/at32m412-start", "at32/at32m412-start",
"at32/at32m416-start", "at32/at32m416-start",
"hc32/ev_hc32f4a0_lqfp176",
"hc32/ev_hc32f4a8_lqfp176",
"hc32/ev_hc32f334_lqfp64", "hc32/ev_hc32f334_lqfp64",
"hc32/ev_hc32f448_lqfp80", "hc32/ev_hc32f448_lqfp80",
"hc32/ev_hc32f460_lqfp100_v2", "hc32/ev_hc32f460_lqfp100_v2",
"hc32/ev_hc32f467_lqfp144",
"hc32/ev_hc32f472_lqfp100", "hc32/ev_hc32f472_lqfp100",
"hc32/ev_hc32f4a0_lqfp176",
"hc32/ev_hc32f4a2_lqfp176",
"hc32/ev_hc32f4a8_lqfp176",
"hc32/lckfb-hc32f4a0-lqfp100", "hc32/lckfb-hc32f4a0-lqfp100",
"hc32l196", "hc32l196",
"hc32l136", "hc32l136",
bsp/hc32/docs/HC32系列BSP制作教程.md
+1 -1
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@@ -227,7 +227,7 @@ HC32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和
- 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND） - 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND）
- BSP 中需要打开调试选项中的断言（宏：RT_DEBUG） - BSP 中需要打开调试选项中的断言（宏：RT_DEBUG）
- 系统空闲线程栈大小统一设置为 256（宏：IDLE_THREAD_STACK_SIZE） - 系统空闲线程栈大小统一设置为 512（宏：IDLE_THREAD_STACK_SIZE）
- 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT） - 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT）
- 需要开启 user main 选项（宏：RT_USING_USER_MAIN） - 需要开启 user main 选项（宏：RT_USING_USER_MAIN）
- FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY） - FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY）
bsp/hc32/docs/HC32系列驱动介绍.md
+1 -1
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@@ -40,7 +40,7 @@
| 8 | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc) | 测量管脚上的模拟量 | | 8 | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc) | 测量管脚上的模拟量 |
| 9 | [DAC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/dac/dac) | 通过管脚输出模拟量 | | 9 | [DAC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/dac/dac) | 通过管脚输出模拟量 |
| 10 | [CAN](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/can/can) | 通过 CAN 收发数据 | | 10 | [CAN](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/can/can) | 通过 CAN 收发数据 |
| 11 | [HWTIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/hwtimer/hwtimer) | 通过硬件定时器计时 | | 11 | [CLOCK_TIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/clock_timer/clock_timer) | 通过硬件定时器计时 |
| 12 | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) | 在特定的管脚输出 PWM 波形 | | 12 | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) | 在特定的管脚输出 PWM 波形 |
| 13 | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) | 设置和读取时间 | | 13 | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) | 设置和读取时间 |
| 14 | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog) | 看门狗驱动 | | 14 | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog) | 看门狗驱动 |
bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml
+2 -2
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@@ -24,9 +24,9 @@ devices.flash:
devices.gpio: devices.gpio:
kconfig: kconfig:
- CONFIG_BSP_USING_GPIO=y - CONFIG_BSP_USING_GPIO=y
devices.hwtimer: devices.clock_timer:
kconfig: kconfig:
- CONFIG_BSP_USING_HWTIMER=y - CONFIG_BSP_USING_CLOCK_TIMER=y
- CONFIG_BSP_USING_TMRA_1=y - CONFIG_BSP_USING_TMRA_1=y
devices.i2c: devices.i2c:
kconfig: kconfig:
bsp/hc32/ev_hc32f334_lqfp64/.config
+1 -1
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@@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set # CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_IDLE_THREAD_STACK_SIZE=512
# CONFIG_RT_USING_TIMER_SOFT is not set # CONFIG_RT_USING_TIMER_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set
bsp/hc32/ev_hc32f334_lqfp64/README.md
+1 -1
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@@ -46,7 +46,7 @@ EV_F334_LQ64 开发板常用 **板载资源** 如下：
| DAC | 支持 | | | DAC | 支持 | |
| FLASH | 支持 | | | FLASH | 支持 | |
| GPIO | 支持 | PA0，PA1...PF3 ---> PIN：0，1...68 | | GPIO | 支持 | PA0，PA1...PF3 ---> PIN：0，1...68 |
| HwTimer | 支持 | | | CLOCK_TIMER | 支持 | |
| I2C | 支持 | 软件、硬件 I2C | | I2C | 支持 | 软件、硬件 I2C |
| InputCapture | 支持 | | | InputCapture | 支持 | |
| MCAN | 支持 | | | MCAN | 支持 | |
bsp/hc32/ev_hc32f334_lqfp64/applications/main.c
+1 -1
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@@ -13,7 +13,7 @@
#include <board.h> #include <board.h>
/* defined the LED_BLUE pin: PC13 */ /* defined the LED_BLUE pin: PC13 */
#define LED_BLUE_PIN GET_PIN(C, 13) #define LED_BLUE_PIN GET_PIN(C, 13)
int main(void) int main(void)
{ {
bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c
+8 -8
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@@ -18,8 +18,8 @@
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_FCM_THREAD_STACK_SIZE (1024) #define XTAL32_FCM_THREAD_STACK_SIZE (1024)
#define XTAL32_FCM_UNIT (CM_FCM) #define XTAL32_FCM_UNIT (CM_FCM)
/** /**
* @brief This thread is used to monitor whether XTAL32 is stable. * @brief This thread is used to monitor whether XTAL32 is stable.
@@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter)
/* FCM config */ /* FCM config */
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
(void)FCM_StructInit(&stcFcmInit); (void)FCM_StructInit(&stcFcmInit);
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
(void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit);
/* Enable FCM, to ensure xtal32 stable */ /* Enable FCM, to ensure xtal32 stable */
FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); FCM_Cmd(XTAL32_FCM_UNIT, ENABLE);
bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig
+6 -6
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@@ -528,24 +528,24 @@ menu "On-chip Peripheral Drivers"
endif endif
menuconfig BSP_USING_CLOCK_TIMER menuconfig BSP_USING_CLOCK_TIMER
bool "Enable Hw Timer" bool "Enable Clock Timer"
default n default n
select RT_USING_CLOCK_TIME select RT_USING_CLOCK_TIME
if BSP_USING_CLOCK_TIMER if BSP_USING_CLOCK_TIMER
config BSP_USING_TMRA_1 config BSP_USING_TMRA_1
bool "Use Timer_a1 As The Hw Timer" bool "Use Timer_a1 As The Clock Timer"
default n default n
config BSP_USING_TMRA_2 config BSP_USING_TMRA_2
bool "Use Timer_a2 As The Hw Timer" bool "Use Timer_a2 As The Clock Timer"
default n default n
config BSP_USING_TMRA_3 config BSP_USING_TMRA_3
bool "Use Timer_a3 As The Hw Timer" bool "Use Timer_a3 As The Clock Timer"
default n default n
config BSP_USING_TMRA_4 config BSP_USING_TMRA_4
bool "Use Timer_a4 As The Hw Timer" bool "Use Timer_a4 As The Clock Timer"
default n default n
config BSP_USING_TMRA_5 config BSP_USING_TMRA_5
bool "Use Timer_a5 As The Hw Timer" bool "Use Timer_a5 As The Clock Timer"
default n default n
endif endif
bsp/hc32/ev_hc32f334_lqfp64/board/board.c
+8 -8
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@@ -12,9 +12,9 @@
#include "board_config.h" #include "board_config.h"
/* unlock/lock peripheral */ /* unlock/lock peripheral */
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ #define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) #define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
/** System Base Configuration /** System Base Configuration
*/ */
@@ -54,9 +54,9 @@ void SystemClock_Config(void)
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
(void)CLK_XtalStructInit(&stcXtalInit); (void)CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */ /* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
(void)CLK_XtalInit(&stcXtalInit); (void)CLK_XtalInit(&stcXtalInit);
@@ -82,8 +82,8 @@ void SystemClock_Config(void)
/* Xtal32 config */ /* Xtal32 config */
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_PIN, ENABLE); GPIO_AnalogCmd(XTAL32_PORT, XTAL32_PIN, ENABLE);
(void)CLK_Xtal32StructInit(&stcXtal32Init); (void)CLK_Xtal32StructInit(&stcXtal32Init);
stcXtal32Init.u8State = CLK_XTAL32_ON; stcXtal32Init.u8State = CLK_XTAL32_ON;
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
(void)CLK_Xtal32Init(&stcXtal32Init); (void)CLK_Xtal32Init(&stcXtal32Init);
#endif #endif
bsp/hc32/ev_hc32f334_lqfp64/board/board.h
+12 -12
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@@ -19,27 +19,27 @@
extern "C" { extern "C" {
#endif #endif
#define HC32_FLASH_ERASE_GRANULARITY (4 * 1024) #define HC32_FLASH_ERASE_GRANULARITY (4 * 1024)
#define HC32_FLASH_WRITE_GRANULARITY (4) #define HC32_FLASH_WRITE_GRANULARITY (4)
#define HC32_FLASH_SIZE (128 * 1024) #define HC32_FLASH_SIZE (128 * 1024)
#define HC32_FLASH_START_ADDRESS (0) #define HC32_FLASH_START_ADDRESS (0)
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) #define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
#define HC32_SRAM_SIZE (32) #define HC32_SRAM_SIZE (32)
#define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024) #define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION #ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM2$$ZI$$Limit; extern int Image$$RW_IRAM2$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
#elif __ICCARM__ #elif __ICCARM__
#pragma section="HEAP" #pragma section = "HEAP"
#define HEAP_BEGIN (__segment_end("HEAP")) #define HEAP_BEGIN (__segment_end("HEAP"))
#else #else
extern int __bss_end; extern int __bss_end;
#define HEAP_BEGIN (&__bss_end) #define HEAP_BEGIN (&__bss_end)
#endif #endif
#define HEAP_END HC32_SRAM_END #define HEAP_END HC32_SRAM_END
void PeripheralRegister_Unlock(void); void PeripheralRegister_Unlock(void);
void PeripheralClock_Config(void); void PeripheralClock_Config(void);
bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c
+9 -9
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@@ -141,13 +141,13 @@ void CanPhyEnable(void)
#if defined(BSP_USING_MCAN1) #if defined(BSP_USING_MCAN1)
GPIO_StructInit(&stcGpioInit); GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_RST; stcGpioInit.u16PinState = PIN_STAT_RST;
stcGpioInit.u16PinDir = PIN_DIR_OUT; stcGpioInit.u16PinDir = PIN_DIR_OUT;
GPIO_Init(MCAN1_PHY_STBY_PORT, MCAN1_PHY_STBY_PIN, &stcGpioInit); GPIO_Init(MCAN1_PHY_STBY_PORT, MCAN1_PHY_STBY_PIN, &stcGpioInit);
#endif #endif
#if defined(BSP_USING_MCAN2) #if defined(BSP_USING_MCAN2)
GPIO_StructInit(&stcGpioInit); GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_RST; stcGpioInit.u16PinState = PIN_STAT_RST;
stcGpioInit.u16PinDir = PIN_DIR_OUT; stcGpioInit.u16PinDir = PIN_DIR_OUT;
GPIO_Init(MCAN2_PHY_STBY_PORT, MCAN2_PHY_STBY_PIN, &stcGpioInit); GPIO_Init(MCAN2_PHY_STBY_PORT, MCAN2_PHY_STBY_PIN, &stcGpioInit);
#endif #endif
} }
@@ -179,7 +179,7 @@ rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx)
} }
#endif #endif
#if defined (RT_USING_SPI) #if defined(RT_USING_SPI)
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
{ {
rt_err_t result = RT_EOK; rt_err_t result = RT_EOK;
@@ -194,10 +194,10 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
(void)GPIO_StructInit(&stcGpioInit); (void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
break; break;
@@ -311,24 +311,24 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
#endif #endif
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE) #if defined(BSP_USING_INPUT_CAPTURE)
rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
{ {
rt_err_t result = RT_EOK; rt_err_t result = RT_EOK;
switch ((rt_uint32_t)tmr_instance) switch ((rt_uint32_t)tmr_instance)
{ {
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
case (rt_uint32_t)CM_TMR6_1: case (rt_uint32_t)CM_TMR6_1:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC);
break; break;
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
case (rt_uint32_t)CM_TMR6_2: case (rt_uint32_t)CM_TMR6_2:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC);
break; break;
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
case (rt_uint32_t)CM_TMR6_3: case (rt_uint32_t)CM_TMR6_3:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC);
break; break;
bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h
+173 -173
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@@ -18,248 +18,248 @@
/************************* XTAL port **********************/ /************************* XTAL port **********************/
#define XTAL_PORT (GPIO_PORT_F) #define XTAL_PORT (GPIO_PORT_F)
#define XTAL_IN_PIN (GPIO_PIN_00) #define XTAL_IN_PIN (GPIO_PIN_00)
#define XTAL_OUT_PIN (GPIO_PIN_01) #define XTAL_OUT_PIN (GPIO_PIN_01)
/************************ USART port **********************/ /************************ USART port **********************/
#if defined(BSP_USING_UART1) #if defined(BSP_USING_UART1)
#define USART1_RX_PORT (GPIO_PORT_B) #define USART1_RX_PORT (GPIO_PORT_B)
#define USART1_RX_PIN (GPIO_PIN_06) #define USART1_RX_PIN (GPIO_PIN_06)
#define USART1_RX_FUNC (GPIO_FUNC_33) #define USART1_RX_FUNC (GPIO_FUNC_33)
#define USART1_TX_PORT (GPIO_PORT_B) #define USART1_TX_PORT (GPIO_PORT_B)
#define USART1_TX_PIN (GPIO_PIN_07) #define USART1_TX_PIN (GPIO_PIN_07)
#define USART1_TX_FUNC (GPIO_FUNC_32) #define USART1_TX_FUNC (GPIO_FUNC_32)
#endif #endif
#if defined(BSP_USING_UART2) #if defined(BSP_USING_UART2)
#define USART2_RX_PORT (GPIO_PORT_C) #define USART2_RX_PORT (GPIO_PORT_C)
#define USART2_RX_PIN (GPIO_PIN_04) #define USART2_RX_PIN (GPIO_PIN_04)
#define USART2_RX_FUNC (GPIO_FUNC_37) #define USART2_RX_FUNC (GPIO_FUNC_37)
#define USART2_TX_PORT (GPIO_PORT_C) #define USART2_TX_PORT (GPIO_PORT_C)
#define USART2_TX_PIN (GPIO_PIN_10) #define USART2_TX_PIN (GPIO_PIN_10)
#define USART2_TX_FUNC (GPIO_FUNC_36) #define USART2_TX_FUNC (GPIO_FUNC_36)
#endif #endif
/************************ I2C port **********************/ /************************ I2C port **********************/
#if defined(BSP_USING_I2C1) #if defined(BSP_USING_I2C1)
#define I2C1_SDA_PORT (GPIO_PORT_B) #define I2C1_SDA_PORT (GPIO_PORT_B)
#define I2C1_SDA_PIN (GPIO_PIN_06) #define I2C1_SDA_PIN (GPIO_PIN_06)
#define I2C1_SDA_FUNC (GPIO_FUNC_52) #define I2C1_SDA_FUNC (GPIO_FUNC_52)
#define I2C1_SCL_PORT (GPIO_PORT_B) #define I2C1_SCL_PORT (GPIO_PORT_B)
#define I2C1_SCL_PIN (GPIO_PIN_07) #define I2C1_SCL_PIN (GPIO_PIN_07)
#define I2C1_SCL_FUNC (GPIO_FUNC_53) #define I2C1_SCL_FUNC (GPIO_FUNC_53)
#endif #endif
/*********** ADC configure *********/ /*********** ADC configure *********/
#if defined(BSP_USING_ADC1) #if defined(BSP_USING_ADC1)
#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */ #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */
#define ADC1_CH_PIN (GPIO_PIN_00) #define ADC1_CH_PIN (GPIO_PIN_00)
#endif #endif
#if defined(BSP_USING_ADC2) #if defined(BSP_USING_ADC2)
#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */ #define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */
#define ADC2_CH_PIN (GPIO_PIN_04) #define ADC2_CH_PIN (GPIO_PIN_04)
#endif #endif
#if defined(BSP_USING_ADC3) #if defined(BSP_USING_ADC3)
#define ADC3_CH_PORT (GPIO_PORT_B) /* Default ADC3_IN1 */ #define ADC3_CH_PORT (GPIO_PORT_B) /* Default ADC3_IN1 */
#define ADC3_CH_PIN (GPIO_PIN_13) #define ADC3_CH_PIN (GPIO_PIN_13)
#endif #endif
/*********** DAC configure *********/ /*********** DAC configure *********/
#if defined(BSP_USING_DAC1) #if defined(BSP_USING_DAC1)
#define DAC1_CH1_PORT (GPIO_PORT_A) #define DAC1_CH1_PORT (GPIO_PORT_A)
#define DAC1_CH1_PIN (GPIO_PIN_04) #define DAC1_CH1_PIN (GPIO_PIN_04)
#define DAC1_CH2_PORT (GPIO_PORT_A) #define DAC1_CH2_PORT (GPIO_PORT_A)
#define DAC1_CH2_PIN (GPIO_PIN_05) #define DAC1_CH2_PIN (GPIO_PIN_05)
#endif #endif
#if defined(BSP_USING_DAC2) #if defined(BSP_USING_DAC2)
#define DAC2_CH1_PORT (GPIO_PORT_A) #define DAC2_CH1_PORT (GPIO_PORT_A)
#define DAC2_CH1_PIN (GPIO_PIN_06) #define DAC2_CH1_PIN (GPIO_PIN_06)
#endif #endif
/*********** CAN configure *********/ /*********** CAN configure *********/
#if defined(BSP_USING_MCAN1) #if defined(BSP_USING_MCAN1)
#define MCAN1_TX_PORT (GPIO_PORT_A) #define MCAN1_TX_PORT (GPIO_PORT_A)
#define MCAN1_TX_PIN (GPIO_PIN_02) #define MCAN1_TX_PIN (GPIO_PIN_02)
#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_54) #define MCAN1_TX_PIN_FUNC (GPIO_FUNC_54)
#define MCAN1_RX_PORT (GPIO_PORT_C) #define MCAN1_RX_PORT (GPIO_PORT_C)
#define MCAN1_RX_PIN (GPIO_PIN_05) #define MCAN1_RX_PIN (GPIO_PIN_05)
#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_55) #define MCAN1_RX_PIN_FUNC (GPIO_FUNC_55)
#define MCAN1_PHY_STBY_PORT (GPIO_PORT_B) #define MCAN1_PHY_STBY_PORT (GPIO_PORT_B)
#define MCAN1_PHY_STBY_PIN (GPIO_PIN_01) #define MCAN1_PHY_STBY_PIN (GPIO_PIN_01)
#endif #endif
#if defined(BSP_USING_MCAN2) #if defined(BSP_USING_MCAN2)
#define MCAN2_TX_PORT (GPIO_PORT_B) #define MCAN2_TX_PORT (GPIO_PORT_B)
#define MCAN2_TX_PIN (GPIO_PIN_11) #define MCAN2_TX_PIN (GPIO_PIN_11)
#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56) #define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56)
#define MCAN2_RX_PORT (GPIO_PORT_B) #define MCAN2_RX_PORT (GPIO_PORT_B)
#define MCAN2_RX_PIN (GPIO_PIN_10) #define MCAN2_RX_PIN (GPIO_PIN_10)
#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57) #define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57)
#define MCAN2_PHY_STBY_PORT (GPIO_PORT_B) #define MCAN2_PHY_STBY_PORT (GPIO_PORT_B)
#define MCAN2_PHY_STBY_PIN (GPIO_PIN_02) #define MCAN2_PHY_STBY_PIN (GPIO_PIN_02)
#endif #endif
/************************* SPI port ***********************/ /************************* SPI port ***********************/
#if defined(BSP_USING_SPI1) #if defined(BSP_USING_SPI1)
#define SPI1_CS_PORT (GPIO_PORT_C) #define SPI1_CS_PORT (GPIO_PORT_C)
#define SPI1_CS_PIN (GPIO_PIN_01) #define SPI1_CS_PIN (GPIO_PIN_01)
#define SPI1_SCK_PORT (GPIO_PORT_B) #define SPI1_SCK_PORT (GPIO_PORT_B)
#define SPI1_SCK_PIN (GPIO_PIN_05) #define SPI1_SCK_PIN (GPIO_PIN_05)
#define SPI1_SCK_FUNC (GPIO_FUNC_49) #define SPI1_SCK_FUNC (GPIO_FUNC_49)
#define SPI1_MOSI_PORT (GPIO_PORT_A) #define SPI1_MOSI_PORT (GPIO_PORT_A)
#define SPI1_MOSI_PIN (GPIO_PIN_00) #define SPI1_MOSI_PIN (GPIO_PIN_00)
#define SPI1_MOSI_FUNC (GPIO_FUNC_50) #define SPI1_MOSI_FUNC (GPIO_FUNC_50)
#define SPI1_MISO_PORT (GPIO_PORT_A) #define SPI1_MISO_PORT (GPIO_PORT_A)
#define SPI1_MISO_PIN (GPIO_PIN_01) #define SPI1_MISO_PIN (GPIO_PIN_01)
#define SPI1_MISO_FUNC (GPIO_FUNC_51) #define SPI1_MISO_FUNC (GPIO_FUNC_51)
#endif #endif
/************************ RTC/PM *****************************/ /************************ RTC/PM *****************************/
#if defined(BSP_USING_RTC) || defined(RT_USING_PM) #if defined(BSP_USING_RTC) || defined(RT_USING_PM)
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_PORT (GPIO_PORT_C) #define XTAL32_PORT (GPIO_PORT_C)
#define XTAL32_PIN (GPIO_PIN_14 | GPIO_PIN_15) #define XTAL32_PIN (GPIO_PIN_14 | GPIO_PIN_15)
#endif #endif
#endif #endif
#if defined(RT_USING_PWM) #if defined(RT_USING_PWM)
/*********** PWM_TMRA configure *********/ /*********** PWM_TMRA configure *********/
#if defined(BSP_USING_PWM_TMRA_1) #if defined(BSP_USING_PWM_TMRA_1)
#if defined(BSP_USING_PWM_TMRA_1_CH1) #if defined(BSP_USING_PWM_TMRA_1_CH1)
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00) #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00)
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15) #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15)
#endif #endif
#if defined(BSP_USING_PWM_TMRA_1_CH2) #if defined(BSP_USING_PWM_TMRA_1_CH2)
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01) #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01)
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15) #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15)
#endif #endif
#if defined(BSP_USING_PWM_TMRA_1_CH3) #if defined(BSP_USING_PWM_TMRA_1_CH3)
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02) #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02)
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15) #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15)
#endif #endif
#if defined(BSP_USING_PWM_TMRA_1_CH4) #if defined(BSP_USING_PWM_TMRA_1_CH4)
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03) #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03)
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15) #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15)
#endif #endif
#endif #endif
/*********** PWM_TMR4 configure *********/ /*********** PWM_TMR4 configure *********/
#if defined(BSP_USING_PWM_TMR4_1) #if defined(BSP_USING_PWM_TMR4_1)
#if defined(BSP_USING_PWM_TMR4_1_OUH) #if defined(BSP_USING_PWM_TMR4_1_OUH)
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A) #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_02) #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_02)
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20) #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20)
#endif #endif
#if defined(BSP_USING_PWM_TMR4_1_OUL) #if defined(BSP_USING_PWM_TMR4_1_OUL)
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A) #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_01) #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_01)
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20) #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20)
#endif #endif
#if defined(BSP_USING_PWM_TMR4_1_OVH) #if defined(BSP_USING_PWM_TMR4_1_OVH)
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A) #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_06) #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_06)
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20) #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20)
#endif #endif
#if defined(BSP_USING_PWM_TMR4_1_OVL) #if defined(BSP_USING_PWM_TMR4_1_OVL)
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_A) #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_04) #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_04)
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20) #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20)
#endif #endif
#if defined(BSP_USING_PWM_TMR4_1_OWH) #if defined(BSP_USING_PWM_TMR4_1_OWH)
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A) #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_07) #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_07)
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20) #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20)
#endif #endif
#if defined(BSP_USING_PWM_TMR4_1_OWL) #if defined(BSP_USING_PWM_TMR4_1_OWL)
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B) #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B)
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_02) #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_02)
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20) #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20)
#endif #endif
#if defined(BSP_USING_PWM_TMR4_1_OXH) #if defined(BSP_USING_PWM_TMR4_1_OXH)
#define PWM_TMR4_1_OXH_PORT (GPIO_PORT_A) #define PWM_TMR4_1_OXH_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OXH_PIN (GPIO_PIN_01) #define PWM_TMR4_1_OXH_PIN (GPIO_PIN_01)
#define PWM_TMR4_1_OXH_PIN_FUNC (GPIO_FUNC_23) #define PWM_TMR4_1_OXH_PIN_FUNC (GPIO_FUNC_23)
#endif #endif
#if defined(BSP_USING_PWM_TMR4_1_OXL) #if defined(BSP_USING_PWM_TMR4_1_OXL)
#define PWM_TMR4_1_OXL_PORT (GPIO_PORT_A) #define PWM_TMR4_1_OXL_PORT (GPIO_PORT_A)
#define PWM_TMR4_1_OXL_PIN (GPIO_PIN_00) #define PWM_TMR4_1_OXL_PIN (GPIO_PIN_00)
#define PWM_TMR4_1_OXL_PIN_FUNC (GPIO_FUNC_23) #define PWM_TMR4_1_OXL_PIN_FUNC (GPIO_FUNC_23)
#endif #endif
#endif #endif
/*********** PWM_TMR6 configure *********/ /*********** PWM_TMR6 configure *********/
#if defined(BSP_USING_PWM_TMR6_1) #if defined(BSP_USING_PWM_TMR6_1)
#if defined(BSP_USING_PWM_TMR6_1_A) #if defined(BSP_USING_PWM_TMR6_1_A)
#define PWM_TMR6_1_A_PORT (GPIO_PORT_C) #define PWM_TMR6_1_A_PORT (GPIO_PORT_C)
#define PWM_TMR6_1_A_PIN (GPIO_PIN_00) #define PWM_TMR6_1_A_PIN (GPIO_PIN_00)
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_12) #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_12)
#endif #endif
#if defined(BSP_USING_PWM_TMR6_1_B) #if defined(BSP_USING_PWM_TMR6_1_B)
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A) #define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
#define PWM_TMR6_1_B_PIN (GPIO_PIN_00) #define PWM_TMR6_1_B_PIN (GPIO_PIN_00)
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12) #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12)
#endif #endif
#endif #endif
#endif #endif
#if defined(BSP_USING_INPUT_CAPTURE) #if defined(BSP_USING_INPUT_CAPTURE)
#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_14) #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_14)
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_C) #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_C)
#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_06) #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_06)
#endif #endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_C) #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_C)
#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07)
#endif #endif
#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_B) #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_B)
#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_02) #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_02)
#endif #endif
#endif #endif
/*********** TMRA_PULSE_ENCODER configure *********/ /*********** TMRA_PULSE_ENCODER configure *********/
#if defined(RT_USING_PULSE_ENCODER) #if defined(RT_USING_PULSE_ENCODER)
#if defined(BSP_USING_TMRA_PULSE_ENCODER) #if defined(BSP_USING_TMRA_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#endif /* BSP_USING_TMRA_PULSE_ENCODER */ #endif /* BSP_USING_TMRA_PULSE_ENCODER */
#if defined(BSP_USING_TMR6_PULSE_ENCODER) #if defined(BSP_USING_TMR6_PULSE_ENCODER)
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) #if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05) #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05)
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B)
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13) #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13)
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* BSP_USING_TMR6_PULSE_ENCODER */
#endif /* RT_USING_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */
#endif #endif
bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h
+93 -96
View File
@@ -20,42 +20,41 @@ extern "C" {
#ifdef BSP_USING_ADC1 #ifdef BSP_USING_ADC1
#ifndef ADC1_INIT_PARAMS #ifndef ADC1_INIT_PARAMS
#define ADC1_INIT_PARAMS \ #define ADC1_INIT_PARAMS \
{ \ { \
.name = "adc1", \ .name = "adc1", \
.vref = 3300, \ .vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \ .resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \ .data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \ .eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \ .hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \ .hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \ .internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \ .internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \ .continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \ .data_reg_auto_clear = RT_TRUE, \
} }
#endif /* ADC1_INIT_PARAMS */ #endif /* ADC1_INIT_PARAMS */
#if defined (BSP_ADC1_USING_DMA) #if defined(BSP_ADC1_USING_DMA)
#ifndef ADC1_EOCA_DMA_CONFIG #ifndef ADC1_EOCA_DMA_CONFIG
#define ADC1_EOCA_DMA_CONFIG \ #define ADC1_EOCA_DMA_CONFIG \
{ \ { \
.Instance = ADC1_EOCA_DMA_INSTANCE, \ .Instance = ADC1_EOCA_DMA_INSTANCE, \
.channel = ADC1_EOCA_DMA_CHANNEL, \ .channel = ADC1_EOCA_DMA_CHANNEL, \
.clock = ADC1_EOCA_DMA_CLOCK, \ .clock = ADC1_EOCA_DMA_CLOCK, \
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC1_EOCA, \ .trigger_event = EVT_SRC_ADC1_EOCA, \
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \ .flag = ADC1_EOCA_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = ADC1_EOCA_DMA_IRQn, \
.irq_num = ADC1_EOCA_DMA_IRQn, \ .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ .int_src = ADC1_EOCA_DMA_INT_SRC, \
.int_src = ADC1_EOCA_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* ADC1_EOCA_DMA_CONFIG */ #endif /* ADC1_EOCA_DMA_CONFIG */
#endif /* BSP_ADC1_USING_DMA */ #endif /* BSP_ADC1_USING_DMA */
@@ -63,42 +62,41 @@ extern "C" {
#ifdef BSP_USING_ADC2 #ifdef BSP_USING_ADC2
#ifndef ADC2_INIT_PARAMS #ifndef ADC2_INIT_PARAMS
#define ADC2_INIT_PARAMS \ #define ADC2_INIT_PARAMS \
{ \ { \
.name = "adc2", \ .name = "adc2", \
.vref = 3300, \ .vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \ .resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \ .data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \ .eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \ .hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \ .hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \ .internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \ .internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \ .continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \ .data_reg_auto_clear = RT_TRUE, \
} }
#endif /* ADC2_INIT_PARAMS */ #endif /* ADC2_INIT_PARAMS */
#if defined (BSP_ADC2_USING_DMA) #if defined(BSP_ADC2_USING_DMA)
#ifndef ADC2_EOCA_DMA_CONFIG #ifndef ADC2_EOCA_DMA_CONFIG
#define ADC2_EOCA_DMA_CONFIG \ #define ADC2_EOCA_DMA_CONFIG \
{ \ { \
.Instance = ADC2_EOCA_DMA_INSTANCE, \ .Instance = ADC2_EOCA_DMA_INSTANCE, \
.channel = ADC2_EOCA_DMA_CHANNEL, \ .channel = ADC2_EOCA_DMA_CHANNEL, \
.clock = ADC2_EOCA_DMA_CLOCK, \ .clock = ADC2_EOCA_DMA_CLOCK, \
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC2_EOCA, \ .trigger_event = EVT_SRC_ADC2_EOCA, \
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \ .flag = ADC2_EOCA_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = ADC2_EOCA_DMA_IRQn, \
.irq_num = ADC2_EOCA_DMA_IRQn, \ .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ .int_src = ADC2_EOCA_DMA_INT_SRC, \
.int_src = ADC2_EOCA_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* ADC2_EOCA_DMA_CONFIG */ #endif /* ADC2_EOCA_DMA_CONFIG */
#endif /* BSP_ADC2_USING_DMA */ #endif /* BSP_ADC2_USING_DMA */
@@ -106,42 +104,41 @@ extern "C" {
#ifdef BSP_USING_ADC3 #ifdef BSP_USING_ADC3
#ifndef ADC3_INIT_PARAMS #ifndef ADC3_INIT_PARAMS
#define ADC3_INIT_PARAMS \ #define ADC3_INIT_PARAMS \
{ \ { \
.name = "adc3", \ .name = "adc3", \
.vref = 3300, \ .vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \ .resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \ .data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \ .eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \ .hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \ .hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \ .internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \ .internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \
.continue_conv_mode_enable = RT_FALSE, \ .continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \ .data_reg_auto_clear = RT_TRUE, \
} }
#endif /* ADC3_INIT_PARAMS */ #endif /* ADC3_INIT_PARAMS */
#if defined (BSP_ADC3_USING_DMA) #if defined(BSP_ADC3_USING_DMA)
#ifndef ADC3_EOCA_DMA_CONFIG #ifndef ADC3_EOCA_DMA_CONFIG
#define ADC3_EOCA_DMA_CONFIG \ #define ADC3_EOCA_DMA_CONFIG \
{ \ { \
.Instance = ADC3_EOCA_DMA_INSTANCE, \ .Instance = ADC3_EOCA_DMA_INSTANCE, \
.channel = ADC3_EOCA_DMA_CHANNEL, \ .channel = ADC3_EOCA_DMA_CHANNEL, \
.clock = ADC3_EOCA_DMA_CLOCK, \ .clock = ADC3_EOCA_DMA_CLOCK, \
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC3_EOCA, \ .trigger_event = EVT_SRC_ADC3_EOCA, \
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \ .flag = ADC3_EOCA_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = ADC3_EOCA_DMA_IRQn, \
.irq_num = ADC3_EOCA_DMA_IRQn, \ .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ .int_src = ADC3_EOCA_DMA_INT_SRC, \
.int_src = ADC3_EOCA_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* ADC3_EOCA_DMA_CONFIG */ #endif /* ADC3_EOCA_DMA_CONFIG */
#endif /* BSP_ADC3_USING_DMA */ #endif /* BSP_ADC3_USING_DMA */
bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h
+18 -18
View File
@@ -19,30 +19,30 @@ extern "C" {
#ifdef BSP_USING_DAC1 #ifdef BSP_USING_DAC1
#ifndef DAC1_INIT_PARAMS #ifndef DAC1_INIT_PARAMS
#define DAC1_INIT_PARAMS \ #define DAC1_INIT_PARAMS \
{ \ { \
.name = "dac1", \ .name = "dac1", \
.vref = 3300, \ .vref = 3300, \
.dac_adp_enable = RT_FALSE, \ .dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \ .dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \ .ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \ .ch2_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \ .ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \ .ch2_amp_enable = RT_TRUE, \
} }
#endif /* DAC1_INIT_PARAMS */ #endif /* DAC1_INIT_PARAMS */
#endif /* BSP_USING_DAC1 */ #endif /* BSP_USING_DAC1 */
#ifdef BSP_USING_DAC2 #ifdef BSP_USING_DAC2
#ifndef DAC2_INIT_PARAMS #ifndef DAC2_INIT_PARAMS
#define DAC2_INIT_PARAMS \ #define DAC2_INIT_PARAMS \
{ \ { \
.name = "dac2", \ .name = "dac2", \
.vref = 3300, \ .vref = 3300, \
.dac_adp_enable = RT_FALSE, \ .dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \ .dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \ .ch1_output_enable = RT_TRUE, \
.ch1_amp_enable = RT_TRUE, \ .ch1_amp_enable = RT_TRUE, \
} }
#endif /* DAC2_INIT_PARAMS */ #endif /* DAC2_INIT_PARAMS */
#endif /* BSP_USING_DAC2 */ #endif /* BSP_USING_DAC2 */
bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h
+120 -120
View File
@@ -20,168 +20,168 @@ extern "C" {
/* DMA1 ch0 */ /* DMA1 ch0 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE CM_DMA #define UART1_TX_DMA_INSTANCE CM_DMA
#define UART1_TX_DMA_CHANNEL DMA_CH0 #define UART1_TX_DMA_CHANNEL DMA_CH0
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0 #define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 #define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM #define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO #define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 #define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) #elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE CM_DMA #define SPI1_TX_DMA_INSTANCE CM_DMA
#define SPI1_TX_DMA_CHANNEL DMA_CH0 #define SPI1_TX_DMA_CHANNEL DMA_CH0
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0 #define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 #define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM #define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO #define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 #define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0
#endif #endif
/* DMA1 ch1 */ /* DMA1 ch1 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE CM_DMA #define UART1_RX_DMA_INSTANCE CM_DMA
#define UART1_RX_DMA_CHANNEL DMA_CH1 #define UART1_RX_DMA_CHANNEL DMA_CH1
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1 #define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 #define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM #define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO #define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 #define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) #elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE CM_DMA #define SPI1_RX_DMA_INSTANCE CM_DMA
#define SPI1_RX_DMA_CHANNEL DMA_CH1 #define SPI1_RX_DMA_CHANNEL DMA_CH1
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1 #define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 #define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM #define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO #define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 #define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1
#endif #endif
/* DMA1 ch2 */ /* DMA1 ch2 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE CM_DMA #define UART2_TX_DMA_INSTANCE CM_DMA
#define UART2_TX_DMA_CHANNEL DMA_CH2 #define UART2_TX_DMA_CHANNEL DMA_CH2
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2 #define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 #define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM #define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO #define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2 #define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
#define I2C1_TX_DMA_INSTANCE CM_DMA #define I2C1_TX_DMA_INSTANCE CM_DMA
#define I2C1_TX_DMA_CHANNEL DMA_CH2 #define I2C1_TX_DMA_CHANNEL DMA_CH2
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2 #define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 #define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM #define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO #define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2 #define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2
#endif #endif
/* DMA1 ch3 */ /* DMA1 ch3 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_RX_DMA_INSTANCE CM_DMA #define UART2_RX_DMA_INSTANCE CM_DMA
#define UART2_RX_DMA_CHANNEL DMA_CH3 #define UART2_RX_DMA_CHANNEL DMA_CH3
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3 #define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 #define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM #define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO #define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3 #define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
#define I2C1_RX_DMA_INSTANCE CM_DMA #define I2C1_RX_DMA_INSTANCE CM_DMA
#define I2C1_RX_DMA_CHANNEL DMA_CH3 #define I2C1_RX_DMA_CHANNEL DMA_CH3
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3 #define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 #define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM #define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO #define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3 #define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3
#endif #endif
/* DMA1 ch4 */ /* DMA1 ch4 */
#if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) #if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
#define UART3_TX_DMA_INSTANCE CM_DMA #define UART3_TX_DMA_INSTANCE CM_DMA
#define UART3_TX_DMA_CHANNEL DMA_CH4 #define UART3_TX_DMA_CHANNEL DMA_CH4
#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4 #define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4
#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 #define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM #define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO #define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4 #define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
#define ADC1_EOCA_DMA_INSTANCE CM_DMA #define ADC1_EOCA_DMA_INSTANCE CM_DMA
#define ADC1_EOCA_DMA_CHANNEL DMA_CH4 #define ADC1_EOCA_DMA_CHANNEL DMA_CH4
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4 #define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 #define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM #define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO #define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4 #define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4
#endif #endif
/* DMA1 ch5 */ /* DMA1 ch5 */
#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
#define UART3_RX_DMA_INSTANCE CM_DMA #define UART3_RX_DMA_INSTANCE CM_DMA
#define UART3_RX_DMA_CHANNEL DMA_CH5 #define UART3_RX_DMA_CHANNEL DMA_CH5
#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5 #define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5
#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 #define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM #define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO #define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5 #define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
#define ADC2_EOCA_DMA_INSTANCE CM_DMA #define ADC2_EOCA_DMA_INSTANCE CM_DMA
#define ADC2_EOCA_DMA_CHANNEL DMA_CH5 #define ADC2_EOCA_DMA_CHANNEL DMA_CH5
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5 #define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 #define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM #define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO #define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5 #define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5
#endif #endif
/* DMA1 ch6 */ /* DMA1 ch6 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
#define UART4_TX_DMA_INSTANCE CM_DMA #define UART4_TX_DMA_INSTANCE CM_DMA
#define UART4_TX_DMA_CHANNEL DMA_CH6 #define UART4_TX_DMA_CHANNEL DMA_CH6
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6 #define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 #define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
#define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM #define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO #define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6 #define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6
#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
#define ADC3_EOCA_DMA_INSTANCE CM_DMA #define ADC3_EOCA_DMA_INSTANCE CM_DMA
#define ADC3_EOCA_DMA_CHANNEL DMA_CH6 #define ADC3_EOCA_DMA_CHANNEL DMA_CH6
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6 #define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 #define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM #define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO #define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6 #define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6
#endif #endif
/* DMA1 ch7 */ /* DMA1 ch7 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_RX_DMA_INSTANCE CM_DMA #define UART4_RX_DMA_INSTANCE CM_DMA
#define UART4_RX_DMA_CHANNEL DMA_CH7 #define UART4_RX_DMA_CHANNEL DMA_CH7
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) #define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS)
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7 #define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 #define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7
#define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM #define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM
#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO #define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7 #define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h
+80 -80
View File
@@ -22,146 +22,146 @@ extern "C" {
#if defined(RT_USING_PIN) #if defined(RT_USING_PIN)
#ifndef EXTINT0_IRQ_CONFIG #ifndef EXTINT0_IRQ_CONFIG
#define EXTINT0_IRQ_CONFIG \ #define EXTINT0_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT0_IRQ_NUM, \ .irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \ .irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \ .int_src = INT_SRC_PORT_EIRQ0, \
} }
#endif /* EXTINT1_IRQ_CONFIG */ #endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT1_IRQ_CONFIG #ifndef EXTINT1_IRQ_CONFIG
#define EXTINT1_IRQ_CONFIG \ #define EXTINT1_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT1_IRQ_NUM, \ .irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \ .irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \ .int_src = INT_SRC_PORT_EIRQ1, \
} }
#endif /* EXTINT1_IRQ_CONFIG */ #endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT2_IRQ_CONFIG #ifndef EXTINT2_IRQ_CONFIG
#define EXTINT2_IRQ_CONFIG \ #define EXTINT2_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT2_IRQ_NUM, \ .irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \ .irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \ .int_src = INT_SRC_PORT_EIRQ2, \
} }
#endif /* EXTINT2_IRQ_CONFIG */ #endif /* EXTINT2_IRQ_CONFIG */
#ifndef EXTINT3_IRQ_CONFIG #ifndef EXTINT3_IRQ_CONFIG
#define EXTINT3_IRQ_CONFIG \ #define EXTINT3_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT3_IRQ_NUM, \ .irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \ .irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \ .int_src = INT_SRC_PORT_EIRQ3, \
} }
#endif /* EXTINT3_IRQ_CONFIG */ #endif /* EXTINT3_IRQ_CONFIG */
#ifndef EXTINT4_IRQ_CONFIG #ifndef EXTINT4_IRQ_CONFIG
#define EXTINT4_IRQ_CONFIG \ #define EXTINT4_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT4_IRQ_NUM, \ .irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \ .irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \ .int_src = INT_SRC_PORT_EIRQ4, \
} }
#endif /* EXTINT4_IRQ_CONFIG */ #endif /* EXTINT4_IRQ_CONFIG */
#ifndef EXTINT5_IRQ_CONFIG #ifndef EXTINT5_IRQ_CONFIG
#define EXTINT5_IRQ_CONFIG \ #define EXTINT5_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT5_IRQ_NUM, \ .irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \ .irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \ .int_src = INT_SRC_PORT_EIRQ5, \
} }
#endif /* EXTINT5_IRQ_CONFIG */ #endif /* EXTINT5_IRQ_CONFIG */
#ifndef EXTINT6_IRQ_CONFIG #ifndef EXTINT6_IRQ_CONFIG
#define EXTINT6_IRQ_CONFIG \ #define EXTINT6_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT6_IRQ_NUM, \ .irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \ .irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \ .int_src = INT_SRC_PORT_EIRQ6, \
} }
#endif /* EXTINT6_IRQ_CONFIG */ #endif /* EXTINT6_IRQ_CONFIG */
#ifndef EXTINT7_IRQ_CONFIG #ifndef EXTINT7_IRQ_CONFIG
#define EXTINT7_IRQ_CONFIG \ #define EXTINT7_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT7_IRQ_NUM, \ .irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \ .irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \ .int_src = INT_SRC_PORT_EIRQ7, \
} }
#endif /* EXTINT7_IRQ_CONFIG */ #endif /* EXTINT7_IRQ_CONFIG */
#ifndef EXTINT8_IRQ_CONFIG #ifndef EXTINT8_IRQ_CONFIG
#define EXTINT8_IRQ_CONFIG \ #define EXTINT8_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT8_IRQ_NUM, \ .irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \ .irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \ .int_src = INT_SRC_PORT_EIRQ8, \
} }
#endif /* EXTINT8_IRQ_CONFIG */ #endif /* EXTINT8_IRQ_CONFIG */
#ifndef EXTINT9_IRQ_CONFIG #ifndef EXTINT9_IRQ_CONFIG
#define EXTINT9_IRQ_CONFIG \ #define EXTINT9_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT9_IRQ_NUM, \ .irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \ .irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \ .int_src = INT_SRC_PORT_EIRQ9, \
} }
#endif /* EXTINT9_IRQ_CONFIG */ #endif /* EXTINT9_IRQ_CONFIG */
#ifndef EXTINT10_IRQ_CONFIG #ifndef EXTINT10_IRQ_CONFIG
#define EXTINT10_IRQ_CONFIG \ #define EXTINT10_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT10_IRQ_NUM, \ .irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \ .irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \ .int_src = INT_SRC_PORT_EIRQ10, \
} }
#endif /* EXTINT10_IRQ_CONFIG */ #endif /* EXTINT10_IRQ_CONFIG */
#ifndef EXTINT11_IRQ_CONFIG #ifndef EXTINT11_IRQ_CONFIG
#define EXTINT11_IRQ_CONFIG \ #define EXTINT11_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT11_IRQ_NUM, \ .irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \ .irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \ .int_src = INT_SRC_PORT_EIRQ11, \
} }
#endif /* EXTINT11_IRQ_CONFIG */ #endif /* EXTINT11_IRQ_CONFIG */
#ifndef EXTINT12_IRQ_CONFIG #ifndef EXTINT12_IRQ_CONFIG
#define EXTINT12_IRQ_CONFIG \ #define EXTINT12_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT12_IRQ_NUM, \ .irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \ .irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \ .int_src = INT_SRC_PORT_EIRQ12, \
} }
#endif /* EXTINT12_IRQ_CONFIG */ #endif /* EXTINT12_IRQ_CONFIG */
#ifndef EXTINT13_IRQ_CONFIG #ifndef EXTINT13_IRQ_CONFIG
#define EXTINT13_IRQ_CONFIG \ #define EXTINT13_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT13_IRQ_NUM, \ .irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \ .irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \ .int_src = INT_SRC_PORT_EIRQ13, \
} }
#endif /* EXTINT13_IRQ_CONFIG */ #endif /* EXTINT13_IRQ_CONFIG */
#ifndef EXTINT14_IRQ_CONFIG #ifndef EXTINT14_IRQ_CONFIG
#define EXTINT14_IRQ_CONFIG \ #define EXTINT14_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT14_IRQ_NUM, \ .irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \ .irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \ .int_src = INT_SRC_PORT_EIRQ14, \
} }
#endif /* EXTINT14_IRQ_CONFIG */ #endif /* EXTINT14_IRQ_CONFIG */
#ifndef EXTINT15_IRQ_CONFIG #ifndef EXTINT15_IRQ_CONFIG
#define EXTINT15_IRQ_CONFIG \ #define EXTINT15_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT15_IRQ_NUM, \ .irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \ .irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \ .int_src = INT_SRC_PORT_EIRQ15, \
} }
#endif /* EXTINT15_IRQ_CONFIG */ #endif /* EXTINT15_IRQ_CONFIG */
bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h
+33 -35
View File
@@ -20,51 +20,49 @@ extern "C" {
#if defined(BSP_USING_I2C1) #if defined(BSP_USING_I2C1)
#ifndef I2C1_CONFIG #ifndef I2C1_CONFIG
#define I2C1_CONFIG \ #define I2C1_CONFIG \
{ \ { \
.name = "i2c1", \ .name = "i2c1", \
.Instance = CM_I2C, \ .Instance = CM_I2C, \
.clock = FCG1_PERIPH_I2C, \ .clock = FCG1_PERIPH_I2C, \
.baudrate = 100000UL, \ .baudrate = 100000UL, \
.timeout = 10000UL, \ .timeout = 10000UL, \
} }
#endif /* I2C1_CONFIG */ #endif /* I2C1_CONFIG */
#endif #endif
#if defined(BSP_I2C1_USING_DMA) #if defined(BSP_I2C1_USING_DMA)
#ifndef I2C1_TX_DMA_CONFIG #ifndef I2C1_TX_DMA_CONFIG
#define I2C1_TX_DMA_CONFIG \ #define I2C1_TX_DMA_CONFIG \
{ \ { \
.Instance = I2C1_TX_DMA_INSTANCE, \ .Instance = I2C1_TX_DMA_INSTANCE, \
.channel = I2C1_TX_DMA_CHANNEL, \ .channel = I2C1_TX_DMA_CHANNEL, \
.clock = I2C1_TX_DMA_CLOCK, \ .clock = I2C1_TX_DMA_CLOCK, \
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C_TEI, \ .trigger_event = EVT_SRC_I2C_TEI, \
.flag = I2C1_TX_DMA_TRANS_FLAG, \ .flag = I2C1_TX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C1_TX_DMA_IRQn, \
.irq_num = I2C1_TX_DMA_IRQn, \ .irq_prio = I2C1_TX_DMA_INT_PRIO, \
.irq_prio = I2C1_TX_DMA_INT_PRIO, \ .int_src = I2C1_TX_DMA_INT_SRC, \
.int_src = I2C1_TX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C1_TX_DMA_CONFIG */ #endif /* I2C1_TX_DMA_CONFIG */
#ifndef I2C1_RX_DMA_CONFIG #ifndef I2C1_RX_DMA_CONFIG
#define I2C1_RX_DMA_CONFIG \ #define I2C1_RX_DMA_CONFIG \
{ \ { \
.Instance = I2C1_RX_DMA_INSTANCE, \ .Instance = I2C1_RX_DMA_INSTANCE, \
.channel = I2C1_RX_DMA_CHANNEL, \ .channel = I2C1_RX_DMA_CHANNEL, \
.clock = I2C1_RX_DMA_CLOCK, \ .clock = I2C1_RX_DMA_CLOCK, \
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C_RXI, \ .trigger_event = EVT_SRC_I2C_RXI, \
.flag = I2C1_RX_DMA_TRANS_FLAG, \ .flag = I2C1_RX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C1_RX_DMA_IRQn, \
.irq_num = I2C1_RX_DMA_IRQn, \ .irq_prio = I2C1_RX_DMA_INT_PRIO, \
.irq_prio = I2C1_RX_DMA_INT_PRIO, \ .int_src = I2C1_RX_DMA_INT_SRC, \
.int_src = I2C1_RX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C1_RX_DMA_CONFIG */ #endif /* I2C1_RX_DMA_CONFIG */
#endif /* BSP_I2C1_USING_DMA */ #endif /* BSP_I2C1_USING_DMA */
bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h
+129 -129
View File
@@ -17,222 +17,222 @@
extern "C" { extern "C" {
#endif #endif
#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn #define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn #define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn #define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn #define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn #define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn #define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn #define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn #define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn #define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn #define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn #define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn #define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn #define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn #define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn #define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn #define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch0 */ /* DMA1 ch0 */
#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn #define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch1 */ /* DMA1 ch1 */
#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn #define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch2 */ /* DMA1 ch2 */
#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn #define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch3 */ /* DMA1 ch3 */
#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn #define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch4 */ /* DMA1 ch4 */
#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn #define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch5 */ /* DMA1 ch5 */
#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn #define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch6 */ /* DMA1 ch6 */
#define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn #define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn
#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch7 */ /* DMA1 ch7 */
#define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn #define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn
#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_UART1) #if defined(BSP_USING_UART1)
#define BSP_UART1_IRQ_NUM USART1_IRQn #define BSP_UART1_IRQ_NUM USART1_IRQn
#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \ #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2) defined(RT_USING_SERIAL_V2)
#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn #define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#endif /* BSP_USING_UART1 */ #endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2) #if defined(BSP_USING_UART2)
#define BSP_UART2_IRQ_NUM USART2_IRQn #define BSP_UART2_IRQ_NUM USART2_IRQn
#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \ #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2) defined(RT_USING_SERIAL_V2)
#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn #define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#endif /* BSP_USING_UART2 */ #endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3) #if defined(BSP_USING_UART3)
#define BSP_UART3_IRQ_NUM USART3_IRQn #define BSP_UART3_IRQ_NUM USART3_IRQn
#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)) || \ #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2) defined(RT_USING_SERIAL_V2)
#define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn #define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn
#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#endif /* BSP_USING_UART3 */ #endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4) #if defined(BSP_USING_UART4)
#define BSP_UART4_IRQ_NUM USART4_IRQn #define BSP_UART4_IRQ_NUM USART4_IRQn
#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \ #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2) defined(RT_USING_SERIAL_V2)
#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn #define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#endif /* BSP_USING_UART4 */ #endif /* BSP_USING_UART4 */
#if defined(BSP_USING_SPI1) #if defined(BSP_USING_SPI1)
#define BSP_SPI1_ERR_IRQ_NUM SPI_IRQn #define BSP_SPI1_ERR_IRQ_NUM SPI_IRQn
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#if defined (BSP_USING_QSPI) #if defined(BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn #define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_QSPI */ #endif /* BSP_USING_QSPI */
#if defined(BSP_USING_TMRA_1) #if defined(BSP_USING_TMRA_1)
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn #define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_1 */ #endif/* BSP_USING_TMRA_1 */
#if defined(BSP_USING_TMRA_2) #if defined(BSP_USING_TMRA_2)
#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn #define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_2 */ #endif/* BSP_USING_TMRA_2 */
#if defined(BSP_USING_TMRA_3) #if defined(BSP_USING_TMRA_3)
#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn #define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_3 */ #endif/* BSP_USING_TMRA_3 */
#if defined(BSP_USING_TMRA_4) #if defined(BSP_USING_TMRA_4)
#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn #define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_4 */ #endif/* BSP_USING_TMRA_4 */
#if defined(BSP_USING_TMRA_5) #if defined(BSP_USING_TMRA_5)
#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn #define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_5 */ #endif/* BSP_USING_TMRA_5 */
#if defined(BSP_USING_MCAN1) #if defined(BSP_USING_MCAN1)
#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn #define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_MCAN1 */ #endif/* BSP_USING_MCAN1 */
#if defined(BSP_USING_MCAN2) #if defined(BSP_USING_MCAN2)
#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn #define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_MCAN2 */ #endif/* BSP_USING_MCAN2 */
#if defined(RT_USING_ALARM) #if defined(RT_USING_ALARM)
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn #define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* RT_USING_ALARM */ #endif/* RT_USING_ALARM */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2) #if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3) #if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4) #if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5) #if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) #if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2) #if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
#if defined(BSP_USING_INPUT_CAPTURE) #if defined(BSP_USING_INPUT_CAPTURE)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT008_IRQn) #define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT008_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT009_IRQn) #define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT009_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT010_IRQn) #define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT010_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT011_IRQn) #define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT011_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT012_IRQn) #define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT012_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT013_IRQn) #define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT013_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM (INT014_IRQn) #define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM (INT014_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM (INT015_IRQn) #define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM (INT015_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#endif/* BSP_USING_INPUT_CAPTURE */ #endif/* BSP_USING_INPUT_CAPTURE */
#ifdef __cplusplus #ifdef __cplusplus
bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h
+232 -232
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h
+32 -32
View File
@@ -21,18 +21,18 @@ extern "C" {
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK #ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK \ #define PM_TICKLESS_TIMER_ENABLE_MASK \
( (1UL << PM_SLEEP_MODE_IDLE) | \ ((1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP)) (1UL << PM_SLEEP_MODE_DEEP))
#endif #endif
/** /**
* @brief run mode config @ref pm_run_mode_config structure * @brief run mode config @ref pm_run_mode_config structure
*/ */
#ifndef PM_RUN_MODE_CFG #ifndef PM_RUN_MODE_CFG
#define PM_RUN_MODE_CFG \ #define PM_RUN_MODE_CFG \
{ \ { \
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
} }
#endif /* PM_RUN_MODE_CFG */ #endif /* PM_RUN_MODE_CFG */
@@ -40,50 +40,50 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure * @brief sleep idle config @ref pm_sleep_mode_idle_config structure
*/ */
#ifndef PM_SLEEP_IDLE_CFG #ifndef PM_SLEEP_IDLE_CFG
#define PM_SLEEP_IDLE_CFG \ #define PM_SLEEP_IDLE_CFG \
{ \ { \
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \ .pwc_sleep_type = PWC_SLEEP_WFE_INT, \
} }
#endif /*PM_SLEEP_IDLE_CFG*/ #endif /*PM_SLEEP_IDLE_CFG*/
/** /**
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure * @brief sleep deep config @ref pm_sleep_mode_deep_config structure
*/ */
#ifndef PM_SLEEP_DEEP_CFG #ifndef PM_SLEEP_DEEP_CFG
#define PM_SLEEP_DEEP_CFG \ #define PM_SLEEP_DEEP_CFG \
{ \ { \
{ \ { \
.u16Clock = PWC_STOP_CLK_KEEP, \ .u16Clock = PWC_STOP_CLK_KEEP, \
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
}, \ }, \
.pwc_stop_type = PWC_STOP_WFE_INT, \ .pwc_stop_type = PWC_STOP_WFE_INT, \
} }
#endif /*PM_SLEEP_DEEP_CFG*/ #endif /*PM_SLEEP_DEEP_CFG*/
/** /**
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure * @brief sleep standby config @ref pm_sleep_mode_standby_config structure
*/ */
#ifndef PM_SLEEP_STANDBY_CFG #ifndef PM_SLEEP_STANDBY_CFG
#define PM_SLEEP_STANDBY_CFG \ #define PM_SLEEP_STANDBY_CFG \
{ \ { \
{ \ { \
.u8Mode = PWC_PD_MD1, \ .u8Mode = PWC_PD_MD1, \
.u8IOState = PWC_PD_IO_KEEP1, \ .u8IOState = PWC_PD_IO_KEEP1, \
}, \ }, \
} }
#endif /*PM_SLEEP_STANDBY_CFG*/ #endif /*PM_SLEEP_STANDBY_CFG*/
/** /**
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
*/ */
#ifndef PM_SLEEP_SHUTDOWN_CFG #ifndef PM_SLEEP_SHUTDOWN_CFG
#define PM_SLEEP_SHUTDOWN_CFG \ #define PM_SLEEP_SHUTDOWN_CFG \
{ \ { \
{ \ { \
.u8Mode = PWC_PD_MD3, \ .u8Mode = PWC_PD_MD3, \
.u8IOState = PWC_PD_IO_KEEP1, \ .u8IOState = PWC_PD_IO_KEEP1, \
}, \ }, \
} }
#endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /*PM_SLEEP_SHUTDOWN_CFG*/
#endif /* BSP_USING_PM */ #endif /* BSP_USING_PM */
bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h
+126 -140
View File
@@ -21,182 +21,168 @@ extern "C" {
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifdef BSP_USING_PULSE_ENCODER_TMRA_1
#ifndef PULSE_ENCODER_TMRA_1_CONFIG #ifndef PULSE_ENCODER_TMRA_1_CONFIG
#define PULSE_ENCODER_TMRA_1_CONFIG \ #define PULSE_ENCODER_TMRA_1_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_1, \ .tmr_handler = CM_TMRA_1, \
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \ .u32PeriphClock = FCG2_PERIPH_TMRA_1, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a1" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a1" \
} }
#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* PULSE_ENCODER_TMRA_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifdef BSP_USING_PULSE_ENCODER_TMRA_2
#ifndef PULSE_ENCODER_TMRA_2_CONFIG #ifndef PULSE_ENCODER_TMRA_2_CONFIG
#define PULSE_ENCODER_TMRA_2_CONFIG \ #define PULSE_ENCODER_TMRA_2_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_2, \ .tmr_handler = CM_TMRA_2, \
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \ .u32PeriphClock = FCG2_PERIPH_TMRA_2, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a2" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a2" \
} }
#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* PULSE_ENCODER_TMRA_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifdef BSP_USING_PULSE_ENCODER_TMRA_3
#ifndef PULSE_ENCODER_TMRA_3_CONFIG #ifndef PULSE_ENCODER_TMRA_3_CONFIG
#define PULSE_ENCODER_TMRA_3_CONFIG \ #define PULSE_ENCODER_TMRA_3_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_3, \ .tmr_handler = CM_TMRA_3, \
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \ .u32PeriphClock = FCG2_PERIPH_TMRA_3, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a3" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a3" \
} }
#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* PULSE_ENCODER_TMRA_3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifdef BSP_USING_PULSE_ENCODER_TMRA_4
#ifndef PULSE_ENCODER_TMRA_4_CONFIG #ifndef PULSE_ENCODER_TMRA_4_CONFIG
#define PULSE_ENCODER_TMRA_4_CONFIG \ #define PULSE_ENCODER_TMRA_4_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_4, \ .tmr_handler = CM_TMRA_4, \
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \ .u32PeriphClock = FCG2_PERIPH_TMRA_4, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a4" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a4" \
} }
#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* PULSE_ENCODER_TMRA_4_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifdef BSP_USING_PULSE_ENCODER_TMRA_5
#ifndef PULSE_ENCODER_TMRA_5_CONFIG #ifndef PULSE_ENCODER_TMRA_5_CONFIG
#define PULSE_ENCODER_TMRA_5_CONFIG \ #define PULSE_ENCODER_TMRA_5_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_5, \ .tmr_handler = CM_TMRA_5, \
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \ .u32PeriphClock = FCG2_PERIPH_TMRA_5, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a5" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a5" \
} }
#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* PULSE_ENCODER_TMRA_5_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifdef BSP_USING_PULSE_ENCODER_TMR6_1
#ifndef PULSE_ENCODER_TMR6_1_CONFIG #ifndef PULSE_ENCODER_TMR6_1_CONFIG
#define PULSE_ENCODER_TMR6_1_CONFIG \ #define PULSE_ENCODER_TMR6_1_CONFIG \
{ \ { \
.tmr_handler = CM_TMR6_1, \ .tmr_handler = CM_TMR6_1, \
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \ .u32PeriphClock = FCG2_PERIPH_TMR6_1, \
.hw_count = \ .hw_count = { \
{ \ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_61" \
.u32PeriodValue = 1000UL, \
.name = "pulse_61" \
} }
#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* PULSE_ENCODER_TMR6_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifdef BSP_USING_PULSE_ENCODER_TMR6_2
#ifndef PULSE_ENCODER_TMR6_2_CONFIG #ifndef PULSE_ENCODER_TMR6_2_CONFIG
#define PULSE_ENCODER_TMR6_2_CONFIG \ #define PULSE_ENCODER_TMR6_2_CONFIG \
{ \ { \
.tmr_handler = CM_TMR6_2, \ .tmr_handler = CM_TMR6_2, \
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \ .u32PeriphClock = FCG2_PERIPH_TMR6_2, \
.hw_count = \ .hw_count = { \
{ \ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_62" \
.u32PeriodValue = 1000UL, \
.name = "pulse_62" \
} }
#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* PULSE_ENCODER_TMR6_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h
+276 -319
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File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h
+37 -40
View File
@@ -21,58 +21,55 @@ extern "C" {
#ifdef BSP_USING_SPI1 #ifdef BSP_USING_SPI1
#ifndef SPI1_BUS_CONFIG #ifndef SPI1_BUS_CONFIG
#define SPI1_BUS_CONFIG \ #define SPI1_BUS_CONFIG \
{ \ { \
.Instance = CM_SPI, \ .Instance = CM_SPI, \
.bus_name = "spi1", \ .bus_name = "spi1", \
.clock = FCG1_PERIPH_SPI, \ .clock = FCG1_PERIPH_SPI, \
.timeout = 5000UL, \ .timeout = 5000UL, \
.err_irq.irq_config = \ .err_irq.irq_config = { \
{ \ .irq_num = BSP_SPI1_ERR_IRQ_NUM, \
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \ .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ .int_src = INT_SRC_SPI_SPEI, \
.int_src = INT_SRC_SPI_SPEI, \ }, \
}, \
} }
#endif /* SPI1_BUS_CONFIG */ #endif /* SPI1_BUS_CONFIG */
#endif /* BSP_USING_SPI1 */ #endif /* BSP_USING_SPI1 */
#ifdef BSP_SPI1_TX_USING_DMA #ifdef BSP_SPI1_TX_USING_DMA
#ifndef SPI1_TX_DMA_CONFIG #ifndef SPI1_TX_DMA_CONFIG
#define SPI1_TX_DMA_CONFIG \ #define SPI1_TX_DMA_CONFIG \
{ \ { \
.Instance = SPI1_TX_DMA_INSTANCE, \ .Instance = SPI1_TX_DMA_INSTANCE, \
.channel = SPI1_TX_DMA_CHANNEL, \ .channel = SPI1_TX_DMA_CHANNEL, \
.clock = SPI1_TX_DMA_CLOCK, \ .clock = SPI1_TX_DMA_CLOCK, \
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI_SPTI, \ .trigger_event = EVT_SRC_SPI_SPTI, \
.flag = SPI1_TX_DMA_TRANS_FLAG, \ .flag = SPI1_TX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = SPI1_TX_DMA_IRQn, \
.irq_num = SPI1_TX_DMA_IRQn, \ .irq_prio = SPI1_TX_DMA_INT_PRIO, \
.irq_prio = SPI1_TX_DMA_INT_PRIO, \ .int_src = SPI1_TX_DMA_INT_SRC, \
.int_src = SPI1_TX_DMA_INT_SRC, \ } \
} \
} }
#endif /* SPI1_TX_DMA_CONFIG */ #endif /* SPI1_TX_DMA_CONFIG */
#endif /* BSP_SPI1_TX_USING_DMA */ #endif /* BSP_SPI1_TX_USING_DMA */
#ifdef BSP_SPI1_RX_USING_DMA #ifdef BSP_SPI1_RX_USING_DMA
#ifndef SPI1_RX_DMA_CONFIG #ifndef SPI1_RX_DMA_CONFIG
#define SPI1_RX_DMA_CONFIG \ #define SPI1_RX_DMA_CONFIG \
{ \ { \
.Instance = SPI1_RX_DMA_INSTANCE, \ .Instance = SPI1_RX_DMA_INSTANCE, \
.channel = SPI1_RX_DMA_CHANNEL, \ .channel = SPI1_RX_DMA_CHANNEL, \
.clock = SPI1_RX_DMA_CLOCK, \ .clock = SPI1_RX_DMA_CLOCK, \
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_SPI_SPRI, \ .trigger_event = EVT_SRC_SPI_SPRI, \
.flag = SPI1_RX_DMA_TRANS_FLAG, \ .flag = SPI1_RX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = SPI1_RX_DMA_IRQn, \
.irq_num = SPI1_RX_DMA_IRQn, \ .irq_prio = SPI1_RX_DMA_INT_PRIO, \
.irq_prio = SPI1_RX_DMA_INT_PRIO, \ .int_src = SPI1_RX_DMA_INT_SRC, \
.int_src = SPI1_RX_DMA_INT_SRC, \ } \
} \
} }
#endif /* SPI1_RX_DMA_CONFIG */ #endif /* SPI1_RX_DMA_CONFIG */
#endif /* BSP_SPI1_RX_USING_DMA */ #endif /* BSP_SPI1_RX_USING_DMA */
bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h
+60 -65
View File
@@ -19,95 +19,90 @@ extern "C" {
#ifdef BSP_USING_TMRA_1 #ifdef BSP_USING_TMRA_1
#ifndef TMRA_1_CONFIG #ifndef TMRA_1_CONFIG
#define TMRA_1_CONFIG \ #define TMRA_1_CONFIG \
{ \ { \
.tmr_handle = CM_TMRA_1, \ .tmr_handle = CM_TMRA_1, \
.clock_source = CLK_BUS_PCLK0, \ .clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_1, \ .clock = FCG2_PERIPH_TMRA_1, \
.flag = TMRA_FLAG_OVF, \ .flag = TMRA_FLAG_OVF, \
.isr = \ .isr = { \
{ \ .enIntSrc = INT_SRC_TMRA_1_OVF, \
.enIntSrc = INT_SRC_TMRA_1_OVF, \ .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ }, \
}, \ .name = "tmra_1" \
.name = "tmra_1" \
} }
#endif /* TMRA_1_CONFIG */ #endif /* TMRA_1_CONFIG */
#endif /* BSP_USING_TMRA_1 */ #endif /* BSP_USING_TMRA_1 */
#ifdef BSP_USING_TMRA_2 #ifdef BSP_USING_TMRA_2
#ifndef TMRA_2_CONFIG #ifndef TMRA_2_CONFIG
#define TMRA_2_CONFIG \ #define TMRA_2_CONFIG \
{ \ { \
.tmr_handle = CM_TMRA_2, \ .tmr_handle = CM_TMRA_2, \
.clock_source = CLK_BUS_PCLK0, \ .clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_2, \ .clock = FCG2_PERIPH_TMRA_2, \
.flag = TMRA_FLAG_OVF, \ .flag = TMRA_FLAG_OVF, \
.isr = \ .isr = { \
{ \ .enIntSrc = INT_SRC_TMRA_2_OVF, \
.enIntSrc = INT_SRC_TMRA_2_OVF, \ .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ }, \
}, \ .name = "tmra_2" \
.name = "tmra_2" \
} }
#endif /* TMRA_2_CONFIG */ #endif /* TMRA_2_CONFIG */
#endif /* BSP_USING_TMRA_2 */ #endif /* BSP_USING_TMRA_2 */
#ifdef BSP_USING_TMRA_3 #ifdef BSP_USING_TMRA_3
#ifndef TMRA_3_CONFIG #ifndef TMRA_3_CONFIG
#define TMRA_3_CONFIG \ #define TMRA_3_CONFIG \
{ \ { \
.tmr_handle = CM_TMRA_3, \ .tmr_handle = CM_TMRA_3, \
.clock_source = CLK_BUS_PCLK0, \ .clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_3, \ .clock = FCG2_PERIPH_TMRA_3, \
.flag = TMRA_FLAG_OVF, \ .flag = TMRA_FLAG_OVF, \
.isr = \ .isr = { \
{ \ .enIntSrc = INT_SRC_TMRA_3_OVF, \
.enIntSrc = INT_SRC_TMRA_3_OVF, \ .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ }, \
}, \ .name = "tmra_3" \
.name = "tmra_3" \
} }
#endif /* TMRA_3_CONFIG */ #endif /* TMRA_3_CONFIG */
#endif /* BSP_USING_TMRA_3 */ #endif /* BSP_USING_TMRA_3 */
#ifdef BSP_USING_TMRA_4 #ifdef BSP_USING_TMRA_4
#ifndef TMRA_4_CONFIG #ifndef TMRA_4_CONFIG
#define TMRA_4_CONFIG \ #define TMRA_4_CONFIG \
{ \ { \
.tmr_handle = CM_TMRA_4, \ .tmr_handle = CM_TMRA_4, \
.clock_source = CLK_BUS_PCLK0, \ .clock_source = CLK_BUS_PCLK0, \
.clock = FCG2_PERIPH_TMRA_4, \ .clock = FCG2_PERIPH_TMRA_4, \
.flag = TMRA_FLAG_OVF, \ .flag = TMRA_FLAG_OVF, \
.isr = \ .isr = { \
{ \ .enIntSrc = INT_SRC_TMRA_4_OVF, \
.enIntSrc = INT_SRC_TMRA_4_OVF, \ .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ }, \
}, \ .name = "tmra_4" \
.name = "tmra_4" \
} }
#endif /* TMRA_4_CONFIG */ #endif /* TMRA_4_CONFIG */
#endif /* BSP_USING_TMRA_4 */ #endif /* BSP_USING_TMRA_4 */
#ifdef BSP_USING_TMRA_5 #ifdef BSP_USING_TMRA_5
#ifndef TMRA_5_CONFIG #ifndef TMRA_5_CONFIG
#define TMRA_5_CONFIG \ #define TMRA_5_CONFIG \
{ \ { \
.tmr_handle = CM_TMRA_5, \ .tmr_handle = CM_TMRA_5, \
.clock_source = CLK_BUS_PCLK1, \ .clock_source = CLK_BUS_PCLK1, \
.clock = FCG2_PERIPH_TMRA_5, \ .clock = FCG2_PERIPH_TMRA_5, \
.flag = TMRA_FLAG_OVF, \ .flag = TMRA_FLAG_OVF, \
.isr = \ .isr = { \
{ \ .enIntSrc = INT_SRC_TMRA_5_OVF, \
.enIntSrc = INT_SRC_TMRA_5_OVF, \ .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ }, \
}, \ .name = "tmra_5" \
.name = "tmra_5" \
} }
#endif /* TMRA_5_CONFIG */ #endif /* TMRA_5_CONFIG */
#endif /* BSP_USING_TMRA_5 */ #endif /* BSP_USING_TMRA_5 */
bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h
+48 -48
View File
@@ -17,64 +17,64 @@
extern "C" { extern "C" {
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
#define IC1_NAME "ic1" #define IC1_NAME "ic1"
#define INPUT_CAPTURE_CFG_TMR6_1 \ #define INPUT_CAPTURE_CFG_TMR6_1 \
{ \ { \
.name = IC1_NAME, \ .name = IC1_NAME, \
.ch = TMR6_CH_A, \ .ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \ .clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \ .first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \
} }
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
#define IC2_NAME "ic2" #define IC2_NAME "ic2"
#define INPUT_CAPTURE_CFG_TMR6_2 \ #define INPUT_CAPTURE_CFG_TMR6_2 \
{ \ { \
.name = IC2_NAME, \ .name = IC2_NAME, \
.ch = TMR6_CH_A, \ .ch = TMR6_CH_A, \
.clk_div = TMR6_CLK_DIV32, \ .clk_div = TMR6_CLK_DIV32, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \ .first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \
} }
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3)
#define IC3_NAME "ic3" #define IC3_NAME "ic3"
#define INPUT_CAPTURE_CFG_TMR6_3 \ #define INPUT_CAPTURE_CFG_TMR6_3 \
{ \ { \
.name = IC3_NAME, \ .name = IC3_NAME, \
.ch = TMR6_CH_B, \ .ch = TMR6_CH_B, \
.clk_div = TMR6_CLK_DIV16, \ .clk_div = TMR6_CLK_DIV16, \
.first_edge = TMR6_CAPT_COND_TRIGD_RISING, \ .first_edge = TMR6_CAPT_COND_TRIGD_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \
} }
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_4) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_4)
#define IC4_NAME "ic4" #define IC4_NAME "ic4"
#define INPUT_CAPTURE_CFG_TMR6_4 \ #define INPUT_CAPTURE_CFG_TMR6_4 \
{ \ { \
.name = IC4_NAME, \ .name = IC4_NAME, \
.ch = TMR6_CH_B, \ .ch = TMR6_CH_B, \
.clk_div = TMR6_CLK_DIV16, \ .clk_div = TMR6_CLK_DIV16, \
.first_edge = TMR6_CAPT_COND_PWMA_RISING, \ .first_edge = TMR6_CAPT_COND_PWMA_RISING, \
.irq_num_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM, \ .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM, \
.irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO, \ .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO, \
.irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM, \ .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM, \
.irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO, \ .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO, \
} }
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h
+220 -236
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h
+42 -43
View File
@@ -27,8 +27,7 @@
/* C binding of definitions if building with C++ compiler */ /* C binding of definitions if building with C++ compiler */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" extern "C" {
{
#endif #endif
/******************************************************************************* /*******************************************************************************
@@ -48,48 +47,48 @@ extern "C"
* Library. * Library.
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
*/ */
#define LL_ICG_ENABLE (DDL_ON) #define LL_ICG_ENABLE (DDL_ON)
#define LL_UTILITY_ENABLE (DDL_ON) #define LL_UTILITY_ENABLE (DDL_ON)
#define LL_PRINT_ENABLE (DDL_OFF) #define LL_PRINT_ENABLE (DDL_OFF)
#define LL_ADC_ENABLE (DDL_ON) #define LL_ADC_ENABLE (DDL_ON)
#define LL_AOS_ENABLE (DDL_ON) #define LL_AOS_ENABLE (DDL_ON)
#define LL_CLK_ENABLE (DDL_ON) #define LL_CLK_ENABLE (DDL_ON)
#define LL_CMP_ENABLE (DDL_ON) #define LL_CMP_ENABLE (DDL_ON)
#define LL_CRC_ENABLE (DDL_ON) #define LL_CRC_ENABLE (DDL_ON)
#define LL_CTC_ENABLE (DDL_ON) #define LL_CTC_ENABLE (DDL_ON)
#define LL_DAC_ENABLE (DDL_ON) #define LL_DAC_ENABLE (DDL_ON)
#define LL_DBGC_ENABLE (DDL_OFF) #define LL_DBGC_ENABLE (DDL_OFF)
#define LL_DMA_ENABLE (DDL_ON) #define LL_DMA_ENABLE (DDL_ON)
#define LL_EFM_ENABLE (DDL_ON) #define LL_EFM_ENABLE (DDL_ON)
#define LL_EMB_ENABLE (DDL_ON) #define LL_EMB_ENABLE (DDL_ON)
#define LL_EVENT_PORT_ENABLE (DDL_OFF) #define LL_EVENT_PORT_ENABLE (DDL_OFF)
#define LL_FCG_ENABLE (DDL_ON) #define LL_FCG_ENABLE (DDL_ON)
#define LL_FCM_ENABLE (DDL_ON) #define LL_FCM_ENABLE (DDL_ON)
#define LL_HRPWM_ENABLE (DDL_ON) #define LL_HRPWM_ENABLE (DDL_ON)
#define LL_GPIO_ENABLE (DDL_ON) #define LL_GPIO_ENABLE (DDL_ON)
#define LL_I2C_ENABLE (DDL_ON) #define LL_I2C_ENABLE (DDL_ON)
#define LL_INTERRUPTS_ENABLE (DDL_ON) #define LL_INTERRUPTS_ENABLE (DDL_ON)
#define LL_MCAN_ENABLE (DDL_ON) #define LL_MCAN_ENABLE (DDL_ON)
#define LL_MPU_ENABLE (DDL_ON) #define LL_MPU_ENABLE (DDL_ON)
#define LL_PLA_ENABLE (DDL_ON) #define LL_PLA_ENABLE (DDL_ON)
#define LL_PWC_ENABLE (DDL_ON) #define LL_PWC_ENABLE (DDL_ON)
#define LL_RMU_ENABLE (DDL_ON) #define LL_RMU_ENABLE (DDL_ON)
#define LL_RTC_ENABLE (DDL_ON) #define LL_RTC_ENABLE (DDL_ON)
#define LL_SPI_ENABLE (DDL_ON) #define LL_SPI_ENABLE (DDL_ON)
#define LL_SRAM_ENABLE (DDL_ON) #define LL_SRAM_ENABLE (DDL_ON)
#define LL_SWDT_ENABLE (DDL_ON) #define LL_SWDT_ENABLE (DDL_ON)
#define LL_TMR0_ENABLE (DDL_ON) #define LL_TMR0_ENABLE (DDL_ON)
#define LL_TMR4_ENABLE (DDL_ON) #define LL_TMR4_ENABLE (DDL_ON)
#define LL_TMR6_ENABLE (DDL_ON) #define LL_TMR6_ENABLE (DDL_ON)
#define LL_TMRA_ENABLE (DDL_ON) #define LL_TMRA_ENABLE (DDL_ON)
#define LL_USART_ENABLE (DDL_ON) #define LL_USART_ENABLE (DDL_ON)
#define LL_WDT_ENABLE (DDL_ON) #define LL_WDT_ENABLE (DDL_ON)
/** /**
* @brief The following is a list of currently supported BSP boards. * @brief The following is a list of currently supported BSP boards.
*/ */
#define BSP_EV_HC32F334_LQFP64 (1U) #define BSP_EV_HC32F334_LQFP64 (1U)
/** /**
* @brief The macro BSP_EV_HC32F3XX is used to specify the BSP board currently * @brief The macro BSP_EV_HC32F3XX is used to specify the BSP board currently
@@ -98,15 +97,15 @@ extern "C"
* @note If there is no supported BSP board or the BSP function is not used, * @note If there is no supported BSP board or the BSP function is not used,
* the value needs to be set to 0U. * the value needs to be set to 0U.
*/ */
#define BSP_EV_HC32F3XX (0U) #define BSP_EV_HC32F3XX (0U)
/** /**
* @brief This is the list of BSP components to be used. * @brief This is the list of BSP components to be used.
* Select the components you need to use to DDL_ON. * Select the components you need to use to DDL_ON.
*/ */
#define BSP_24CXX_ENABLE (DDL_OFF) #define BSP_24CXX_ENABLE (DDL_OFF)
#define BSP_W25QXX_ENABLE (DDL_OFF) #define BSP_W25QXX_ENABLE (DDL_OFF)
#define BSP_INT_KEY_ENABLE (DDL_OFF) #define BSP_INT_KEY_ENABLE (DDL_OFF)
/******************************************************************************* /*******************************************************************************
* Global variable definitions ('extern') * Global variable definitions ('extern')
bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h
+10 -10
View File
@@ -23,20 +23,20 @@ extern const struct fal_flash_dev hc32_onchip_flash;
extern struct fal_flash_dev ext_nor_flash0; extern struct fal_flash_dev ext_nor_flash0;
/* flash device table */ /* flash device table */
#define FAL_FLASH_DEV_TABLE \ #define FAL_FLASH_DEV_TABLE \
{ \ { \
&hc32_onchip_flash, \ &hc32_onchip_flash, \
&ext_nor_flash0, \ &ext_nor_flash0, \
} }
/* ====================== Partition Configuration ========================== */ /* ====================== Partition Configuration ========================== */
#ifdef FAL_PART_HAS_TABLE_CFG #ifdef FAL_PART_HAS_TABLE_CFG
/* partition table */ /* partition table */
#define FAL_PART_TABLE \ #define FAL_PART_TABLE \
{ \ { \
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0}, \ { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0 }, \
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \
} }
#endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* FAL_PART_HAS_TABLE_CFG */
#endif /* _FAL_CFG_H_ */ #endif /* _FAL_CFG_H_ */
bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h
+1 -9
View File
@@ -72,7 +72,7 @@
#define RT_HOOK_USING_FUNC_PTR #define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK #define RT_USING_IDLE_HOOK
#define RT_IDLE_HOOK_LIST_SIZE 4 #define RT_IDLE_HOOK_LIST_SIZE 4
#define IDLE_THREAD_STACK_SIZE 256 #define IDLE_THREAD_STACK_SIZE 512
/* kservice options */ /* kservice options */
@@ -326,14 +326,6 @@
/* GD32 Drivers */ /* GD32 Drivers */
/* end of GD32 Drivers */ /* end of GD32 Drivers */
/* HPMicro SDK */
/* end of HPMicro SDK */
/* FT32 HAL & SDK Drivers */
/* end of FT32 HAL & SDK Drivers */
/* end of HAL & SDK Drivers */ /* end of HAL & SDK Drivers */
/* sensors drivers */ /* sensors drivers */
bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml
+4 -4
View File
@@ -22,11 +22,11 @@ devices.flash:
- CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SPI=y
- CONFIG_RT_USING_SFUD=y - CONFIG_RT_USING_SFUD=y
devices.gpio: devices.gpio:
kconfig:
- CONFIG_BSP_USING_GPIO=y
devices.hwtimer:
kconfig: kconfig:
- CONFIG_BSP_USING_HWTIMER=y - CONFIG_BSP_USING_GPIO=y
devices.clock_timer:
kconfig:
- CONFIG_BSP_USING_CLOCK_TIMER=y
- CONFIG_BSP_USING_TMRA_1=y - CONFIG_BSP_USING_TMRA_1=y
devices.i2c: devices.i2c:
kconfig: kconfig:
bsp/hc32/ev_hc32f448_lqfp80/.config
+1 -1
View File
@@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set # CONFIG_RT_USING_HOOKLIST is not set
CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256 CONFIG_IDLE_THREAD_STACK_SIZE=512
# CONFIG_RT_USING_TIMER_SOFT is not set # CONFIG_RT_USING_TIMER_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set
bsp/hc32/ev_hc32f448_lqfp80/README.md
+1 -1
View File
@@ -47,7 +47,7 @@ EV_F448_LQ80 开发板常用 **板载资源** 如下：
| DAC | 支持 | | | DAC | 支持 | |
| FLASH | 支持 | | | FLASH | 支持 | |
| GPIO | 支持 | PA0，PA1...PH2 ---> PIN：0，1...82 | | GPIO | 支持 | PA0，PA1...PH2 ---> PIN：0，1...82 |
| HwTimer | 支持 | | | CLOCK_TIMER | 支持 | |
| I2C | 支持 | 软件、硬件 I2C | | I2C | 支持 | 软件、硬件 I2C |
| InputCapture | 支持 | | | InputCapture | 支持 | |
| MCAN | 支持 | | | MCAN | 支持 | |
bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c
+7 -7
View File
@@ -19,7 +19,7 @@
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
#define XTAL32_FCM_THREAD_STACK_SIZE (1024) #define XTAL32_FCM_THREAD_STACK_SIZE (1024)
/** /**
* @brief This thread is used to monitor whether XTAL32 is stable. * @brief This thread is used to monitor whether XTAL32 is stable.
@@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter)
/* FCM config */ /* FCM config */
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
(void)FCM_StructInit(&stcFcmInit); (void)FCM_StructInit(&stcFcmInit);
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
(void)FCM_Init(&stcFcmInit); (void)FCM_Init(&stcFcmInit);
/* Enable FCM, to ensure xtal32 stable */ /* Enable FCM, to ensure xtal32 stable */
FCM_Cmd(ENABLE); FCM_Cmd(ENABLE);
bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig
+6 -6
View File
@@ -641,24 +641,24 @@ menu "On-chip Peripheral Drivers"
endif endif
menuconfig BSP_USING_CLOCK_TIMER menuconfig BSP_USING_CLOCK_TIMER
bool "Enable Hw Timer" bool "Enable Clock Timer"
default n default n
select RT_USING_CLOCK_TIME select RT_USING_CLOCK_TIME
if BSP_USING_CLOCK_TIMER if BSP_USING_CLOCK_TIMER
config BSP_USING_TMRA_1 config BSP_USING_TMRA_1
bool "Use Timer_a1 As The Hw Timer" bool "Use Timer_a1 As The Clock Timer"
default n default n
config BSP_USING_TMRA_2 config BSP_USING_TMRA_2
bool "Use Timer_a2 As The Hw Timer" bool "Use Timer_a2 As The Clock Timer"
default n default n
config BSP_USING_TMRA_3 config BSP_USING_TMRA_3
bool "Use Timer_a3 As The Hw Timer" bool "Use Timer_a3 As The Clock Timer"
default n default n
config BSP_USING_TMRA_4 config BSP_USING_TMRA_4
bool "Use Timer_a4 As The Hw Timer" bool "Use Timer_a4 As The Clock Timer"
default n default n
config BSP_USING_TMRA_5 config BSP_USING_TMRA_5
bool "Use Timer_a5 As The Hw Timer" bool "Use Timer_a5 As The Clock Timer"
default n default n
endif endif
bsp/hc32/ev_hc32f448_lqfp80/board/board.c
+8 -8
View File
@@ -14,9 +14,9 @@
#include "board_config.h" #include "board_config.h"
/* unlock/lock peripheral */ /* unlock/lock peripheral */
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ #define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD)
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) #define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
/** System Base Configuration /** System Base Configuration
*/ */
@@ -58,9 +58,9 @@ void SystemClock_Config(void)
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
(void)CLK_XtalStructInit(&stcXtalInit); (void)CLK_XtalStructInit(&stcXtalInit);
/* Config Xtal and enable Xtal */ /* Config Xtal and enable Xtal */
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8State = CLK_XTAL_ON;
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
(void)CLK_XtalInit(&stcXtalInit); (void)CLK_XtalInit(&stcXtalInit);
@@ -86,8 +86,8 @@ void SystemClock_Config(void)
/* Xtal32 config */ /* Xtal32 config */
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
(void)CLK_Xtal32StructInit(&stcXtal32Init); (void)CLK_Xtal32StructInit(&stcXtal32Init);
stcXtal32Init.u8State = CLK_XTAL32_ON; stcXtal32Init.u8State = CLK_XTAL32_ON;
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
(void)CLK_Xtal32Init(&stcXtal32Init); (void)CLK_Xtal32Init(&stcXtal32Init);
#endif #endif
bsp/hc32/ev_hc32f448_lqfp80/board/board.h
+12 -12
View File
@@ -20,27 +20,27 @@
extern "C" { extern "C" {
#endif #endif
#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) #define HC32_FLASH_ERASE_GRANULARITY (8 * 1024)
#define HC32_FLASH_WRITE_GRANULARITY (4) #define HC32_FLASH_WRITE_GRANULARITY (4)
#define HC32_FLASH_SIZE (256 * 1024) #define HC32_FLASH_SIZE (256 * 1024)
#define HC32_FLASH_START_ADDRESS (0) #define HC32_FLASH_START_ADDRESS (0)
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) #define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
#define HC32_SRAM_SIZE (64) #define HC32_SRAM_SIZE (64)
#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) #define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
#ifdef __ARMCC_VERSION #ifdef __ARMCC_VERSION
extern int Image$$RW_IRAM2$$ZI$$Limit; extern int Image$$RW_IRAM2$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
#elif __ICCARM__ #elif __ICCARM__
#pragma section="HEAP" #pragma section = "HEAP"
#define HEAP_BEGIN (__segment_end("HEAP")) #define HEAP_BEGIN (__segment_end("HEAP"))
#else #else
extern int __bss_end; extern int __bss_end;
#define HEAP_BEGIN (&__bss_end) #define HEAP_BEGIN (&__bss_end)
#endif #endif
#define HEAP_END HC32_SRAM_END #define HEAP_END HC32_SRAM_END
void PeripheralRegister_Unlock(void); void PeripheralRegister_Unlock(void);
void PeripheralClock_Config(void); void PeripheralClock_Config(void);
bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c
+10 -10
View File
@@ -184,7 +184,7 @@ rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx)
} }
#endif #endif
#if defined (RT_USING_SPI) #if defined(RT_USING_SPI)
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
{ {
rt_err_t result = RT_EOK; rt_err_t result = RT_EOK;
@@ -198,17 +198,17 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
case (rt_uint32_t)CM_SPI1: case (rt_uint32_t)CM_SPI1:
GPIO_StructInit(&stcGpioInit); GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinState = PIN_STAT_SET; stcGpioInit.u16PinState = PIN_STAT_SET;
stcGpioInit.u16PinDir = PIN_DIR_OUT; stcGpioInit.u16PinDir = PIN_DIR_OUT;
GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
(void)GPIO_StructInit(&stcGpioInit); (void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
(void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
break; break;
@@ -332,19 +332,19 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
#endif #endif
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE) #if defined(BSP_USING_INPUT_CAPTURE)
rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
{ {
rt_err_t result = RT_EOK; rt_err_t result = RT_EOK;
switch ((rt_uint32_t)tmr_instance) switch ((rt_uint32_t)tmr_instance)
{ {
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1)
case (rt_uint32_t)CM_TMR6_1: case (rt_uint32_t)CM_TMR6_1:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_1_FUNC); GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_1_FUNC);
break; break;
#endif #endif
#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2)
case (rt_uint32_t)CM_TMR6_2: case (rt_uint32_t)CM_TMR6_2:
GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_2_FUNC); GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_2_FUNC);
break; break;
@@ -358,7 +358,7 @@ rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance)
#endif #endif
#ifdef RT_USING_PM #ifdef RT_USING_PM
#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
{ {
switch (run_mode) switch (run_mode)
@@ -385,8 +385,8 @@ rt_err_t rt_hw_qspi_board_init(void)
(void)GPIO_StructInit(&stcGpioInit); (void)GPIO_StructInit(&stcGpioInit);
stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
#ifndef BSP_QSPI_USING_SOFT_CS #ifndef BSP_QSPI_USING_SOFT_CS
(void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit);
GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC);
#endif #endif
(void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
(void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);
bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h
+213 -213
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h
+93 -96
View File
@@ -20,42 +20,41 @@ extern "C" {
#ifdef BSP_USING_ADC1 #ifdef BSP_USING_ADC1
#ifndef ADC1_INIT_PARAMS #ifndef ADC1_INIT_PARAMS
#define ADC1_INIT_PARAMS \ #define ADC1_INIT_PARAMS \
{ \ { \
.name = "adc1", \ .name = "adc1", \
.vref = 3300, \ .vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \ .resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \ .data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \ .eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \ .hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \ .hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \ .internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \ .internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \ .internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \ .continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \ .data_reg_auto_clear = RT_TRUE, \
} }
#endif /* ADC1_INIT_PARAMS */ #endif /* ADC1_INIT_PARAMS */
#if defined (BSP_ADC1_USING_DMA) #if defined(BSP_ADC1_USING_DMA)
#ifndef ADC1_EOCA_DMA_CONFIG #ifndef ADC1_EOCA_DMA_CONFIG
#define ADC1_EOCA_DMA_CONFIG \ #define ADC1_EOCA_DMA_CONFIG \
{ \ { \
.Instance = ADC1_EOCA_DMA_INSTANCE, \ .Instance = ADC1_EOCA_DMA_INSTANCE, \
.channel = ADC1_EOCA_DMA_CHANNEL, \ .channel = ADC1_EOCA_DMA_CHANNEL, \
.clock = ADC1_EOCA_DMA_CLOCK, \ .clock = ADC1_EOCA_DMA_CLOCK, \
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC1_EOCA, \ .trigger_event = EVT_SRC_ADC1_EOCA, \
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \ .flag = ADC1_EOCA_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = ADC1_EOCA_DMA_IRQn, \
.irq_num = ADC1_EOCA_DMA_IRQn, \ .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ .int_src = ADC1_EOCA_DMA_INT_SRC, \
.int_src = ADC1_EOCA_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* ADC1_EOCA_DMA_CONFIG */ #endif /* ADC1_EOCA_DMA_CONFIG */
#endif /* BSP_ADC1_USING_DMA */ #endif /* BSP_ADC1_USING_DMA */
@@ -63,42 +62,41 @@ extern "C" {
#ifdef BSP_USING_ADC2 #ifdef BSP_USING_ADC2
#ifndef ADC2_INIT_PARAMS #ifndef ADC2_INIT_PARAMS
#define ADC2_INIT_PARAMS \ #define ADC2_INIT_PARAMS \
{ \ { \
.name = "adc2", \ .name = "adc2", \
.vref = 3300, \ .vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \ .resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \ .data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \ .eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \ .hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \ .hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \ .internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \ .internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \ .internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \ .continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \ .data_reg_auto_clear = RT_TRUE, \
} }
#endif /* ADC2_INIT_PARAMS */ #endif /* ADC2_INIT_PARAMS */
#if defined (BSP_ADC2_USING_DMA) #if defined(BSP_ADC2_USING_DMA)
#ifndef ADC2_EOCA_DMA_CONFIG #ifndef ADC2_EOCA_DMA_CONFIG
#define ADC2_EOCA_DMA_CONFIG \ #define ADC2_EOCA_DMA_CONFIG \
{ \ { \
.Instance = ADC2_EOCA_DMA_INSTANCE, \ .Instance = ADC2_EOCA_DMA_INSTANCE, \
.channel = ADC2_EOCA_DMA_CHANNEL, \ .channel = ADC2_EOCA_DMA_CHANNEL, \
.clock = ADC2_EOCA_DMA_CLOCK, \ .clock = ADC2_EOCA_DMA_CLOCK, \
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC2_EOCA, \ .trigger_event = EVT_SRC_ADC2_EOCA, \
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \ .flag = ADC2_EOCA_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = ADC2_EOCA_DMA_IRQn, \
.irq_num = ADC2_EOCA_DMA_IRQn, \ .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ .int_src = ADC2_EOCA_DMA_INT_SRC, \
.int_src = ADC2_EOCA_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* ADC2_EOCA_DMA_CONFIG */ #endif /* ADC2_EOCA_DMA_CONFIG */
#endif /* BSP_ADC2_USING_DMA */ #endif /* BSP_ADC2_USING_DMA */
@@ -106,42 +104,41 @@ extern "C" {
#ifdef BSP_USING_ADC3 #ifdef BSP_USING_ADC3
#ifndef ADC3_INIT_PARAMS #ifndef ADC3_INIT_PARAMS
#define ADC3_INIT_PARAMS \ #define ADC3_INIT_PARAMS \
{ \ { \
.name = "adc3", \ .name = "adc3", \
.vref = 3300, \ .vref = 3300, \
.resolution = ADC_RESOLUTION_12BIT, \ .resolution = ADC_RESOLUTION_12BIT, \
.data_align = ADC_DATAALIGN_RIGHT, \ .data_align = ADC_DATAALIGN_RIGHT, \
.eoc_poll_time_max = 100, \ .eoc_poll_time_max = 100, \
.hard_trig_enable = RT_FALSE, \ .hard_trig_enable = RT_FALSE, \
.hard_trig_src = ADC_HARDTRIG_EVT0, \ .hard_trig_src = ADC_HARDTRIG_EVT0, \
.internal_trig0_comtrg0_enable = RT_FALSE, \ .internal_trig0_comtrg0_enable = RT_FALSE, \
.internal_trig0_comtrg1_enable = RT_FALSE, \ .internal_trig0_comtrg1_enable = RT_FALSE, \
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \
.internal_trig1_comtrg0_enable = RT_FALSE, \ .internal_trig1_comtrg0_enable = RT_FALSE, \
.internal_trig1_comtrg1_enable = RT_FALSE, \ .internal_trig1_comtrg1_enable = RT_FALSE, \
.internal_trig1_sel = EVT_SRC_MAX, \ .internal_trig1_sel = EVT_SRC_MAX, \
.continue_conv_mode_enable = RT_FALSE, \ .continue_conv_mode_enable = RT_FALSE, \
.data_reg_auto_clear = RT_TRUE, \ .data_reg_auto_clear = RT_TRUE, \
} }
#endif /* ADC3_INIT_PARAMS */ #endif /* ADC3_INIT_PARAMS */
#if defined (BSP_ADC3_USING_DMA) #if defined(BSP_ADC3_USING_DMA)
#ifndef ADC3_EOCA_DMA_CONFIG #ifndef ADC3_EOCA_DMA_CONFIG
#define ADC3_EOCA_DMA_CONFIG \ #define ADC3_EOCA_DMA_CONFIG \
{ \ { \
.Instance = ADC3_EOCA_DMA_INSTANCE, \ .Instance = ADC3_EOCA_DMA_INSTANCE, \
.channel = ADC3_EOCA_DMA_CHANNEL, \ .channel = ADC3_EOCA_DMA_CHANNEL, \
.clock = ADC3_EOCA_DMA_CLOCK, \ .clock = ADC3_EOCA_DMA_CLOCK, \
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_ADC3_EOCA, \ .trigger_event = EVT_SRC_ADC3_EOCA, \
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \ .flag = ADC3_EOCA_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = ADC3_EOCA_DMA_IRQn, \
.irq_num = ADC3_EOCA_DMA_IRQn, \ .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ .int_src = ADC3_EOCA_DMA_INT_SRC, \
.int_src = ADC3_EOCA_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* ADC3_EOCA_DMA_CONFIG */ #endif /* ADC3_EOCA_DMA_CONFIG */
#endif /* BSP_ADC3_USING_DMA */ #endif /* BSP_ADC3_USING_DMA */
bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h
+12 -12
View File
@@ -19,18 +19,18 @@ extern "C" {
#ifdef BSP_USING_DAC1 #ifdef BSP_USING_DAC1
#ifndef DAC1_INIT_PARAMS #ifndef DAC1_INIT_PARAMS
#define DAC1_INIT_PARAMS \ #define DAC1_INIT_PARAMS \
{ \ { \
.name = "dac1", \ .name = "dac1", \
.vref = 3300, \ .vref = 3300, \
.dac_adp_enable = RT_FALSE, \ .dac_adp_enable = RT_FALSE, \
.dac_adp_sel = DAC_ADP_SEL_ALL, \ .dac_adp_sel = DAC_ADP_SEL_ALL, \
.ch1_output_enable = RT_TRUE, \ .ch1_output_enable = RT_TRUE, \
.ch2_output_enable = RT_TRUE, \ .ch2_output_enable = RT_TRUE, \
.ch1_data_src = DAC_DATA_SRC_DATAREG, \ .ch1_data_src = DAC_DATA_SRC_DATAREG, \
.ch2_data_src = DAC_DATA_SRC_DATAREG, \ .ch2_data_src = DAC_DATA_SRC_DATAREG, \
.ch1_amp_enable = RT_TRUE, \ .ch1_amp_enable = RT_TRUE, \
.ch2_amp_enable = RT_TRUE, \ .ch2_amp_enable = RT_TRUE, \
} }
#endif /* DAC1_INIT_PARAMS */ #endif /* DAC1_INIT_PARAMS */
#endif /* BSP_USING_DAC1 */ #endif /* BSP_USING_DAC1 */
bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h
+176 -176
View File
@@ -21,248 +21,248 @@ extern "C" {
/* DMA1 ch0 */ /* DMA1 ch0 */
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
#define SPI1_RX_DMA_INSTANCE CM_DMA1 #define SPI1_RX_DMA_INSTANCE CM_DMA1
#define SPI1_RX_DMA_CHANNEL DMA_CH0 #define SPI1_RX_DMA_CHANNEL DMA_CH0
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 #define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 #define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM #define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO #define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) #elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
#define SPI3_RX_DMA_INSTANCE CM_DMA1 #define SPI3_RX_DMA_INSTANCE CM_DMA1
#define SPI3_RX_DMA_CHANNEL DMA_CH0 #define SPI3_RX_DMA_CHANNEL DMA_CH0
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0 #define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0
#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 #define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM #define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO #define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
#define I2C1_TX_DMA_INSTANCE CM_DMA1 #define I2C1_TX_DMA_INSTANCE CM_DMA1
#define I2C1_TX_DMA_CHANNEL DMA_CH0 #define I2C1_TX_DMA_CHANNEL DMA_CH0
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 #define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 #define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM #define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO #define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 #define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
#endif #endif
/* DMA1 ch1 */ /* DMA1 ch1 */
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
#define SPI1_TX_DMA_INSTANCE CM_DMA1 #define SPI1_TX_DMA_INSTANCE CM_DMA1
#define SPI1_TX_DMA_CHANNEL DMA_CH1 #define SPI1_TX_DMA_CHANNEL DMA_CH1
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 #define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 #define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM #define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO #define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) #elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
#define SPI3_TX_DMA_INSTANCE CM_DMA1 #define SPI3_TX_DMA_INSTANCE CM_DMA1
#define SPI3_TX_DMA_CHANNEL DMA_CH1 #define SPI3_TX_DMA_CHANNEL DMA_CH1
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1 #define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1
#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 #define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM #define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO #define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
#define I2C1_RX_DMA_INSTANCE CM_DMA1 #define I2C1_RX_DMA_INSTANCE CM_DMA1
#define I2C1_RX_DMA_CHANNEL DMA_CH1 #define I2C1_RX_DMA_CHANNEL DMA_CH1
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 #define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 #define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM #define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO #define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 #define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
#endif #endif
/* DMA1 ch2 */ /* DMA1 ch2 */
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
#define SPI2_RX_DMA_INSTANCE CM_DMA1 #define SPI2_RX_DMA_INSTANCE CM_DMA1
#define SPI2_RX_DMA_CHANNEL DMA_CH2 #define SPI2_RX_DMA_CHANNEL DMA_CH2
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 #define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 #define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM #define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO #define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
#define I2C2_TX_DMA_INSTANCE CM_DMA1 #define I2C2_TX_DMA_INSTANCE CM_DMA1
#define I2C2_TX_DMA_CHANNEL DMA_CH2 #define I2C2_TX_DMA_CHANNEL DMA_CH2
#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 #define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 #define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM #define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO #define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 #define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
#endif #endif
/* DMA1 ch3 */ /* DMA1 ch3 */
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
#define SPI2_TX_DMA_INSTANCE CM_DMA1 #define SPI2_TX_DMA_INSTANCE CM_DMA1
#define SPI2_TX_DMA_CHANNEL DMA_CH3 #define SPI2_TX_DMA_CHANNEL DMA_CH3
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 #define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 #define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM #define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO #define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
#define I2C2_RX_DMA_INSTANCE CM_DMA1 #define I2C2_RX_DMA_INSTANCE CM_DMA1
#define I2C2_RX_DMA_CHANNEL DMA_CH3 #define I2C2_RX_DMA_CHANNEL DMA_CH3
#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 #define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 #define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM #define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO #define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 #define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 #define ADC1_EOCA_DMA_INSTANCE CM_DMA1
#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 #define ADC1_EOCA_DMA_CHANNEL DMA_CH3
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 #define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 #define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM #define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO #define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 #define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3
#endif #endif
/* DMA1 ch4 */ /* DMA1 ch4 */
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) #if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
#define UART5_RX_DMA_INSTANCE CM_DMA1 #define UART5_RX_DMA_INSTANCE CM_DMA1
#define UART5_RX_DMA_CHANNEL DMA_CH4 #define UART5_RX_DMA_CHANNEL DMA_CH4
#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4 #define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4
#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 #define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM #define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO #define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 #define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 #define ADC2_EOCA_DMA_INSTANCE CM_DMA1
#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 #define ADC2_EOCA_DMA_CHANNEL DMA_CH4
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 #define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 #define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM #define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO #define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 #define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4
#endif #endif
/* DMA1 ch5 */ /* DMA1 ch5 */
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
#define UART5_TX_DMA_INSTANCE CM_DMA1 #define UART5_TX_DMA_INSTANCE CM_DMA1
#define UART5_TX_DMA_CHANNEL DMA_CH5 #define UART5_TX_DMA_CHANNEL DMA_CH5
#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5 #define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5
#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 #define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM #define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO #define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 #define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 #define ADC3_EOCA_DMA_INSTANCE CM_DMA1
#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 #define ADC3_EOCA_DMA_CHANNEL DMA_CH5
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) #define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 #define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 #define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM #define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO #define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 #define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5
#endif #endif
/* DMA2 ch0 */ /* DMA2 ch0 */
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
#define UART1_RX_DMA_INSTANCE CM_DMA2 #define UART1_RX_DMA_INSTANCE CM_DMA2
#define UART1_RX_DMA_CHANNEL DMA_CH0 #define UART1_RX_DMA_CHANNEL DMA_CH0
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 #define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 #define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM #define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO #define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 #define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
#define QSPI_DMA_INSTANCE CM_DMA2 #define QSPI_DMA_INSTANCE CM_DMA2
#define QSPI_DMA_CHANNEL DMA_CH0 #define QSPI_DMA_CHANNEL DMA_CH0
#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0 #define QSPI_DMA_TRIG_SELECT AOS_DMA2_0
#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 #define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM #define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO #define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0 #define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0
#endif #endif
/* DMA2 ch1 */ /* DMA2 ch1 */
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
#define UART1_TX_DMA_INSTANCE CM_DMA2 #define UART1_TX_DMA_INSTANCE CM_DMA2
#define UART1_TX_DMA_CHANNEL DMA_CH1 #define UART1_TX_DMA_CHANNEL DMA_CH1
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 #define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 #define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM #define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO #define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
#endif #endif
/* DMA2 ch2 */ /* DMA2 ch2 */
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
#define UART2_RX_DMA_INSTANCE CM_DMA2 #define UART2_RX_DMA_INSTANCE CM_DMA2
#define UART2_RX_DMA_CHANNEL DMA_CH2 #define UART2_RX_DMA_CHANNEL DMA_CH2
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 #define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 #define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM #define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO #define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 #define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
#endif #endif
/* DMA2 ch3 */ /* DMA2 ch3 */
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
#define UART2_TX_DMA_INSTANCE CM_DMA2 #define UART2_TX_DMA_INSTANCE CM_DMA2
#define UART2_TX_DMA_CHANNEL DMA_CH3 #define UART2_TX_DMA_CHANNEL DMA_CH3
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 #define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 #define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM #define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO #define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
#endif #endif
/* DMA2 ch4 */ /* DMA2 ch4 */
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
#define UART4_RX_DMA_INSTANCE CM_DMA2 #define UART4_RX_DMA_INSTANCE CM_DMA2
#define UART4_RX_DMA_CHANNEL DMA_CH4 #define UART4_RX_DMA_CHANNEL DMA_CH4
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4 #define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 #define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM #define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO #define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 #define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
#endif #endif
/* DMA2 ch5 */ /* DMA2 ch5 */
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
#define UART4_TX_DMA_INSTANCE CM_DMA2 #define UART4_TX_DMA_INSTANCE CM_DMA2
#define UART4_TX_DMA_CHANNEL DMA_CH5 #define UART4_TX_DMA_CHANNEL DMA_CH5
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) #define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5 #define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 #define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM #define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO #define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 #define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h
+80 -80
View File
@@ -23,146 +23,146 @@ extern "C" {
#if defined(RT_USING_PIN) #if defined(RT_USING_PIN)
#ifndef EXTINT0_IRQ_CONFIG #ifndef EXTINT0_IRQ_CONFIG
#define EXTINT0_IRQ_CONFIG \ #define EXTINT0_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT0_IRQ_NUM, \ .irq_num = BSP_EXTINT0_IRQ_NUM, \
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \ .irq_prio = BSP_EXTINT0_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ0, \ .int_src = INT_SRC_PORT_EIRQ0, \
} }
#endif /* EXTINT1_IRQ_CONFIG */ #endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT1_IRQ_CONFIG #ifndef EXTINT1_IRQ_CONFIG
#define EXTINT1_IRQ_CONFIG \ #define EXTINT1_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT1_IRQ_NUM, \ .irq_num = BSP_EXTINT1_IRQ_NUM, \
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \ .irq_prio = BSP_EXTINT1_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ1, \ .int_src = INT_SRC_PORT_EIRQ1, \
} }
#endif /* EXTINT1_IRQ_CONFIG */ #endif /* EXTINT1_IRQ_CONFIG */
#ifndef EXTINT2_IRQ_CONFIG #ifndef EXTINT2_IRQ_CONFIG
#define EXTINT2_IRQ_CONFIG \ #define EXTINT2_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT2_IRQ_NUM, \ .irq_num = BSP_EXTINT2_IRQ_NUM, \
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \ .irq_prio = BSP_EXTINT2_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ2, \ .int_src = INT_SRC_PORT_EIRQ2, \
} }
#endif /* EXTINT2_IRQ_CONFIG */ #endif /* EXTINT2_IRQ_CONFIG */
#ifndef EXTINT3_IRQ_CONFIG #ifndef EXTINT3_IRQ_CONFIG
#define EXTINT3_IRQ_CONFIG \ #define EXTINT3_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT3_IRQ_NUM, \ .irq_num = BSP_EXTINT3_IRQ_NUM, \
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \ .irq_prio = BSP_EXTINT3_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ3, \ .int_src = INT_SRC_PORT_EIRQ3, \
} }
#endif /* EXTINT3_IRQ_CONFIG */ #endif /* EXTINT3_IRQ_CONFIG */
#ifndef EXTINT4_IRQ_CONFIG #ifndef EXTINT4_IRQ_CONFIG
#define EXTINT4_IRQ_CONFIG \ #define EXTINT4_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT4_IRQ_NUM, \ .irq_num = BSP_EXTINT4_IRQ_NUM, \
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \ .irq_prio = BSP_EXTINT4_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ4, \ .int_src = INT_SRC_PORT_EIRQ4, \
} }
#endif /* EXTINT4_IRQ_CONFIG */ #endif /* EXTINT4_IRQ_CONFIG */
#ifndef EXTINT5_IRQ_CONFIG #ifndef EXTINT5_IRQ_CONFIG
#define EXTINT5_IRQ_CONFIG \ #define EXTINT5_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT5_IRQ_NUM, \ .irq_num = BSP_EXTINT5_IRQ_NUM, \
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \ .irq_prio = BSP_EXTINT5_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ5, \ .int_src = INT_SRC_PORT_EIRQ5, \
} }
#endif /* EXTINT5_IRQ_CONFIG */ #endif /* EXTINT5_IRQ_CONFIG */
#ifndef EXTINT6_IRQ_CONFIG #ifndef EXTINT6_IRQ_CONFIG
#define EXTINT6_IRQ_CONFIG \ #define EXTINT6_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT6_IRQ_NUM, \ .irq_num = BSP_EXTINT6_IRQ_NUM, \
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \ .irq_prio = BSP_EXTINT6_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ6, \ .int_src = INT_SRC_PORT_EIRQ6, \
} }
#endif /* EXTINT6_IRQ_CONFIG */ #endif /* EXTINT6_IRQ_CONFIG */
#ifndef EXTINT7_IRQ_CONFIG #ifndef EXTINT7_IRQ_CONFIG
#define EXTINT7_IRQ_CONFIG \ #define EXTINT7_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT7_IRQ_NUM, \ .irq_num = BSP_EXTINT7_IRQ_NUM, \
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \ .irq_prio = BSP_EXTINT7_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ7, \ .int_src = INT_SRC_PORT_EIRQ7, \
} }
#endif /* EXTINT7_IRQ_CONFIG */ #endif /* EXTINT7_IRQ_CONFIG */
#ifndef EXTINT8_IRQ_CONFIG #ifndef EXTINT8_IRQ_CONFIG
#define EXTINT8_IRQ_CONFIG \ #define EXTINT8_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT8_IRQ_NUM, \ .irq_num = BSP_EXTINT8_IRQ_NUM, \
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \ .irq_prio = BSP_EXTINT8_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ8, \ .int_src = INT_SRC_PORT_EIRQ8, \
} }
#endif /* EXTINT8_IRQ_CONFIG */ #endif /* EXTINT8_IRQ_CONFIG */
#ifndef EXTINT9_IRQ_CONFIG #ifndef EXTINT9_IRQ_CONFIG
#define EXTINT9_IRQ_CONFIG \ #define EXTINT9_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT9_IRQ_NUM, \ .irq_num = BSP_EXTINT9_IRQ_NUM, \
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \ .irq_prio = BSP_EXTINT9_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ9, \ .int_src = INT_SRC_PORT_EIRQ9, \
} }
#endif /* EXTINT9_IRQ_CONFIG */ #endif /* EXTINT9_IRQ_CONFIG */
#ifndef EXTINT10_IRQ_CONFIG #ifndef EXTINT10_IRQ_CONFIG
#define EXTINT10_IRQ_CONFIG \ #define EXTINT10_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT10_IRQ_NUM, \ .irq_num = BSP_EXTINT10_IRQ_NUM, \
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \ .irq_prio = BSP_EXTINT10_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ10, \ .int_src = INT_SRC_PORT_EIRQ10, \
} }
#endif /* EXTINT10_IRQ_CONFIG */ #endif /* EXTINT10_IRQ_CONFIG */
#ifndef EXTINT11_IRQ_CONFIG #ifndef EXTINT11_IRQ_CONFIG
#define EXTINT11_IRQ_CONFIG \ #define EXTINT11_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT11_IRQ_NUM, \ .irq_num = BSP_EXTINT11_IRQ_NUM, \
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \ .irq_prio = BSP_EXTINT11_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ11, \ .int_src = INT_SRC_PORT_EIRQ11, \
} }
#endif /* EXTINT11_IRQ_CONFIG */ #endif /* EXTINT11_IRQ_CONFIG */
#ifndef EXTINT12_IRQ_CONFIG #ifndef EXTINT12_IRQ_CONFIG
#define EXTINT12_IRQ_CONFIG \ #define EXTINT12_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT12_IRQ_NUM, \ .irq_num = BSP_EXTINT12_IRQ_NUM, \
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \ .irq_prio = BSP_EXTINT12_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ12, \ .int_src = INT_SRC_PORT_EIRQ12, \
} }
#endif /* EXTINT12_IRQ_CONFIG */ #endif /* EXTINT12_IRQ_CONFIG */
#ifndef EXTINT13_IRQ_CONFIG #ifndef EXTINT13_IRQ_CONFIG
#define EXTINT13_IRQ_CONFIG \ #define EXTINT13_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT13_IRQ_NUM, \ .irq_num = BSP_EXTINT13_IRQ_NUM, \
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \ .irq_prio = BSP_EXTINT13_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ13, \ .int_src = INT_SRC_PORT_EIRQ13, \
} }
#endif /* EXTINT13_IRQ_CONFIG */ #endif /* EXTINT13_IRQ_CONFIG */
#ifndef EXTINT14_IRQ_CONFIG #ifndef EXTINT14_IRQ_CONFIG
#define EXTINT14_IRQ_CONFIG \ #define EXTINT14_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT14_IRQ_NUM, \ .irq_num = BSP_EXTINT14_IRQ_NUM, \
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \ .irq_prio = BSP_EXTINT14_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ14, \ .int_src = INT_SRC_PORT_EIRQ14, \
} }
#endif /* EXTINT14_IRQ_CONFIG */ #endif /* EXTINT14_IRQ_CONFIG */
#ifndef EXTINT15_IRQ_CONFIG #ifndef EXTINT15_IRQ_CONFIG
#define EXTINT15_IRQ_CONFIG \ #define EXTINT15_IRQ_CONFIG \
{ \ { \
.irq_num = BSP_EXTINT15_IRQ_NUM, \ .irq_num = BSP_EXTINT15_IRQ_NUM, \
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \ .irq_prio = BSP_EXTINT15_IRQ_PRIO, \
.int_src = INT_SRC_PORT_EIRQ15, \ .int_src = INT_SRC_PORT_EIRQ15, \
} }
#endif /* EXTINT15_IRQ_CONFIG */ #endif /* EXTINT15_IRQ_CONFIG */
bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h
+198 -210
View File
@@ -21,101 +21,97 @@ extern "C" {
#if defined(BSP_USING_I2C1) #if defined(BSP_USING_I2C1)
#ifndef I2C1_CONFIG #ifndef I2C1_CONFIG
#define I2C1_CONFIG \ #define I2C1_CONFIG \
{ \ { \
.name = "i2c1", \ .name = "i2c1", \
.Instance = CM_I2C1, \ .Instance = CM_I2C1, \
.clock = FCG1_PERIPH_I2C1, \ .clock = FCG1_PERIPH_I2C1, \
.baudrate = 100000UL, \ .baudrate = 100000UL, \
.timeout = 10000UL, \ .timeout = 10000UL, \
} }
#endif /* I2C1_CONFIG */ #endif /* I2C1_CONFIG */
#endif #endif
#if defined(BSP_I2C1_USING_DMA) #if defined(BSP_I2C1_USING_DMA)
#ifndef I2C1_TX_DMA_CONFIG #ifndef I2C1_TX_DMA_CONFIG
#define I2C1_TX_DMA_CONFIG \ #define I2C1_TX_DMA_CONFIG \
{ \ { \
.Instance = I2C1_TX_DMA_INSTANCE, \ .Instance = I2C1_TX_DMA_INSTANCE, \
.channel = I2C1_TX_DMA_CHANNEL, \ .channel = I2C1_TX_DMA_CHANNEL, \
.clock = I2C1_TX_DMA_CLOCK, \ .clock = I2C1_TX_DMA_CLOCK, \
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_TEI, \ .trigger_event = EVT_SRC_I2C1_TEI, \
.flag = I2C1_TX_DMA_TRANS_FLAG, \ .flag = I2C1_TX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C1_TX_DMA_IRQn, \
.irq_num = I2C1_TX_DMA_IRQn, \ .irq_prio = I2C1_TX_DMA_INT_PRIO, \
.irq_prio = I2C1_TX_DMA_INT_PRIO, \ .int_src = I2C1_TX_DMA_INT_SRC, \
.int_src = I2C1_TX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C1_TX_DMA_CONFIG */ #endif /* I2C1_TX_DMA_CONFIG */
#ifndef I2C1_RX_DMA_CONFIG #ifndef I2C1_RX_DMA_CONFIG
#define I2C1_RX_DMA_CONFIG \ #define I2C1_RX_DMA_CONFIG \
{ \ { \
.Instance = I2C1_RX_DMA_INSTANCE, \ .Instance = I2C1_RX_DMA_INSTANCE, \
.channel = I2C1_RX_DMA_CHANNEL, \ .channel = I2C1_RX_DMA_CHANNEL, \
.clock = I2C1_RX_DMA_CLOCK, \ .clock = I2C1_RX_DMA_CLOCK, \
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C1_RXI, \ .trigger_event = EVT_SRC_I2C1_RXI, \
.flag = I2C1_RX_DMA_TRANS_FLAG, \ .flag = I2C1_RX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C1_RX_DMA_IRQn, \
.irq_num = I2C1_RX_DMA_IRQn, \ .irq_prio = I2C1_RX_DMA_INT_PRIO, \
.irq_prio = I2C1_RX_DMA_INT_PRIO, \ .int_src = I2C1_RX_DMA_INT_SRC, \
.int_src = I2C1_RX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C1_RX_DMA_CONFIG */ #endif /* I2C1_RX_DMA_CONFIG */
#endif /* BSP_I2C1_USING_DMA */ #endif /* BSP_I2C1_USING_DMA */
#if defined(BSP_USING_I2C2) #if defined(BSP_USING_I2C2)
#ifndef I2C2_CONFIG #ifndef I2C2_CONFIG
#define I2C2_CONFIG \ #define I2C2_CONFIG \
{ \ { \
.name = "i2c2", \ .name = "i2c2", \
.Instance = CM_I2C2, \ .Instance = CM_I2C2, \
.clock = FCG1_PERIPH_I2C2, \ .clock = FCG1_PERIPH_I2C2, \
.baudrate = 100000UL, \ .baudrate = 100000UL, \
.timeout = 10000UL, \ .timeout = 10000UL, \
} }
#endif /* I2C2_CONFIG */ #endif /* I2C2_CONFIG */
#if defined(BSP_I2C2_USING_DMA) #if defined(BSP_I2C2_USING_DMA)
#ifndef I2C2_TX_DMA_CONFIG #ifndef I2C2_TX_DMA_CONFIG
#define I2C2_TX_DMA_CONFIG \ #define I2C2_TX_DMA_CONFIG \
{ \ { \
.Instance = I2C2_TX_DMA_INSTANCE, \ .Instance = I2C2_TX_DMA_INSTANCE, \
.channel = I2C2_TX_DMA_CHANNEL, \ .channel = I2C2_TX_DMA_CHANNEL, \
.clock = I2C2_TX_DMA_CLOCK, \ .clock = I2C2_TX_DMA_CLOCK, \
.trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_TEI, \ .trigger_event = EVT_SRC_I2C2_TEI, \
.flag = I2C2_TX_DMA_TRANS_FLAG, \ .flag = I2C2_TX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C2_TX_DMA_IRQn, \
.irq_num = I2C2_TX_DMA_IRQn, \ .irq_prio = I2C2_TX_DMA_INT_PRIO, \
.irq_prio = I2C2_TX_DMA_INT_PRIO, \ .int_src = I2C2_TX_DMA_INT_SRC, \
.int_src = I2C2_TX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C2_TX_DMA_CONFIG */ #endif /* I2C2_TX_DMA_CONFIG */
#ifndef I2C2_RX_DMA_CONFIG #ifndef I2C2_RX_DMA_CONFIG
#define I2C2_RX_DMA_CONFIG \ #define I2C2_RX_DMA_CONFIG \
{ \ { \
.Instance = I2C2_RX_DMA_INSTANCE, \ .Instance = I2C2_RX_DMA_INSTANCE, \
.channel = I2C2_RX_DMA_CHANNEL, \ .channel = I2C2_RX_DMA_CHANNEL, \
.clock = I2C2_RX_DMA_CLOCK, \ .clock = I2C2_RX_DMA_CLOCK, \
.trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C2_RXI, \ .trigger_event = EVT_SRC_I2C2_RXI, \
.flag = I2C2_RX_DMA_TRANS_FLAG, \ .flag = I2C2_RX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C2_RX_DMA_IRQn, \
.irq_num = I2C2_RX_DMA_IRQn, \ .irq_prio = I2C2_RX_DMA_INT_PRIO, \
.irq_prio = I2C2_RX_DMA_INT_PRIO, \ .int_src = I2C2_RX_DMA_INT_SRC, \
.int_src = I2C2_RX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C2_RX_DMA_CONFIG */ #endif /* I2C2_RX_DMA_CONFIG */
#endif /* BSP_I2C2_USING_DMA */ #endif /* BSP_I2C2_USING_DMA */
@@ -123,50 +119,48 @@ extern "C" {
#if defined(BSP_USING_I2C3) #if defined(BSP_USING_I2C3)
#ifndef I2C3_CONFIG #ifndef I2C3_CONFIG
#define I2C3_CONFIG \ #define I2C3_CONFIG \
{ \ { \
.name = "i2c3", \ .name = "i2c3", \
.Instance = CM_I2C3, \ .Instance = CM_I2C3, \
.clock = FCG1_PERIPH_I2C3, \ .clock = FCG1_PERIPH_I2C3, \
.baudrate = 100000UL, \ .baudrate = 100000UL, \
.timeout = 10000UL, \ .timeout = 10000UL, \
} }
#endif /* I2C3_CONFIG */ #endif /* I2C3_CONFIG */
#if defined(BSP_I2C3_USING_DMA) #if defined(BSP_I2C3_USING_DMA)
#ifndef I2C3_TX_DMA_CONFIG #ifndef I2C3_TX_DMA_CONFIG
#define I2C3_TX_DMA_CONFIG \ #define I2C3_TX_DMA_CONFIG \
{ \ { \
.Instance = I2C3_TX_DMA_INSTANCE, \ .Instance = I2C3_TX_DMA_INSTANCE, \
.channel = I2C3_TX_DMA_CHANNEL, \ .channel = I2C3_TX_DMA_CHANNEL, \
.clock = I2C3_TX_DMA_CLOCK, \ .clock = I2C3_TX_DMA_CLOCK, \
.trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_TEI, \ .trigger_event = EVT_SRC_I2C3_TEI, \
.flag = I2C3_TX_DMA_TRANS_FLAG, \ .flag = I2C3_TX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C3_TX_DMA_IRQn, \
.irq_num = I2C3_TX_DMA_IRQn, \ .irq_prio = I2C3_TX_DMA_INT_PRIO, \
.irq_prio = I2C3_TX_DMA_INT_PRIO, \ .int_src = I2C3_TX_DMA_INT_SRC, \
.int_src = I2C3_TX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C3_TX_DMA_CONFIG */ #endif /* I2C3_TX_DMA_CONFIG */
#ifndef I2C3_RX_DMA_CONFIG #ifndef I2C3_RX_DMA_CONFIG
#define I2C3_RX_DMA_CONFIG \ #define I2C3_RX_DMA_CONFIG \
{ \ { \
.Instance = I2C3_RX_DMA_INSTANCE, \ .Instance = I2C3_RX_DMA_INSTANCE, \
.channel = I2C3_RX_DMA_CHANNEL, \ .channel = I2C3_RX_DMA_CHANNEL, \
.clock = I2C3_RX_DMA_CLOCK, \ .clock = I2C3_RX_DMA_CLOCK, \
.trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C3_RXI, \ .trigger_event = EVT_SRC_I2C3_RXI, \
.flag = I2C3_RX_DMA_TRANS_FLAG, \ .flag = I2C3_RX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C3_RX_DMA_IRQn, \
.irq_num = I2C3_RX_DMA_IRQn, \ .irq_prio = I2C3_RX_DMA_INT_PRIO, \
.irq_prio = I2C3_RX_DMA_INT_PRIO, \ .int_src = I2C3_RX_DMA_INT_SRC, \
.int_src = I2C3_RX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C3_RX_DMA_CONFIG */ #endif /* I2C3_RX_DMA_CONFIG */
#endif /* BSP_I2C3_USING_DMA */ #endif /* BSP_I2C3_USING_DMA */
@@ -174,50 +168,48 @@ extern "C" {
#if defined(BSP_USING_I2C4) #if defined(BSP_USING_I2C4)
#ifndef I2C4_CONFIG #ifndef I2C4_CONFIG
#define I2C4_CONFIG \ #define I2C4_CONFIG \
{ \ { \
.name = "i2c4", \ .name = "i2c4", \
.Instance = CM_I2C4, \ .Instance = CM_I2C4, \
.clock = FCG1_PERIPH_I2C4, \ .clock = FCG1_PERIPH_I2C4, \
.baudrate = 100000UL, \ .baudrate = 100000UL, \
.timeout = 10000UL, \ .timeout = 10000UL, \
} }
#endif /* I2C4_CONFIG */ #endif /* I2C4_CONFIG */
#if defined(BSP_I2C4_USING_DMA) #if defined(BSP_I2C4_USING_DMA)
#ifndef I2C4_TX_DMA_CONFIG #ifndef I2C4_TX_DMA_CONFIG
#define I2C4_TX_DMA_CONFIG \ #define I2C4_TX_DMA_CONFIG \
{ \ { \
.Instance = I2C4_TX_DMA_INSTANCE, \ .Instance = I2C4_TX_DMA_INSTANCE, \
.channel = I2C4_TX_DMA_CHANNEL, \ .channel = I2C4_TX_DMA_CHANNEL, \
.clock = I2C4_TX_DMA_CLOCK, \ .clock = I2C4_TX_DMA_CLOCK, \
.trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C4_TEI, \ .trigger_event = EVT_SRC_I2C4_TEI, \
.flag = I2C4_TX_DMA_TRANS_FLAG, \ .flag = I2C4_TX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C4_TX_DMA_IRQn, \
.irq_num = I2C4_TX_DMA_IRQn, \ .irq_prio = I2C4_TX_DMA_INT_PRIO, \
.irq_prio = I2C4_TX_DMA_INT_PRIO, \ .int_src = I2C4_TX_DMA_INT_SRC, \
.int_src = I2C4_TX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C4_TX_DMA_CONFIG */ #endif /* I2C4_TX_DMA_CONFIG */
#ifndef I2C4_RX_DMA_CONFIG #ifndef I2C4_RX_DMA_CONFIG
#define I2C4_RX_DMA_CONFIG \ #define I2C4_RX_DMA_CONFIG \
{ \ { \
.Instance = I2C4_RX_DMA_INSTANCE, \ .Instance = I2C4_RX_DMA_INSTANCE, \
.channel = I2C4_RX_DMA_CHANNEL, \ .channel = I2C4_RX_DMA_CHANNEL, \
.clock = I2C4_RX_DMA_CLOCK, \ .clock = I2C4_RX_DMA_CLOCK, \
.trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C4_RXI, \ .trigger_event = EVT_SRC_I2C4_RXI, \
.flag = I2C4_RX_DMA_TRANS_FLAG, \ .flag = I2C4_RX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C4_RX_DMA_IRQn, \
.irq_num = I2C4_RX_DMA_IRQn, \ .irq_prio = I2C4_RX_DMA_INT_PRIO, \
.irq_prio = I2C4_RX_DMA_INT_PRIO, \ .int_src = I2C4_RX_DMA_INT_SRC, \
.int_src = I2C4_RX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C4_RX_DMA_CONFIG */ #endif /* I2C4_RX_DMA_CONFIG */
#endif /* BSP_I2C4_USING_DMA */ #endif /* BSP_I2C4_USING_DMA */
@@ -225,50 +217,48 @@ extern "C" {
#if defined(BSP_USING_I2C5) #if defined(BSP_USING_I2C5)
#ifndef I2C5_CONFIG #ifndef I2C5_CONFIG
#define I2C5_CONFIG \ #define I2C5_CONFIG \
{ \ { \
.name = "i2c5", \ .name = "i2c5", \
.Instance = CM_I2C5, \ .Instance = CM_I2C5, \
.clock = FCG1_PERIPH_I2C5, \ .clock = FCG1_PERIPH_I2C5, \
.baudrate = 100000UL, \ .baudrate = 100000UL, \
.timeout = 10000UL, \ .timeout = 10000UL, \
} }
#endif /* I2C5_CONFIG */ #endif /* I2C5_CONFIG */
#if defined(BSP_I2C5_USING_DMA) #if defined(BSP_I2C5_USING_DMA)
#ifndef I2C5_TX_DMA_CONFIG #ifndef I2C5_TX_DMA_CONFIG
#define I2C5_TX_DMA_CONFIG \ #define I2C5_TX_DMA_CONFIG \
{ \ { \
.Instance = I2C5_TX_DMA_INSTANCE, \ .Instance = I2C5_TX_DMA_INSTANCE, \
.channel = I2C5_TX_DMA_CHANNEL, \ .channel = I2C5_TX_DMA_CHANNEL, \
.clock = I2C5_TX_DMA_CLOCK, \ .clock = I2C5_TX_DMA_CLOCK, \
.trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C5_TEI, \ .trigger_event = EVT_SRC_I2C5_TEI, \
.flag = I2C5_TX_DMA_TRANS_FLAG, \ .flag = I2C5_TX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C5_TX_DMA_IRQn, \
.irq_num = I2C5_TX_DMA_IRQn, \ .irq_prio = I2C5_TX_DMA_INT_PRIO, \
.irq_prio = I2C5_TX_DMA_INT_PRIO, \ .int_src = I2C5_TX_DMA_INT_SRC, \
.int_src = I2C5_TX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C5_TX_DMA_CONFIG */ #endif /* I2C5_TX_DMA_CONFIG */
#ifndef I2C5_RX_DMA_CONFIG #ifndef I2C5_RX_DMA_CONFIG
#define I2C5_RX_DMA_CONFIG \ #define I2C5_RX_DMA_CONFIG \
{ \ { \
.Instance = I2C5_RX_DMA_INSTANCE, \ .Instance = I2C5_RX_DMA_INSTANCE, \
.channel = I2C5_RX_DMA_CHANNEL, \ .channel = I2C5_RX_DMA_CHANNEL, \
.clock = I2C5_RX_DMA_CLOCK, \ .clock = I2C5_RX_DMA_CLOCK, \
.trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C5_RXI, \ .trigger_event = EVT_SRC_I2C5_RXI, \
.flag = I2C5_RX_DMA_TRANS_FLAG, \ .flag = I2C5_RX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C5_RX_DMA_IRQn, \
.irq_num = I2C5_RX_DMA_IRQn, \ .irq_prio = I2C5_RX_DMA_INT_PRIO, \
.irq_prio = I2C5_RX_DMA_INT_PRIO, \ .int_src = I2C5_RX_DMA_INT_SRC, \
.int_src = I2C5_RX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C5_RX_DMA_CONFIG */ #endif /* I2C5_RX_DMA_CONFIG */
#endif /* BSP_I2C5_USING_DMA */ #endif /* BSP_I2C5_USING_DMA */
@@ -276,50 +266,48 @@ extern "C" {
#if defined(BSP_USING_I2C6) #if defined(BSP_USING_I2C6)
#ifndef I2C6_CONFIG #ifndef I2C6_CONFIG
#define I2C6_CONFIG \ #define I2C6_CONFIG \
{ \ { \
.name = "i2c6", \ .name = "i2c6", \
.Instance = CM_I2C6, \ .Instance = CM_I2C6, \
.clock = FCG1_PERIPH_I2C6, \ .clock = FCG1_PERIPH_I2C6, \
.baudrate = 100000UL, \ .baudrate = 100000UL, \
.timeout = 10000UL, \ .timeout = 10000UL, \
} }
#endif /* I2C6_CONFIG */ #endif /* I2C6_CONFIG */
#if defined(BSP_I2C6_USING_DMA) #if defined(BSP_I2C6_USING_DMA)
#ifndef I2C6_TX_DMA_CONFIG #ifndef I2C6_TX_DMA_CONFIG
#define I2C6_TX_DMA_CONFIG \ #define I2C6_TX_DMA_CONFIG \
{ \ { \
.Instance = I2C6_TX_DMA_INSTANCE, \ .Instance = I2C6_TX_DMA_INSTANCE, \
.channel = I2C6_TX_DMA_CHANNEL, \ .channel = I2C6_TX_DMA_CHANNEL, \
.clock = I2C6_TX_DMA_CLOCK, \ .clock = I2C6_TX_DMA_CLOCK, \
.trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C6_TEI, \ .trigger_event = EVT_SRC_I2C6_TEI, \
.flag = I2C6_TX_DMA_TRANS_FLAG, \ .flag = I2C6_TX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C6_TX_DMA_IRQn, \
.irq_num = I2C6_TX_DMA_IRQn, \ .irq_prio = I2C6_TX_DMA_INT_PRIO, \
.irq_prio = I2C6_TX_DMA_INT_PRIO, \ .int_src = I2C6_TX_DMA_INT_SRC, \
.int_src = I2C6_TX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C6_TX_DMA_CONFIG */ #endif /* I2C6_TX_DMA_CONFIG */
#ifndef I2C6_RX_DMA_CONFIG #ifndef I2C6_RX_DMA_CONFIG
#define I2C6_RX_DMA_CONFIG \ #define I2C6_RX_DMA_CONFIG \
{ \ { \
.Instance = I2C6_RX_DMA_INSTANCE, \ .Instance = I2C6_RX_DMA_INSTANCE, \
.channel = I2C6_RX_DMA_CHANNEL, \ .channel = I2C6_RX_DMA_CHANNEL, \
.clock = I2C6_RX_DMA_CLOCK, \ .clock = I2C6_RX_DMA_CLOCK, \
.trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_I2C6_RXI, \ .trigger_event = EVT_SRC_I2C6_RXI, \
.flag = I2C6_RX_DMA_TRANS_FLAG, \ .flag = I2C6_RX_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = I2C6_RX_DMA_IRQn, \
.irq_num = I2C6_RX_DMA_IRQn, \ .irq_prio = I2C6_RX_DMA_INT_PRIO, \
.irq_prio = I2C6_RX_DMA_INT_PRIO, \ .int_src = I2C6_RX_DMA_INT_SRC, \
.int_src = I2C6_RX_DMA_INT_SRC, \ }, \
}, \
} }
#endif /* I2C6_RX_DMA_CONFIG */ #endif /* I2C6_RX_DMA_CONFIG */
#endif /* BSP_I2C6_USING_DMA */ #endif /* BSP_I2C6_USING_DMA */
bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h
+137 -137
View File
@@ -18,245 +18,245 @@
extern "C" { extern "C" {
#endif #endif
#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn #define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn #define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn #define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn #define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn #define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn #define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn #define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn #define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn #define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn #define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn #define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn #define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn #define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn #define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn #define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn #define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch0 */ /* DMA1 ch0 */
#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn #define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch1 */ /* DMA1 ch1 */
#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn #define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch2 */ /* DMA1 ch2 */
#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn #define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch3 */ /* DMA1 ch3 */
#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn #define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch4 */ /* DMA1 ch4 */
#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn #define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA1 ch5 */ /* DMA1 ch5 */
#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn #define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch0 */ /* DMA2 ch0 */
#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn #define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn
#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch1 */ /* DMA2 ch1 */
#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn #define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn
#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch2 */ /* DMA2 ch2 */
#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn #define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn
#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch3 */ /* DMA2 ch3 */
#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn #define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn
#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch4 */ /* DMA2 ch4 */
#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn #define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn
#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
/* DMA2 ch5 */ /* DMA2 ch5 */
#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn #define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn
#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if defined(BSP_USING_UART1) #if defined(BSP_USING_UART1)
#define BSP_UART1_IRQ_NUM USART1_IRQn #define BSP_UART1_IRQ_NUM USART1_IRQn
#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \ #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2) defined(RT_USING_SERIAL_V2)
#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn #define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#endif /* BSP_USING_UART1 */ #endif /* BSP_USING_UART1 */
#if defined(BSP_USING_UART2) #if defined(BSP_USING_UART2)
#define BSP_UART2_IRQ_NUM USART2_IRQn #define BSP_UART2_IRQ_NUM USART2_IRQn
#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \ #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2) defined(RT_USING_SERIAL_V2)
#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn #define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#endif /* BSP_USING_UART2 */ #endif /* BSP_USING_UART2 */
#if defined(BSP_USING_UART3) #if defined(BSP_USING_UART3)
#define BSP_UART3_IRQ_NUM USART3_IRQn #define BSP_UART3_IRQ_NUM USART3_IRQn
#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART3 */ #endif /* BSP_USING_UART3 */
#if defined(BSP_USING_UART4) #if defined(BSP_USING_UART4)
#define BSP_UART4_IRQ_NUM USART4_IRQn #define BSP_UART4_IRQ_NUM USART4_IRQn
#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \ #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2) defined(RT_USING_SERIAL_V2)
#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn #define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#endif /* BSP_USING_UART4 */ #endif /* BSP_USING_UART4 */
#if defined(BSP_USING_UART5) #if defined(BSP_USING_UART5)
#define BSP_UART5_IRQ_NUM USART5_IRQn #define BSP_UART5_IRQ_NUM USART5_IRQn
#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \ #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \
defined(RT_USING_SERIAL_V2) defined(RT_USING_SERIAL_V2)
#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn #define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn
#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#endif /* BSP_USING_UART5 */ #endif /* BSP_USING_UART5 */
#if defined(BSP_USING_UART6) #if defined(BSP_USING_UART6)
#define BSP_UART6_IRQ_NUM USART6_IRQn #define BSP_UART6_IRQ_NUM USART6_IRQn
#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_UART6 */ #endif /* BSP_USING_UART6 */
#if defined(BSP_USING_SPI1) #if defined(BSP_USING_SPI1)
#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn #define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#if defined(BSP_USING_SPI2) #if defined(BSP_USING_SPI2)
#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn #define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn
#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#if defined(BSP_USING_SPI3) #if defined(BSP_USING_SPI3)
#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn #define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif #endif
#if defined (BSP_USING_QSPI) #if defined(BSP_USING_QSPI)
#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn #define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn
#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif /* BSP_USING_QSPI */ #endif /* BSP_USING_QSPI */
#if defined(BSP_USING_TMRA_1) #if defined(BSP_USING_TMRA_1)
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn #define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_1 */ #endif/* BSP_USING_TMRA_1 */
#if defined(BSP_USING_TMRA_2) #if defined(BSP_USING_TMRA_2)
#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn #define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_2 */ #endif/* BSP_USING_TMRA_2 */
#if defined(BSP_USING_TMRA_3) #if defined(BSP_USING_TMRA_3)
#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn #define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_3 */ #endif/* BSP_USING_TMRA_3 */
#if defined(BSP_USING_TMRA_4) #if defined(BSP_USING_TMRA_4)
#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn #define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_4 */ #endif/* BSP_USING_TMRA_4 */
#if defined(BSP_USING_TMRA_5) #if defined(BSP_USING_TMRA_5)
#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn #define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_TMRA_5 */ #endif/* BSP_USING_TMRA_5 */
#if defined(BSP_USING_MCAN1) #if defined(BSP_USING_MCAN1)
#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn #define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn
#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_MCAN1 */ #endif/* BSP_USING_MCAN1 */
#if defined(BSP_USING_MCAN2) #if defined(BSP_USING_MCAN2)
#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn #define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn
#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_MCAN2 */ #endif/* BSP_USING_MCAN2 */
#if defined(RT_USING_ALARM) #if defined(RT_USING_ALARM)
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn #define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* RT_USING_ALARM */ #endif/* RT_USING_ALARM */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_2) #if defined(BSP_USING_PULSE_ENCODER_TMRA_2)
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_3) #if defined(BSP_USING_PULSE_ENCODER_TMRA_3)
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_4) #if defined(BSP_USING_PULSE_ENCODER_TMRA_4)
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */
#if defined(BSP_USING_PULSE_ENCODER_TMRA_5) #if defined(BSP_USING_PULSE_ENCODER_TMRA_5)
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) #if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */
#if defined(BSP_USING_PULSE_ENCODER_TMR6_2) #if defined(BSP_USING_PULSE_ENCODER_TMR6_2)
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn #define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn
#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */
#if defined(BSP_USING_INPUT_CAPTURE) #if defined(BSP_USING_INPUT_CAPTURE)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) #define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) #define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) #define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) #define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn)
#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT)
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
bsp/hc32/ev_hc32f448_lqfp80/board/config/mcan_config.h
+232 -232
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File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h
+36 -36
View File
@@ -22,18 +22,18 @@ extern "C" {
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK #ifndef PM_TICKLESS_TIMER_ENABLE_MASK
#define PM_TICKLESS_TIMER_ENABLE_MASK \ #define PM_TICKLESS_TIMER_ENABLE_MASK \
( (1UL << PM_SLEEP_MODE_IDLE) | \ ((1UL << PM_SLEEP_MODE_IDLE) | \
(1UL << PM_SLEEP_MODE_DEEP)) (1UL << PM_SLEEP_MODE_DEEP))
#endif #endif
/** /**
* @brief run mode config @ref pm_run_mode_config structure * @brief run mode config @ref pm_run_mode_config structure
*/ */
#ifndef PM_RUN_MODE_CFG #ifndef PM_RUN_MODE_CFG
#define PM_RUN_MODE_CFG \ #define PM_RUN_MODE_CFG \
{ \ { \
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
} }
#endif /* PM_RUN_MODE_CFG */ #endif /* PM_RUN_MODE_CFG */
@@ -41,54 +41,54 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure * @brief sleep idle config @ref pm_sleep_mode_idle_config structure
*/ */
#ifndef PM_SLEEP_IDLE_CFG #ifndef PM_SLEEP_IDLE_CFG
#define PM_SLEEP_IDLE_CFG \ #define PM_SLEEP_IDLE_CFG \
{ \ { \
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \ .pwc_sleep_type = PWC_SLEEP_WFE_INT, \
} }
#endif /*PM_SLEEP_IDLE_CFG*/ #endif /*PM_SLEEP_IDLE_CFG*/
/** /**
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure * @brief sleep deep config @ref pm_sleep_mode_deep_config structure
*/ */
#ifndef PM_SLEEP_DEEP_CFG #ifndef PM_SLEEP_DEEP_CFG
#define PM_SLEEP_DEEP_CFG \ #define PM_SLEEP_DEEP_CFG \
{ \ { \
{ \ { \
.u16Clock = PWC_STOP_CLK_KEEP, \ .u16Clock = PWC_STOP_CLK_KEEP, \
.u8StopDrv = PWC_STOP_DRV_HIGH, \ .u8StopDrv = PWC_STOP_DRV_HIGH, \
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
}, \ }, \
.pwc_stop_type = PWC_STOP_WFE_INT, \ .pwc_stop_type = PWC_STOP_WFE_INT, \
} }
#endif /*PM_SLEEP_DEEP_CFG*/ #endif /*PM_SLEEP_DEEP_CFG*/
/** /**
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure * @brief sleep standby config @ref pm_sleep_mode_standby_config structure
*/ */
#ifndef PM_SLEEP_STANDBY_CFG #ifndef PM_SLEEP_STANDBY_CFG
#define PM_SLEEP_STANDBY_CFG \ #define PM_SLEEP_STANDBY_CFG \
{ \ { \
{ \ { \
.u8Mode = PWC_PD_MD1, \ .u8Mode = PWC_PD_MD1, \
.u8IOState = PWC_PD_IO_KEEP1, \ .u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \ }, \
} }
#endif /*PM_SLEEP_STANDBY_CFG*/ #endif /*PM_SLEEP_STANDBY_CFG*/
/** /**
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
*/ */
#ifndef PM_SLEEP_SHUTDOWN_CFG #ifndef PM_SLEEP_SHUTDOWN_CFG
#define PM_SLEEP_SHUTDOWN_CFG \ #define PM_SLEEP_SHUTDOWN_CFG \
{ \ { \
{ \ { \
.u8Mode = PWC_PD_MD3, \ .u8Mode = PWC_PD_MD3, \
.u8IOState = PWC_PD_IO_KEEP1, \ .u8IOState = PWC_PD_IO_KEEP1, \
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
}, \ }, \
} }
#endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /*PM_SLEEP_SHUTDOWN_CFG*/
#endif /* BSP_USING_PM */ #endif /* BSP_USING_PM */
bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h
+126 -140
View File
@@ -22,182 +22,168 @@ extern "C" {
#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifdef BSP_USING_PULSE_ENCODER_TMRA_1
#ifndef PULSE_ENCODER_TMRA_1_CONFIG #ifndef PULSE_ENCODER_TMRA_1_CONFIG
#define PULSE_ENCODER_TMRA_1_CONFIG \ #define PULSE_ENCODER_TMRA_1_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_1, \ .tmr_handler = CM_TMRA_1, \
.u32PeriphClock = FCG2_PERIPH_TMRA_1, \ .u32PeriphClock = FCG2_PERIPH_TMRA_1, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a1" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a1" \
} }
#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* PULSE_ENCODER_TMRA_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifdef BSP_USING_PULSE_ENCODER_TMRA_2
#ifndef PULSE_ENCODER_TMRA_2_CONFIG #ifndef PULSE_ENCODER_TMRA_2_CONFIG
#define PULSE_ENCODER_TMRA_2_CONFIG \ #define PULSE_ENCODER_TMRA_2_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_2, \ .tmr_handler = CM_TMRA_2, \
.u32PeriphClock = FCG2_PERIPH_TMRA_2, \ .u32PeriphClock = FCG2_PERIPH_TMRA_2, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a2" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a2" \
} }
#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* PULSE_ENCODER_TMRA_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifdef BSP_USING_PULSE_ENCODER_TMRA_3
#ifndef PULSE_ENCODER_TMRA_3_CONFIG #ifndef PULSE_ENCODER_TMRA_3_CONFIG
#define PULSE_ENCODER_TMRA_3_CONFIG \ #define PULSE_ENCODER_TMRA_3_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_3, \ .tmr_handler = CM_TMRA_3, \
.u32PeriphClock = FCG2_PERIPH_TMRA_3, \ .u32PeriphClock = FCG2_PERIPH_TMRA_3, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a3" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a3" \
} }
#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* PULSE_ENCODER_TMRA_3_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifdef BSP_USING_PULSE_ENCODER_TMRA_4
#ifndef PULSE_ENCODER_TMRA_4_CONFIG #ifndef PULSE_ENCODER_TMRA_4_CONFIG
#define PULSE_ENCODER_TMRA_4_CONFIG \ #define PULSE_ENCODER_TMRA_4_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_4, \ .tmr_handler = CM_TMRA_4, \
.u32PeriphClock = FCG2_PERIPH_TMRA_4, \ .u32PeriphClock = FCG2_PERIPH_TMRA_4, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a4" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a4" \
} }
#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* PULSE_ENCODER_TMRA_4_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifdef BSP_USING_PULSE_ENCODER_TMRA_5
#ifndef PULSE_ENCODER_TMRA_5_CONFIG #ifndef PULSE_ENCODER_TMRA_5_CONFIG
#define PULSE_ENCODER_TMRA_5_CONFIG \ #define PULSE_ENCODER_TMRA_5_CONFIG \
{ \ { \
.tmr_handler = CM_TMRA_5, \ .tmr_handler = CM_TMRA_5, \
.u32PeriphClock = FCG2_PERIPH_TMRA_5, \ .u32PeriphClock = FCG2_PERIPH_TMRA_5, \
.hw_count = \ .hw_count = { \
{ \ .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \
.u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \
.u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_a5" \
.u32PeriodValue = 1000UL, \
.name = "pulse_a5" \
} }
#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* PULSE_ENCODER_TMRA_5_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifdef BSP_USING_PULSE_ENCODER_TMR6_1
#ifndef PULSE_ENCODER_TMR6_1_CONFIG #ifndef PULSE_ENCODER_TMR6_1_CONFIG
#define PULSE_ENCODER_TMR6_1_CONFIG \ #define PULSE_ENCODER_TMR6_1_CONFIG \
{ \ { \
.tmr_handler = CM_TMR6_1, \ .tmr_handler = CM_TMR6_1, \
.u32PeriphClock = FCG2_PERIPH_TMR6_1, \ .u32PeriphClock = FCG2_PERIPH_TMR6_1, \
.hw_count = \ .hw_count = { \
{ \ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_61" \
.u32PeriodValue = 1000UL, \
.name = "pulse_61" \
} }
#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* PULSE_ENCODER_TMR6_1_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifdef BSP_USING_PULSE_ENCODER_TMR6_2
#ifndef PULSE_ENCODER_TMR6_2_CONFIG #ifndef PULSE_ENCODER_TMR6_2_CONFIG
#define PULSE_ENCODER_TMR6_2_CONFIG \ #define PULSE_ENCODER_TMR6_2_CONFIG \
{ \ { \
.tmr_handler = CM_TMR6_2, \ .tmr_handler = CM_TMR6_2, \
.u32PeriphClock = FCG2_PERIPH_TMR6_2, \ .u32PeriphClock = FCG2_PERIPH_TMR6_2, \
.hw_count = \ .hw_count = { \
{ \ .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \
.u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \
.u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ }, \
}, \ .isr = { \
.isr = \ .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \
{ \ .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \
.enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \
.enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \
.u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \
.enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \
.enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ }, \
.u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ .u32PeriodValue = 1000UL, \
}, \ .name = "pulse_62" \
.u32PeriodValue = 1000UL, \
.name = "pulse_62" \
} }
#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* PULSE_ENCODER_TMR6_2_CONFIG */
#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h
+470 -539
View File
File diff suppressed because it is too large Load Diff
bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h
+31 -33
View File
@@ -21,54 +21,52 @@ extern "C" {
#ifdef BSP_USING_QSPI #ifdef BSP_USING_QSPI
#ifndef QSPI_BUS_CONFIG #ifndef QSPI_BUS_CONFIG
#define QSPI_BUS_CONFIG \ #define QSPI_BUS_CONFIG \
{ \ { \
.Instance = CM_QSPI, \ .Instance = CM_QSPI, \
.clock = FCG1_PERIPH_QSPI, \ .clock = FCG1_PERIPH_QSPI, \
.timeout = 5000UL, \ .timeout = 5000UL, \
.err_irq.irq_config = \ .err_irq.irq_config = { \
{ \ .irq_num = BSP_QSPI_ERR_IRQ_NUM, \
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \ .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ .int_src = INT_SRC_QSPI_INTR, \
.int_src = INT_SRC_QSPI_INTR, \ }, \
}, \
} }
#endif /* QSPI_BUS_CONFIG */ #endif /* QSPI_BUS_CONFIG */
#ifndef QSPI_INIT_PARAMS #ifndef QSPI_INIT_PARAMS
#define QSPI_INIT_PARAMS \ #define QSPI_INIT_PARAMS \
{ \ { \
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
} }
#endif /* QSPI_INIT_PARAMS */ #endif /* QSPI_INIT_PARAMS */
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH #define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
#ifdef BSP_QSPI_USING_DMA #ifdef BSP_QSPI_USING_DMA
#ifndef QSPI_DMA_CONFIG #ifndef QSPI_DMA_CONFIG
#define QSPI_DMA_CONFIG \ #define QSPI_DMA_CONFIG \
{ \ { \
.Instance = QSPI_DMA_INSTANCE, \ .Instance = QSPI_DMA_INSTANCE, \
.channel = QSPI_DMA_CHANNEL, \ .channel = QSPI_DMA_CHANNEL, \
.clock = QSPI_DMA_CLOCK, \ .clock = QSPI_DMA_CLOCK, \
.trigger_select = QSPI_DMA_TRIG_SELECT, \ .trigger_select = QSPI_DMA_TRIG_SELECT, \
.trigger_event = EVT_SRC_AOS_STRG, \ .trigger_event = EVT_SRC_AOS_STRG, \
.flag = QSPI_DMA_TRANS_FLAG, \ .flag = QSPI_DMA_TRANS_FLAG, \
.irq_config = \ .irq_config = { \
{ \ .irq_num = QSPI_DMA_IRQn, \
.irq_num = QSPI_DMA_IRQn, \ .irq_prio = QSPI_DMA_INT_PRIO, \
.irq_prio = QSPI_DMA_INT_PRIO, \ .int_src = QSPI_DMA_INT_SRC, \
.int_src = QSPI_DMA_INT_SRC, \ } \
} \
} }
#endif /* QSPI_DMA_CONFIG */ #endif /* QSPI_DMA_CONFIG */
/* unit: half-word, DMA data width of QSPI transmitting is 16bit */ /* unit: half-word, DMA data width of QSPI transmitting is 16bit */
#ifndef QSPI_DMA_TX_BUFSIZE #ifndef QSPI_DMA_TX_BUFSIZE
#define QSPI_DMA_TX_BUFSIZE 256 #define QSPI_DMA_TX_BUFSIZE 256
#endif /* QSPI_DMA_TX_BUFSIZE */ #endif /* QSPI_DMA_TX_BUFSIZE */
#endif /* BSP_QSPI_USING_DMA */ #endif /* BSP_QSPI_USING_DMA */
#endif /* BSP_USING_QSPI */ #endif /* BSP_USING_QSPI */

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