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set Systick interrupt priority to the lowest

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This commit is contained in:
aozima
2020-05-30 15:23:25 +08:00
parent 1ef77bd969
commit c3d63e49de
18 changed files with 36 additions and 36 deletions
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libcpu/arm/cortex-m0/context_gcc.S
+2 -2
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@@ -22,7 +22,7 @@
.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */ .equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
/* /*
@@ -159,7 +159,7 @@ rt_hw_context_switch_to:
MOVS R0, #1 MOVS R0, #1
STR R0, [R1] STR R0, [R1]
/* set the PendSV exception priority */ /* set the PendSV and SysTick exception priority */
LDR R0, =NVIC_SHPR3 LDR R0, =NVIC_SHPR3
LDR R1, =NVIC_PENDSV_PRI LDR R1, =NVIC_PENDSV_PRI
LDR R2, [R0,#0x00] /* read */ LDR R2, [R0,#0x00] /* read */
libcpu/arm/cortex-m0/context_iar.S
+2 -2
View File
@@ -19,7 +19,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2) SECTION .text:CODE(2)
@@ -163,7 +163,7 @@ rt_hw_context_switch_to:
MOVS r0, #1 MOVS r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SHPR3 LDR r0, =NVIC_SHPR3
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR r2, [r0,#0x00] ; read LDR r2, [r0,#0x00] ; read
libcpu/arm/cortex-m0/context_rvds.S
+2 -2
View File
@@ -19,7 +19,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2 AREA |.text|, CODE, READONLY, ALIGN=2
@@ -168,7 +168,7 @@ rt_hw_context_switch_to PROC
MOVS r0, #1 MOVS r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SHPR3 LDR r0, =NVIC_SHPR3
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR r2, [r0,#0x00] ; read LDR r2, [r0,#0x00] ; read
libcpu/arm/cortex-m23/context_gcc.S
+2 -2
View File
@@ -23,7 +23,7 @@
.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */ .equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
/* /*
@@ -160,7 +160,7 @@ rt_hw_context_switch_to:
MOVS R0, #1 MOVS R0, #1
STR R0, [R1] STR R0, [R1]
/* set the PendSV exception priority */ /* set the PendSV and SysTick exception priority */
LDR R0, =NVIC_SHPR3 LDR R0, =NVIC_SHPR3
LDR R1, =NVIC_PENDSV_PRI LDR R1, =NVIC_PENDSV_PRI
LDR R2, [R0,#0x00] /* read */ LDR R2, [R0,#0x00] /* read */
libcpu/arm/cortex-m23/context_iar.S
+2 -2
View File
@@ -20,7 +20,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2) SECTION .text:CODE(2)
@@ -164,7 +164,7 @@ rt_hw_context_switch_to:
MOVS r0, #1 MOVS r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SHPR3 LDR r0, =NVIC_SHPR3
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR r2, [r0,#0x00] ; read LDR r2, [r0,#0x00] ; read
libcpu/arm/cortex-m23/context_rvds.S
+2 -2
View File
@@ -20,7 +20,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2 AREA |.text|, CODE, READONLY, ALIGN=2
@@ -169,7 +169,7 @@ rt_hw_context_switch_to PROC
MOVS r0, #1 MOVS r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SHPR3 LDR r0, =NVIC_SHPR3
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR r2, [r0,#0x00] ; read LDR r2, [r0,#0x00] ; read
libcpu/arm/cortex-m3/context_gcc.S
+2 -2
View File
@@ -24,7 +24,7 @@
.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
.equ SHPR3, 0xE000ED20 /* system priority register (3) */ .equ SHPR3, 0xE000ED20 /* system priority register (3) */
.equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */ .equ PENDSV_PRI_LOWEST, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
/* /*
* rt_base_t rt_hw_interrupt_disable(); * rt_base_t rt_hw_interrupt_disable();
@@ -140,7 +140,7 @@ rt_hw_context_switch_to:
MOV R0, #1 MOV R0, #1
STR R0, [R1] STR R0, [R1]
/* set the PendSV exception priority */ /* set the PendSV and SysTick exception priority */
LDR R0, =SHPR3 LDR R0, =SHPR3
LDR R1, =PENDSV_PRI_LOWEST LDR R1, =PENDSV_PRI_LOWEST
LDR.W R2, [R0,#0] /* read */ LDR.W R2, [R0,#0] /* read */
libcpu/arm/cortex-m3/context_iar.S
+2 -2
View File
@@ -19,7 +19,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2) SECTION .text:CODE(2)
@@ -139,7 +139,7 @@ rt_hw_context_switch_to:
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
libcpu/arm/cortex-m3/context_rvds.S
+2 -2
View File
@@ -18,7 +18,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2 AREA |.text|, CODE, READONLY, ALIGN=2
@@ -145,7 +145,7 @@ rt_hw_context_switch_to PROC
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
libcpu/arm/cortex-m33/context_gcc.S
+2 -2
View File
@@ -25,7 +25,7 @@
.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
/* /*
@@ -225,7 +225,7 @@ rt_hw_context_switch_to:
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
/* set the PendSV exception priority */ /* set the PendSV and SysTick exception priority */
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] /* read */ LDR.W r2, [r0,#0x00] /* read */
libcpu/arm/cortex-m33/context_iar.S
+2 -2
View File
@@ -21,7 +21,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2) SECTION .text:CODE(2)
@@ -231,7 +231,7 @@ rt_hw_context_switch_to:
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
libcpu/arm/cortex-m33/context_rvds.S
+2 -2
View File
@@ -20,7 +20,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2 AREA |.text|, CODE, READONLY, ALIGN=2
@@ -232,7 +232,7 @@ rt_hw_context_switch_to PROC
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
libcpu/arm/cortex-m4/context_gcc.S
+2 -2
View File
@@ -25,7 +25,7 @@
.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
/* /*
@@ -182,7 +182,7 @@ rt_hw_context_switch_to:
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
/* set the PendSV exception priority */ /* set the PendSV and SysTick exception priority */
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] /* read */ LDR.W r2, [r0,#0x00] /* read */
libcpu/arm/cortex-m4/context_iar.S
+2 -2
View File
@@ -21,7 +21,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2) SECTION .text:CODE(2)
@@ -186,7 +186,7 @@ rt_hw_context_switch_to:
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
libcpu/arm/cortex-m4/context_rvds.S
+2 -2
View File
@@ -20,7 +20,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2 AREA |.text|, CODE, READONLY, ALIGN=2
@@ -186,7 +186,7 @@ rt_hw_context_switch_to PROC
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
libcpu/arm/cortex-m7/context_gcc.S
+2 -2
View File
@@ -25,7 +25,7 @@
.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
/* /*
@@ -182,7 +182,7 @@ rt_hw_context_switch_to:
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
/* set the PendSV exception priority */ /* set the PendSV and SysTick exception priority */
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] /* read */ LDR.W r2, [r0,#0x00] /* read */
libcpu/arm/cortex-m7/context_iar.S
+2 -2
View File
@@ -21,7 +21,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
SECTION .text:CODE(2) SECTION .text:CODE(2)
@@ -186,7 +186,7 @@ rt_hw_context_switch_to:
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read
libcpu/arm/cortex-m7/context_rvds.S
+2 -2
View File
@@ -20,7 +20,7 @@
SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
AREA |.text|, CODE, READONLY, ALIGN=2 AREA |.text|, CODE, READONLY, ALIGN=2
@@ -186,7 +186,7 @@ rt_hw_context_switch_to PROC
MOV r0, #1 MOV r0, #1
STR r0, [r1] STR r0, [r1]
; set the PendSV exception priority ; set the PendSV and SysTick exception priority
LDR r0, =NVIC_SYSPRI2 LDR r0, =NVIC_SYSPRI2
LDR r1, =NVIC_PENDSV_PRI LDR r1, =NVIC_PENDSV_PRI
LDR.W r2, [r0,#0x00] ; read LDR.W r2, [r0,#0x00] ; read