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https://github.com/RT-Thread/rt-thread.git
synced 2026-05-22 02:21:38 +08:00
set Systick interrupt priority to the lowest
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@@ -24,7 +24,7 @@
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.equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */
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.equ SHPR3, 0xE000ED20 /* system priority register (3) */
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.equ PENDSV_PRI_LOWEST, 0x00FF0000 /* PendSV priority value (lowest) */
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.equ PENDSV_PRI_LOWEST, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */
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/*
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* rt_base_t rt_hw_interrupt_disable();
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@@ -140,7 +140,7 @@ rt_hw_context_switch_to:
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MOV R0, #1
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STR R0, [R1]
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/* set the PendSV exception priority */
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/* set the PendSV and SysTick exception priority */
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LDR R0, =SHPR3
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LDR R1, =PENDSV_PRI_LOWEST
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LDR.W R2, [R0,#0] /* read */
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@@ -19,7 +19,7 @@
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SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
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NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
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NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
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NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
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NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
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SECTION .text:CODE(2)
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@@ -139,7 +139,7 @@ rt_hw_context_switch_to:
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MOV r0, #1
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STR r0, [r1]
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; set the PendSV exception priority
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; set the PendSV and SysTick exception priority
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LDR r0, =NVIC_SYSPRI2
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LDR r1, =NVIC_PENDSV_PRI
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LDR.W r2, [r0,#0x00] ; read
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@@ -18,7 +18,7 @@
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SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register
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NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2)
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NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest)
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NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest)
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NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
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AREA |.text|, CODE, READONLY, ALIGN=2
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@@ -145,7 +145,7 @@ rt_hw_context_switch_to PROC
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MOV r0, #1
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STR r0, [r1]
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; set the PendSV exception priority
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; set the PendSV and SysTick exception priority
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LDR r0, =NVIC_SYSPRI2
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LDR r1, =NVIC_PENDSV_PRI
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LDR.W r2, [r0,#0x00] ; read
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