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[DM/FEATURE] Support PHY (external) (#9597)

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This framework will be of use only to devices that use
external PHY (PHY functionality is not embedded within the controller).

Use in PCIE, USB, HDMI, DP...

Signed-off-by: GuEe-GUI <2991707448@qq.com>
This commit is contained in:
GUI
2024-11-25 10:23:01 +08:00
committed by GitHub
parent 8b4d1c0c5d
commit c2545cdd7b
7 changed files with 466 additions and 0 deletions
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components/drivers/include/drivers/phye.h
+91
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@@ -0,0 +1,91 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2022-10-24 GuEe-GUI first version
*/
#ifndef __PHYE_H__
#define __PHYE_H__
#include <rtthread.h>
#include <drivers/ofw.h>
enum rt_phye_mode
{
RT_PHYE_MODE_INVALID,
RT_PHYE_MODE_USB_HOST,
RT_PHYE_MODE_USB_HOST_LS,
RT_PHYE_MODE_USB_HOST_FS,
RT_PHYE_MODE_USB_HOST_HS,
RT_PHYE_MODE_USB_HOST_SS,
RT_PHYE_MODE_USB_DEVICE,
RT_PHYE_MODE_USB_DEVICE_LS,
RT_PHYE_MODE_USB_DEVICE_FS,
RT_PHYE_MODE_USB_DEVICE_HS,
RT_PHYE_MODE_USB_DEVICE_SS,
RT_PHYE_MODE_USB_OTG,
RT_PHYE_MODE_UFS_HS_A,
RT_PHYE_MODE_UFS_HS_B,
RT_PHYE_MODE_PCIE,
RT_PHYE_MODE_ETHERNET,
RT_PHYE_MODE_MIPI_DPHY,
RT_PHYE_MODE_SATA,
RT_PHYE_MODE_LVDS,
RT_PHYE_MODE_DP,
RT_PHYE_MODE_MAX,
/* PCIe */
RT_PHYE_MODE_PCIE_RC = RT_PHYE_MODE_MAX,
RT_PHYE_MODE_PCIE_EP,
RT_PHYE_MODE_PCIE_BIFURCATION,
};
struct rt_phye_ops;
struct rt_phye
{
struct rt_device *dev;
const struct rt_phye_ops *ops;
int init_count;
int power_count;
struct rt_spinlock lock;
};
struct rt_phye_ops
{
rt_err_t (*init)(struct rt_phye *phye);
rt_err_t (*exit)(struct rt_phye *phye);
rt_err_t (*reset)(struct rt_phye *phye);
rt_err_t (*power_on)(struct rt_phye *phye);
rt_err_t (*power_off)(struct rt_phye *phye);
rt_err_t (*set_mode)(struct rt_phye *phye, enum rt_phye_mode mode, int submode);
rt_err_t (*ofw_parse)(struct rt_phye *phye, struct rt_ofw_cell_args *phye_args);
};
rt_err_t rt_phye_register(struct rt_phye *phye);
rt_err_t rt_phye_unregister(struct rt_phye *phye);
rt_err_t rt_phye_init(struct rt_phye *phye);
rt_err_t rt_phye_exit(struct rt_phye *phye);
rt_err_t rt_phye_reset(struct rt_phye *phye);
rt_err_t rt_phye_power_on(struct rt_phye *phye);
rt_err_t rt_phye_power_off(struct rt_phye *phye);
rt_err_t rt_phye_set_mode(struct rt_phye *phye, enum rt_phye_mode mode, int submode);
rt_inline rt_err_t rt_phye_set_mode_simple(struct rt_phye *phye, enum rt_phye_mode mode)
{
return rt_phye_set_mode(phye, mode, RT_PHYE_MODE_INVALID);
}
struct rt_phye *rt_phye_get_by_index(struct rt_device *dev, int index);
struct rt_phye *rt_phye_get_by_name(struct rt_device *dev, const char *id);
void rt_phye_put(struct rt_phye *phye);
#endif /* __PHYE_H__ */
components/drivers/include/dt-bindings/phye/phye.h
+24
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@@ -0,0 +1,24 @@
/*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __DT_BINDINGS_PHYE_H__
#define __DT_BINDINGS_PHYE_H__
#define PHY_NONE 0
#define PHY_TYPE_SATA 1
#define PHY_TYPE_PCIE 2
#define PHY_TYPE_USB2 3
#define PHY_TYPE_USB3 4
#define PHY_TYPE_UFS 5
#define PHY_TYPE_DP 6
#define PHY_TYPE_XPCS 7
#define PHY_TYPE_SGMII 8
#define PHY_TYPE_QSGMII 9
#define PHY_TYPE_DPHY 10
#define PHY_TYPE_CPHY 11
#define PHY_TYPE_USXGMII 12
#endif /* __DT_BINDINGS_PHYE_H__ */
components/drivers/include/rtdevice.h
+4
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@@ -67,6 +67,10 @@ extern "C" {
#include "drivers/ofw_raw.h"
#endif /* RT_USING_OFW */
#ifdef RT_USING_PHYE
#include "drivers/phye.h"
#endif
#ifdef RT_USING_PIC
#include "drivers/pic.h"
#endif