mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-09-28 16:14:20 +08:00
[bsp] Adapt ls{1b,1c}dev to new mips common code
LS1C selfboot feature have been rewiritten, and we changed bare boot base to 0x80000000 to better utilize memory. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
This commit is contained in:
Jiaxun Yang
+43
-33
@@ -9,108 +9,118 @@ config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../.."
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config PKGS_DIR
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string
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option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$RTT_DIR/libcpu/mips/common/Kconfig"
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source "$PKGS_DIR/Kconfig"
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config SOC_1C300
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bool
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bool
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select RT_USING_COMPONENTS_INIT
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select RT_USING_USER_MAIN
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default y
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choice
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prompt "Board Type"
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config RT_LS1C_OPENLOONGSON
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bool "OpenLoongson Board"
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config RT_LS1C_BAICAIBOARD
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bool "Baicai Board"
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endchoice
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config RT_USING_SELF_BOOT
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bool "Enable RT-Thread run without bootloader"
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default n
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if RT_USING_SELF_BOOT
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config RT_SELF_BOOT_DEBUG
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bool "Debug self boot code"
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default n
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endif
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if RT_USING_SERIAL
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config RT_USING_UART2
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bool "Using RT_USING_UART2"
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default y
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default y
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config RT_USING_UART1
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bool "Using RT_USING_UART1"
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default y
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default y
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config RT_USING_UART3
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bool "Using RT_USING_UART3"
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default n
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default n
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config RT_UART_RX_BUFFER_SIZE
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int "The rx buffer size"
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int "The rx buffer size"
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default 64 if RT_USING_SERIAL
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default 64
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endif
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default 64
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endif
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config RT_USING_GMAC_INT_MODE
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bool "Using RT_USING_GMAC_INT_MODE"
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default y
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config RT_USING_FPU
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bool "Using RT_USING_FPU"
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default y
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config RT_USING_SPI0
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bool "Enable SPI0"
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select RT_USING_SPI
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default y
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default y
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config RT_USING_SPI1
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bool "Enable SPI1"
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select RT_USING_SPI
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default y
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default y
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if RT_USING_I2C
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config RT_USING_I2C1
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bool "Enable I2C1"
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default y
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config RT_USING_I2C2
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bool "Enable I2C2"
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default y
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bool "Enable I2C2"
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default y
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endif
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config USING_BXCAN0
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bool "Enable CAN0"
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select RT_USING_CAN
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default y
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default y
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config USING_BXCAN1
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bool "Enable CAN1"
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select RT_USING_CAN
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default y
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default y
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if RT_USING_CAN
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config RT_CAN_USING_HDR
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bool "Using RT_CAN_USING_HDR"
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select RT_USING_CAN
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default y
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endif
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default y
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endif
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choice
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prompt "Touch format"
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default NO_TOUCH
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config NO_TOUCH
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bool "with no touch"
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bool "with no touch"
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if RT_USING_RTGUI
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config XPT2046_USING_TOUCH
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bool "with XPT2046 touch"
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endif
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endif
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config TINA_USING_TOUCH
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bool "with TINA touch"
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bool "with TINA touch"
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endchoice
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if RT_USING_RTC
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config RT_RTC_NAME
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string "RT_RTC_NAME"
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default "RTC"
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endif
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default "RTC"
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endif
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@@ -16,10 +16,10 @@ rtconfig.AFLAGS += ' -I' + str(Dir('#'))
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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Export('RTT_ROOT')
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@@ -29,9 +29,9 @@ Export('rtconfig')
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objs = PrepareBuilding(env, RTT_ROOT)
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if GetDepend('RT_USING_SELF_BOOT'):
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rtconfig.LFLAGS += " -Ttext 0x80010000"
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rtconfig.LFLAGS += " -Ttext 0x80000000"
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else:
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rtconfig.LFLAGS += " -Ttext 0x80200000"
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rtconfig.LFLAGS += " -Ttext 0x80200000"
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env.Replace(LINKFLAGS = rtconfig.LFLAGS)
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if GetDepend('RT_USING_FPU'):
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@@ -39,9 +39,9 @@ if GetDepend('RT_USING_FPU'):
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env['ASFLAGS'] = env['ASFLAGS'].replace('-msoft-float', '-mhard-float')
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env['CXXFLAGS'] = env['CXXFLAGS'].replace('-msoft-float', '-mhard-float')
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env['LINKFLAGS'] = env['LINKFLAGS'].replace('-msoft-float', '-mhard-float')
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if GetDepend('RT_USING_RTGUI'):
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objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
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# make a building
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DoBuilding(TARGET, objs)
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@@ -1,7 +1,7 @@
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
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CPPPATH = [cwd]
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+14
-79
@@ -8,74 +8,20 @@
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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* 2015-07-06 chinesebear modified for Loongson LS1C
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* 2019-12-04 Jiaxun Yang Adapt new generic MIPS code
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <mips.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "ls1c.h"
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#define A_K0BASE 0x80000000
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extern unsigned char __bss_end;
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extern void tlb_refill_exception(void);
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extern void general_exception(void);
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extern void irq_exception(void);
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extern void rt_hw_cache_init(void);
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extern void invalidate_writeback_dcache_all(void);
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extern void invalidate_icache_all(void);
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/**
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* This is the timer interrupt service routine.
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*/
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void rt_hw_timer_handler(void)
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{
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unsigned int count;
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count = read_c0_compare();
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write_c0_compare(count);
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write_c0_count(0);
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/* increase a OS tick */
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rt_tick_increase();
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}
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/**
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* This function will initial OS timer
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*/
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void rt_hw_timer_init(void)
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{
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write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
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write_c0_count(0);
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}
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/**
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* init hardware FPU
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*/
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void rt_hw_fpu_init(void)
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{
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rt_uint32_t c0_status = 0;
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rt_uint32_t c1_status = 0;
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// 使能协处理器1--FPU
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c0_status = read_c0_status();
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c0_status |= (ST0_CU1 | ST0_FR);
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write_c0_status(c0_status);
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// 配置FPU
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c1_status = read_c1_status();
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c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN); // set FS, FO, FN
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c1_status &= ~(FPU_CSR_ALL_E); // disable exception
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c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN; // set RN
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write_c1_status(c1_status);
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return ;
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}
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#define RT_HW_HEAP_END (0x80000000 + MEM_SIZE)
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/**
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@@ -83,35 +29,24 @@ void rt_hw_fpu_init(void)
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*/
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void rt_hw_board_init(void)
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{
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/* init cache */
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rt_hw_cache_init();
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/* init hardware interrupt */
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rt_hw_interrupt_init();
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/* clear bev */
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write_c0_status(read_c0_status()&(~(1<<22)));
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/* copy vector */
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rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x80);
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rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x80);
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rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x80);
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invalidate_writeback_dcache_all();
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invalidate_icache_all();
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/* init hardware interrupt */
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rt_hw_exception_init();
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/* init hardware interrupt */
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rt_hw_interrupt_init();
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#ifdef RT_USING_HEAP
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rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
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rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
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#endif
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#ifdef RT_USING_SERIAL
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/* init hardware UART device */
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rt_hw_uart_init();
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/* init hardware UART device */
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rt_hw_uart_init();
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#endif
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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/* init operating system timer */
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rt_hw_timer_init();
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@@ -8,15 +8,55 @@
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* 2010-06-25 Bernard first version
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* 2011-08-08 lgnq modified for Loongson LS1B
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* 2015-07-06 chinesebear modified for Loongson LS1C
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* 2019-12-04 Jiaxun Yang Add board config defines
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*/
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#ifndef __BOARD_H__
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#define __BOARD_H__
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#include <rtconfig.h>
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#ifndef __ASSEMBLY__
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void rt_hw_board_init(void);
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#endif
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/* 32M SDRAM */
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#define RT_HW_HEAP_END (0x80000000 + 32 * 1024 * 1024)
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/*
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* SDRAM config
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*
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* Take IS42S16400 SDRAM chip as a example
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* The specfication is
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* Size 8MB
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* WIDTH: 16 bits
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* COL WIDTH: 8 bits, so we should take the 8 power of 2, it's 256
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* ROW WIDTH: 12 bits, so we take the 12 power of 2, it's 4K
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*
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* Please reference macro SD_PARA0 and SDRAM registers intruduction
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* in user's manual to edit the SDRAM config.
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*/
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#if defined(RT_LS1C_BAICAIBOARD)
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/* 8MByte IS42S16400 appeared in bacai_board V1.x V2.x */
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#define MEM_SIZE (0x800000)
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#define SDRAM_WIDTH (WIDTH_16)
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#define SDRAM_COL (COL_256)
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#define SDRAM_ROW (ROW_4K)
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#elif defined(RT_LS1C_OPENLOONGSON)
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/* 32MByte appeared in SmartLoong board */
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#define MEM_SIZE (0x2000000)
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#define SDRAM_WIDTH (WIDTH_16)
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#define SDRAM_COL (COL_512)
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#define SDRAM_ROW (ROW_8K)
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#else
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#error Unknown Board
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#endif
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/* Early Debug config */
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#define EARLY_DEBUG /* UART2 serial print debug in early stage */
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#define EARLY_DEBUG_BAUD (115200)
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/* Clock config */
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#define CPU_HZ (252 * 1000000)
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#define PLL_MULT (0x54) /* When external clock is 24Mhz PLL=504Mhz */
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#define SDRAM_DIV (0) /* SDRAM is CPU divided by 2*/
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#define CPU_DIV (2) /* CPU clock is PLL divided by 2 */
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#endif
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@@ -12,6 +12,7 @@
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#define __DRV_UART_H__
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#include "ls1c.h"
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#include <rthw.h>
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#define DEV_CLK 252000000 // 252MHz
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#define UART_BAUDRATE 115200
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@@ -31,43 +32,43 @@
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#define UART11_BASE 0xBFE4Cb00
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/* UART registers */
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#define UART_DAT(base) __REG8(base + 0x00)
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#define UART_IER(base) __REG8(base + 0x01)
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#define UART_IIR(base) __REG8(base + 0x02)
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#define UART_FCR(base) __REG8(base + 0x02)
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#define UART_LCR(base) __REG8(base + 0x03)
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#define UART_MCR(base) __REG8(base + 0x04)
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#define UART_LSR(base) __REG8(base + 0x05)
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#define UART_MSR(base) __REG8(base + 0x06)
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#define UART_DAT(base) HWREG8(base + 0x00)
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#define UART_IER(base) HWREG8(base + 0x01)
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#define UART_IIR(base) HWREG8(base + 0x02)
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#define UART_FCR(base) HWREG8(base + 0x02)
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#define UART_LCR(base) HWREG8(base + 0x03)
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#define UART_MCR(base) HWREG8(base + 0x04)
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#define UART_LSR(base) HWREG8(base + 0x05)
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#define UART_MSR(base) HWREG8(base + 0x06)
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#define UART_LSB(base) __REG8(base + 0x00)
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#define UART_MSB(base) __REG8(base + 0x01)
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#define UART_LSB(base) HWREG8(base + 0x00)
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#define UART_MSB(base) HWREG8(base + 0x01)
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/* UART0 registers */
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#define UART0_DAT __REG8(UART0_BASE + 0x00)
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#define UART0_IER __REG8(UART0_BASE + 0x01)
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#define UART0_IIR __REG8(UART0_BASE + 0x02)
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#define UART0_FCR __REG8(UART0_BASE + 0x02)
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#define UART0_LCR __REG8(UART0_BASE + 0x03)
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#define UART0_MCR __REG8(UART0_BASE + 0x04)
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#define UART0_LSR __REG8(UART0_BASE + 0x05)
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#define UART0_MSR __REG8(UART0_BASE + 0x06)
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#define UART0_DAT HWREG8(UART0_BASE + 0x00)
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#define UART0_IER HWREG8(UART0_BASE + 0x01)
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#define UART0_IIR HWREG8(UART0_BASE + 0x02)
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#define UART0_FCR HWREG8(UART0_BASE + 0x02)
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#define UART0_LCR HWREG8(UART0_BASE + 0x03)
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#define UART0_MCR HWREG8(UART0_BASE + 0x04)
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#define UART0_LSR HWREG8(UART0_BASE + 0x05)
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#define UART0_MSR HWREG8(UART0_BASE + 0x06)
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#define UART0_LSB __REG8(UART0_BASE + 0x00)
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#define UART0_MSB __REG8(UART0_BASE + 0x01)
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#define UART0_LSB HWREG8(UART0_BASE + 0x00)
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#define UART0_MSB HWREG8(UART0_BASE + 0x01)
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/* UART1 registers */
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#define UART1_DAT __REG8(UART1_BASE + 0x00)
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#define UART1_IER __REG8(UART1_BASE + 0x01)
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#define UART1_IIR __REG8(UART1_BASE + 0x02)
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#define UART1_FCR __REG8(UART1_BASE + 0x02)
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#define UART1_LCR __REG8(UART1_BASE + 0x03)
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#define UART1_MCR __REG8(UART1_BASE + 0x04)
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#define UART1_LSR __REG8(UART1_BASE + 0x05)
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#define UART1_MSR __REG8(UART1_BASE + 0x06)
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#define UART1_DAT HWREG8(UART1_BASE + 0x00)
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#define UART1_IER HWREG8(UART1_BASE + 0x01)
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#define UART1_IIR HWREG8(UART1_BASE + 0x02)
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#define UART1_FCR HWREG8(UART1_BASE + 0x02)
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#define UART1_LCR HWREG8(UART1_BASE + 0x03)
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#define UART1_MCR HWREG8(UART1_BASE + 0x04)
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#define UART1_LSR HWREG8(UART1_BASE + 0x05)
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#define UART1_MSR HWREG8(UART1_BASE + 0x06)
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#define UART1_LSB __REG8(UART1_BASE + 0x00)
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#define UART1_MSB __REG8(UART1_BASE + 0x01)
|
||||
#define UART1_LSB HWREG8(UART1_BASE + 0x00)
|
||||
#define UART1_MSB HWREG8(UART1_BASE + 0x01)
|
||||
|
||||
/* UART interrupt enable register value */
|
||||
#define UARTIER_IME (1 << 3)
|
||||
|
||||
@@ -39,14 +39,6 @@
|
||||
typedef int bool;
|
||||
//typedef unsigned long dma_addr_t;
|
||||
|
||||
//sw
|
||||
/* write/read MMIO register */
|
||||
#define writeb(val, addr) (*(volatile u8*)(addr) = (val))
|
||||
#define writew(val, addr) (*(volatile u16*)(addr) = (val))
|
||||
#define writel(val, addr) (*(volatile u32*)(addr) = (val))
|
||||
#define readb(addr) (*(volatile u8*)(addr))
|
||||
#define readw(addr) (*(volatile u16*)(addr))
|
||||
#define readl(addr) (*(volatile u32*)(addr))
|
||||
|
||||
|
||||
#define KUSEG_ADDR 0x0
|
||||
|
||||
@@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2019, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2019-12-04 Jiaxun Yang Initial version
|
||||
*/
|
||||
|
||||
#ifndef __RT_LS1C_SELFBOOT_H
|
||||
#define __RT_LS1C_SELFBOOT_H
|
||||
|
||||
/* SDRAM PARAM macro */
|
||||
#define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
|
||||
|
||||
|
||||
/* SDRAM ROW */
|
||||
#define ROW_1K 0x7
|
||||
#define ROW_2K 0x0
|
||||
#define ROW_4K 0x1
|
||||
#define ROW_8K 0x2
|
||||
#define ROW_16K 0x3
|
||||
/* SDRAM COL */
|
||||
#define COL_256 0x7
|
||||
#define COL_512 0x0
|
||||
#define COL_1K 0x1
|
||||
#define COL_2K 0x2
|
||||
#define COL_4K 0x3
|
||||
/* SDRAM WIDTH */
|
||||
#define WIDTH_8 0x0
|
||||
#define WIDTH_16 0x1
|
||||
#define WIDTH_32 0x2
|
||||
|
||||
#define TRCD 3
|
||||
#define TCL 3
|
||||
#define TRP 3
|
||||
#define TRFC 8
|
||||
#define TRAS 6
|
||||
#define TREF 0x818
|
||||
#define TWR 2
|
||||
|
||||
#define DEF_SEL 0x1
|
||||
#define DEF_SEL_N 0x0
|
||||
#define HANG_UP 0x1
|
||||
#define HANG_UP_N 0x0
|
||||
#define CFG_VALID 0x1
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#define SD_PARA0 (0x7f<<25 | \
|
||||
(TRAS << 21) | \
|
||||
(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
|
||||
(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
|
||||
SDRAM_ROW)
|
||||
|
||||
#define SD_PARA1 ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
|
||||
|
||||
#define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \
|
||||
(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
|
||||
|
||||
#define LS1C_CBUS_FIRST1 0xBFE011C4
|
||||
#define LS1C_UART2_BASE 0xBFE48000
|
||||
|
||||
/* UART register offset*/
|
||||
#define LS1C_UART_DAT_OFFSET (0)
|
||||
#define LS1C_UART_IER_OFFSET (1)
|
||||
#define LS1C_UART_IIR_OFFSET (2)
|
||||
#define LS1C_UART_FCR_OFFSET (2)
|
||||
#define LS1C_UART_LCR_OFFSET (3)
|
||||
#define LS1C_UART_MCR_OFFSET (4)
|
||||
#define LS1C_UART_LSR_OFFSET (5)
|
||||
#define LS1C_UART_MSR_OFFSET (6)
|
||||
|
||||
#define LS1C_UART_LSB_OFFSET (0)
|
||||
#define LS1C_UART_MSB_OFFSET (1)
|
||||
|
||||
/* interrupt enable register */
|
||||
#define IER_IRxE 0x1
|
||||
#define IER_ITxE 0x2
|
||||
#define IER_ILE 0x4
|
||||
#define IER_IME 0x8
|
||||
|
||||
/* interrupt identification register */
|
||||
#define IIR_IMASK 0xf /* mask */
|
||||
#define IIR_RXTOUT 0xc /* receive timeout */
|
||||
#define IIR_RLS 0x6 /* receive line status */
|
||||
#define IIR_RXRDY 0x4 /* receive ready */
|
||||
#define IIR_TXRDY 0x2 /* transmit ready */
|
||||
#define IIR_NOPEND 0x1 /* nothing */
|
||||
#define IIR_MLSC 0x0 /* modem status */
|
||||
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
|
||||
|
||||
/* fifo control register */
|
||||
#define FIFO_ENABLE 0x01 /* enable fifo */
|
||||
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
|
||||
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
|
||||
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
|
||||
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
|
||||
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
|
||||
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
|
||||
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
|
||||
|
||||
/* character format control register */
|
||||
#define CFCR_DLAB 0x80 /* divisor latch */
|
||||
#define CFCR_SBREAK 0x40 /* send break */
|
||||
#define CFCR_PZERO 0x30 /* zero parity */
|
||||
#define CFCR_PONE 0x20 /* one parity */
|
||||
#define CFCR_PEVEN 0x10 /* even parity */
|
||||
#define CFCR_PODD 0x00 /* odd parity */
|
||||
#define CFCR_PENAB 0x08 /* parity enable */
|
||||
#define CFCR_STOPB 0x04 /* 2 stop bits */
|
||||
#define CFCR_8BITS 0x03 /* 8 data bits */
|
||||
#define CFCR_7BITS 0x02 /* 7 data bits */
|
||||
#define CFCR_6BITS 0x01 /* 6 data bits */
|
||||
#define CFCR_5BITS 0x00 /* 5 data bits */
|
||||
|
||||
/* modem control register */
|
||||
#define MCR_LOOPBACK 0x10 /* loopback */
|
||||
#define MCR_IENABLE 0x08 /* output 2 = int enable */
|
||||
#define MCR_DRS 0x04 /* output 1 = xxx */
|
||||
#define MCR_RTS 0x02 /* enable RTS */
|
||||
#define MCR_DTR 0x01 /* enable DTR */
|
||||
|
||||
/* line status register */
|
||||
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
|
||||
#define LSR_TSRE 0x40 /* transmitter empty */
|
||||
#define LSR_TXRDY 0x20 /* transmitter ready */
|
||||
#define LSR_BI 0x10 /* break detected */
|
||||
#define LSR_FE 0x08 /* framing error */
|
||||
#define LSR_PE 0x04 /* parity error */
|
||||
#define LSR_OE 0x02 /* overrun error */
|
||||
#define LSR_RXRDY 0x01 /* receiver ready */
|
||||
#define LSR_RCV_MASK 0x1f
|
||||
|
||||
|
||||
/* External clock frequency */
|
||||
#define AHB_CLK (24000000)
|
||||
#define APB_CLK (AHB_CLK)
|
||||
|
||||
|
||||
/* START_FREQ register bits */
|
||||
#define M_PLL_SHIFT (8)
|
||||
#define M_PLL (0xff << M_PLL_SHIFT)
|
||||
#define FRAC_N_SHIFT (16)
|
||||
#define FRAC_N (0xff << FRAC_N_SHIFT)
|
||||
#define DIV_SDRAM_SHIFT (0)
|
||||
#define DIV_SDRAM (0x3 << DIV_SDRAM_SHIFT)
|
||||
|
||||
/* CLK_DIV_PARAM register bits */
|
||||
#define DIV_PIX_EN (0x1 << 31)
|
||||
#define DIV_PIX (0x7f << 24)
|
||||
#define DIV_CAM_EN (0x1 << 23)
|
||||
#define DIV_CAM (0x7f << 16)
|
||||
#define DIV_CPU_EN (0x1 << 15)
|
||||
#define DIV_CPU (0x7f << 8)
|
||||
#define DIV_PIX_VALID (0x1 << 5)
|
||||
#define DIV_PIX_SEL (0x1 << 4)
|
||||
#define DIV_CAM_VALID (0x1 << 3)
|
||||
#define DIV_CAM_SEL (0x1 << 2)
|
||||
#define DIV_CPU_VALID (0x1 << 1)
|
||||
#define DIV_CPU_SEL (0x1 << 0)
|
||||
|
||||
#define DIV_PIX_SHIFT (24)
|
||||
#define DIV_CAM_SHIFT (16)
|
||||
#define DIV_CPU_SHIFT (8)
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -12,6 +12,7 @@
|
||||
* 2010-05-17 swkyer first version
|
||||
* 2010-09-04 bernard move the beginning entry to 0x80200000
|
||||
* 2018-05-12 zhuangwei use -Ttext
|
||||
* 2019-12-04 Jiaxun Yang Adapt new memory layout
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
@@ -20,13 +21,19 @@ GROUP(-lgcc -lc)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x80000000 ;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
start = ABSOLUTE(.);
|
||||
*(.start);
|
||||
start = ABSOLUTE(.);
|
||||
*(.selfboot);
|
||||
*(.selfboot_data);
|
||||
. = ALIGN(4);
|
||||
__selfboot_end = .;
|
||||
. = ALIGN(0x1000);
|
||||
__ebase_entry = .;
|
||||
KEEP(*(.exc_vectors))
|
||||
__ebase_end = .;
|
||||
*(.start);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
@@ -74,6 +81,15 @@ SECTIONS
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
}
|
||||
_edata = .;
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
_system_stack_start = .;
|
||||
. = . + 0x400; /* 1kb system stack */
|
||||
_system_stack = .;
|
||||
}
|
||||
|
||||
.sbss :
|
||||
{
|
||||
|
||||
+26
-175
File diff suppressed because it is too large
Load Diff
@@ -2,7 +2,7 @@ import os
|
||||
|
||||
# CPU options
|
||||
ARCH='mips'
|
||||
CPU ='loongson_1c'
|
||||
CPU ='gs232'
|
||||
|
||||
# toolchains options
|
||||
CROSS_TOOL = 'gcc'
|
||||
@@ -12,8 +12,8 @@ if os.getenv('RTT_CC'):
|
||||
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
# EXEC_PATH = "/opt/mips-2015.05/bin"
|
||||
EXEC_PATH = r'D:\mgc\embedded\codebench\bin'
|
||||
EXEC_PATH = "/opt/mips-2016.05/bin"
|
||||
# EXEC_PATH = r'D:\mgc\embedded\codebench\bin'
|
||||
else:
|
||||
print('================ERROR===========================')
|
||||
print('Not support %s yet!' % CROSS_TOOL)
|
||||
@@ -41,7 +41,7 @@ READELF = PREFIX + 'readelf'
|
||||
|
||||
DEVICE = ' -mips32 -msoft-float -mfp32'
|
||||
CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
|
||||
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp -DSYSTEM_STACK=0x80003fe8'
|
||||
AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
|
||||
LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1c_ram.lds'
|
||||
|
||||
CPATH = ''
|
||||
|
||||
Reference in New Issue
Block a user