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add sep4020.h (register address )

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modify serial.c serial.h and clk.c (for compatibility with sep4020.h) 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1294 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
dennis.zhang.os@gmail.com
2011-02-27 13:31:59 +00:00
parent 8ac855d164
commit c217af8061
5 changed files with 987 additions and 84 deletions
Download Patch File Download Diff File Expand all files Collapse all files
libcpu/arm/sep4020/clk.c
+6 -6
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@@ -42,19 +42,19 @@ static void rt_hw_set_system_clock(void)
/* pv value*/
pv = SYSCLK/2/CLK_IN;
/* go to normal mode*/
PMC_PMDR = 0x01;
*(RP)PMU_PMDR = 0x01;
/* set the clock */
PMC_PMCR = 0x4000 | pv;
*(RP)PMU_PMCR = 0x4000 | pv;
/* trige configurate*/
PMC_PMCR = 0xc000 | pv;
*(RP)PMU_PMCR = 0xc000 | pv;
}
static void rt_hw_set_usb_clock(void)
{
/* set the clock */
PMC_PUCR = 0x000c;
*(RP)PMU_PUCR = 0x000c;
/* trige configurate*/
PMC_PMCR = 0x800c;
*(RP)PMU_PMCR = 0x800c;
}
@@ -78,7 +78,7 @@ rt_uint32_t rt_hw_get_clock(void)
rt_uint8_t pv, pd, npd;
/* get PMCR value */
val = PMC_PMCR;
val =*(RP) PMU_PMCR;
/* get NPD */
npd = (val >> 14) & 0x01;
/* get PD */
libcpu/arm/sep4020/sep4020.h
+867
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File diff suppressed because it is too large Load Diff
libcpu/arm/sep4020/serial.c
+60 -59
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File diff suppressed because it is too large Load Diff
libcpu/arm/sep4020/serial.h
+51 -17
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@@ -1,17 +1,53 @@
#ifndef __RT_SERIAL_H__
#define __RT_SERIAL_H__
/*
* File : serial.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://openlab.rt-thread.com/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2006-03-13 Bernard first version
* 2009-04-20 yi.qiu modified according bernard's stm32 version
* 2010-10-6 wangmeng added sep4020 surpport
*/
#include <rthw.h>
#include <rtthread.h>
#ifndef __SERIAL_H__
#define __SERIAL_H__
#include <sep4020.h>
#define USTAT_RCV_READY 0x01 /* receive data ready */
#define USTAT_TXB_EMPTY 0x20 /* tx buffer empty */
#define BPS 115200 /* serial baudrate */
#define USTAT_RCV_READY 0x01 /* receive data ready */
#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */
#define BPS 115200 /* serial baudrate */
#define UART_RX_BUFFER_SIZE 64
#define UART_TX_BUFFER_SIZE 64
/*For sep4020's uart have several secondary function*/
/*we use union to decribe it*/
union dlbl_fifo
{
rt_uint32_t dlbl;
rt_uint32_t rxfifo;
rt_uint32_t txfifo;
};
union dlbh_ier
{
rt_uint32_t dlbh;
rt_uint32_t ier;
};
union iir_fcr
{
rt_uint32_t iir;
rt_uint32_t fcr;
};
struct serial_int_rx
{
rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE];
@@ -24,21 +60,19 @@ struct serial_int_tx
rt_uint32_t write_index, save_index;
};
/* serial port registers */
typedef struct uartport
{
volatile rt_uint32_t dlbl_rxfifo_txfifo;
volatile rt_uint32_t dlbh_ier;
volatile rt_uint32_t iir_fcr;
volatile rt_uint32_t lcr;
volatile rt_uint32_t mcr;
volatile rt_uint32_t lsr;
volatile rt_uint32_t msr;
union dlbl_fifo dlbl_fifo;
union dlbh_ier dlbh_ier;
union iir_fcr iir_fcr;
rt_uint32_t lcr;
rt_uint32_t mcr;
rt_uint32_t lsr;
rt_uint32_t msr;
}uartport;
struct serial_device
{
/* uart hardware registers */
uartport* uart_device;
/* rx structure */
@@ -52,5 +86,5 @@ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t
void rt_hw_serial_isr(rt_device_t device);
#endif
#endif
libcpu/arm/sep4020/start_rvds.S
+3 -2
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@@ -3,7 +3,7 @@
;
; SEP4020 start up code
;
; Change Logs:
; Change Logs:
; Date Author Notes
; 2010-03-17 zchong
;=============================================================================================
@@ -97,7 +97,8 @@ __heap_limit
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
EXPORT Entry_Point
Entry_Point
Vectors LDR PC,Reset_Addr
LDR PC,Undef_Addr
LDR PC,SWI_Addr